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It is VERY OS dependant. What I suggest, if accuracy is required (and the latency is more than your application can tolerate), you keep "a" counter running, from when you issue the interrupt until you can read that counter...so you know how long it took. PCI interrupt latency is not due to the PCI bus at all, that's pretty fast...but the OS can really delay things, especially if your ISR is chained, which the PCI spec requires you to be able to handle... "Speedy Zero Two" <david@manorsway.NOSPAMPLEASE.freeserve.co.uk> wrote in message news:aic9t9$3ra$1@newsg4.svr.pol.co.uk... > Hi group, > I have a PCI design which requires the addition of using the interrupt. > The operation is that the software will write a value to a down counter > which when it reaches zero an interrupt is generated. > Can anyone help as to explain the actual operation and possible problems > associated with the calibration of the "timer" > This delay is used in software timing so I would be interested in any > help/advice > > Thanks in advance > Dave > >Article: 45751
Kevin Neilson <kevin-neilson@removethistextattbi.com> wrote: > 100MHz. > > Worst-case margins are already built into the timing models. But clock jitter isn't. Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 45752
Hi,
I am newbie in the field of FPGAs.. I need some links to Reed-Muller
form and BDDs (Binary Decision Diagrams)
Any help appreciated ..
Thanks and Regards
Sandeep
--
"C is quirky, flawed and an enormous success"
^^^^^^
-- Dennis Ritchie
Article: 45753Hi, I am pretty new to FPGA's. I have a question and i need some one to help me. I have designed a Architecture in VHDL using memories and interconnection matrices and functional units. THe values for these interconnection matrices and the address for the registers in memories comes from a text file ( output of a bunch of C programs that i wrote). Now i need to develop a controller for this and implement this architecture in FPGA ( Xilinix). Now the problem that i am facing is that , " how would i be able to download or include the text file somehow in my program , because that is the file which gives all the important values to my architecture " . Can someone help me out. Thanks, Ram.Article: 45754
yangyugang@263.sina.com (yanggg) wrote in message news:<11a0944b.0208031835.14e8db06@posting.google.com>... > You know the different interface (MII and E1)'s datarate are > different,so when I recive datas I store them in a buffer ,but how to > send them?For example, send 1 byte then change to another E1 > interface,or send 16 byte then change to another E1 interface? > So that is the policy of schedule. > If you have some ideas please contact me. Howdy, Inverse multiplexing is what you are talking about. Commonly called "IMA" in the ATM world (for which there is a standard, defined on the ATM Forum web site), or you can purchase an FPGA core [the sole reason this reply is in the newsgroup]. From the sounds of your description, you are talking as if this is a personal project that you hope to take commerical. Unless you are doing this for purely educational reasons, I highly encourage you to make sure there is really a market for such a device. I find it hard to believe that someone would want to buy 3-4 E1's to transport 10 Mbps Ethernet, but I suppose it's possible. Aren't most people going to 100 Mbps Ethernet? That's 30-50 E1's, depending on how much you want to assume about the traffic patterns. More of a question for the SONET group, but at some point, the cost of a T3 (or E3) will be less than the cost of a large number of E1's. Still doesn't get you anywhere close to 100 Mbps though. So now you need SONET virtual concatenation and bond two T3's together to give you a ~100 Mbps pipe. Unfortunately several telecom equipment vendors have a head start on you: they have, or will soon have, something that fits that description. Good luck, MarcArticle: 45755
Thank You, I needed exactly such information. Regards, MaciekArticle: 45756
Yes. You can (in the EDA Tools section) set up a simulator specific output simulation file, which is a gate level netlist as well. I've used that quite a bit (with Modelsim -> creates a vo file and sdo timing file), and seems to work fine. Cheers, Xanatos "Prashant" <prashantj@usa.net> wrote in message news:ea62e09.0208041608.7e947420@posting.google.com... > Hi, > If I followed the Quartus II flow of compiling a design (includes > synthesis, fitting of the circuit in an FPGA device and timing > analysis) and then simulate the design in Quartus using its own > simulator, would that be considered equal to gate level simulation ? > > Thanks, > PrashantArticle: 45757
I'm having a problem understanding how to use primitives with
Web pack (or Foundation, doesn't matter). I'm sure it's a
generic VHDL question, and it's obvious to everyone here.
Here's the code:
library ieee;
use ieee.std_logic_1164.all;
package matrix_types is
type mtrx_adrs is array (15 downto 0) of std_logic_vector (3 downto 0);
end package matrix_types;
library ieee;
use ieee.std_logic_1164.all, matrix_types.all;
entity bit_matrix16x16 is
port( in_data : in std_logic_vector(15 downto 0);
out_data : out std_logic_vector(15 downto 0);
we : in std_logic;
wclk : in std_logic;
adrs : in mtrx_adrs
);
end entity bit_matrix16x16;
architecture storage of bit_matrix16x16 is
component RAM16X1S
-- pragma translate_off
generic (
-- RAM initialization ("0" by default) for functional simulation:
INIT : bit_vector := X"0000"
);
-- pragma translate_on
port (
D : in std_logic;
WE : in std_logic;
WCLK : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
O : out std_logic
);
end component;
begin
matrix: process (wclk) is
begin
-- Distributed SelectRAM Instantiation
column15: RAM16X1S
port map (
D => in_data(15), -- insert input signal
WE => we, -- insert Write Enable signal
WCLK => wclk, -- insert Write Clock signal
A0 => adrs(15)(0), -- insert Address 0 signal
A1 => adrs(15)(1), -- insert Address 1 signal
A2 => adrs(15)(2), -- insert Address 2 signal
A3 => adrs(15)(3), -- insert Address 3 signal
O => out_data(15) -- insert output signal
);
:
:
And here's the error:
Compiling vhdl file C:/Xilinx/bin/matrix_test/bit_matrix16x16.vhd in
Library work.
ERROR:HDLParsers:3324 - C:/Xilinx/bin/matrix_test/bit_matrix16x16.vhd
Line 59. IN mode Formal d of ram16x1s with no default
value must be associated with an actual value.
ERROR:HDLParsers:162 - C:/Xilinx/bin/matrix_test/bit_matrix16x16.vhd
Line 60. Read symbol PORT, expecting ';'.
WARNING:HDLParsers:901 - C:/Xilinx/bin/matrix_test/bit_matrix16x16.vhd
Line 59. Label column15 is ignored.
:
:
The component part was just cut and pasted from the Xilinx
and it seems to me that in_data is a formal signal. But it
still doesn't like me. What am I doing that's stupid?
Patience, persistence, truth,
Dr. mike
--
Mike Rosing
www.beastrider.com BeastRider, LLC
SHARC debug tools
Article: 45758
A sample of one or two running on the bench is sufficient (and advisable) to
verify function, but not timing. It is not very likely to have the design in
your lab hit the worst case corner for temperature, voltage and process. A
static timing analysis must be run to tell you your margins. Empirical testing
does not give a sufficient sample size, plus the sample is probably not a
representative one because the lab is usually more tightly controlled conditions,
and the test articles probably have parts from the same chip lots.
Clock jitter must also be considered, as it is not included in the worst case
timing numbers.
Finally, the amount of slack you do have is highly dependent on the exact nature
of your design. Not every path is a critical path, although it may be considered
that way by the timing analysis. If your design has hidden slack (extra slack
time not included in the timing constraints), exceeding your timing budget on
some paths may not cause a detectable failure.
Jim Granville wrote:
> Peter Baltazarovic wrote:
> >
> > Hello to everybody,
> >
> > I would like to know that if I want my design to be run at say 100 MHz,
> > for what speed should it be synthesized to be safe, stable and workung? I
> > mean 1%, 2% above 100 MHz?
>
> If things are looking tight, it is worthwhile to also run a HW test, to
> make sure your are 'well clear' of 100MHz on the test bench.
> ( worst case is Vcc and Temp corner qualified, so a bench test should
> not fail at 102MHz )
>
> The 'Rely on SW' pathway is fine in theory, but a bench reality
> check is the true yardstick. ( bit like Opinion Polls and Elections .. )
>
> -jg
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 45759Sylvain Yon wrote: > Mike Rosing <rosing@neurophys.wisc.edu> wrote in > >>architecture storage of bit_matrix16x16 is >> >> component RAM16X1S >> >>begin >> >> matrix: process (wclk) is >> >> begin >> >> -- Distributed SelectRAM Instantiation >> column15: RAM16X1S >> port map ( >> >> > > > I think it's a copy/paste artefact, but is your component instantiated > inside the 'matrix' process? I don't think it's a legal in vhdl, and is > probably misinterpreted by ths synthetizer. Yes, that's where I'm trying to put it. I guess that's not allowed? So I need to declare the entities outside the process, and in this case I'm just creating a storage object, so there's no process to really do. I'll try that, thanks!! Patience, persistence, truth, Dr. mike -- Mike Rosing www.beastrider.com BeastRider, LLC SHARC debug toolsArticle: 45760
Sylvain Yon wrote: > I often refer to this page, when I have a doubt about vhdl constructs > > http://www.ami.bolton.ac.uk/courseware/adveda/vhdl/vhdlbnf.html Thanks, that looks like a good reference. I got past that mistake, and I think I see what the compiler is doing now. My next question may be more Xilinx specific: How do I tell it that some signals are internal? I've got a huge number of signals that it automaticly connected to IOB's, and I assume I can attach some of them that I really want using obuf's. But how do I tell it not to connect signals to IOB's? Patience, persistence, truth, Dr. mike -- Mike Rosing www.beastrider.com BeastRider, LLC SHARC debug toolsArticle: 45761
Mike Rosing wrote: > Sylvain Yon wrote: > >> I often refer to this page, when I have a doubt about vhdl constructs >> >> http://www.ami.bolton.ac.uk/courseware/adveda/vhdl/vhdlbnf.html > > > Thanks, that looks like a good reference. > > I got past that mistake, and I think I see what the compiler is doing > now. My next question may be more Xilinx specific: How do I tell it > that some signals are internal? I've got a huge number of signals that > it automaticly connected to IOB's, and I assume I can attach some of > them that I really want using obuf's. But how do I tell it not to > connect signals to IOB's? > > Patience, persistence, truth, > Dr. mike > I think I figured out how to answer this, any other comments appreciated tho! I need to use the "attribute iob : string;" statement in the entity or architecture header, and then say attribute iob of <signal name> : signal is "false"; and that should fix my problem. Patience, persistence, truth, Dr. mike -- Mike Rosing www.beastrider.com BeastRider, LLC SHARC debug toolsArticle: 45762
mrand@my-deja.com (Marc Randolph) writes: >yangyugang@263.sina.com (yanggg) wrote in message news:<11a0944b.0208031835.14e8db06@posting.google.com>... >> You know the different interface (MII and E1)'s datarate are >> different,so when I recive datas I store them in a buffer ,but how to >> send them?For example, send 1 byte then change to another E1 >> interface,or send 16 byte then change to another E1 interface? >> So that is the policy of schedule. >> If you have some ideas please contact me. >Inverse multiplexing is what you are talking about. Commonly called >"IMA" in the ATM world (for which there is a standard, defined on the >ATM Forum web site), or you can purchase an FPGA core [the sole reason >this reply is in the newsgroup]. >From the sounds of your description, you are talking as if this is a >personal project that you hope to take commerical. Unless you are >doing this for purely educational reasons, I highly encourage you to >make sure there is really a market for such a device. I find it hard >to believe that someone would want to buy 3-4 E1's to transport 10 >Mbps Ethernet, but I suppose it's possible. Aren't most people going >to 100 Mbps Ethernet? That's 30-50 E1's, depending on how much you >want to assume about the traffic patterns. >More of a question for the SONET group, but at some point, the cost of >a T3 (or E3) will be less than the cost of a large number of E1's. >Still doesn't get you anywhere close to 100 Mbps though. So now you >need SONET virtual concatenation and bond two T3's together to give >you a ~100 Mbps pipe. Unfortunately several telecom equipment vendors >have a head start on you: they have, or will soon have, something that >fits that description. I believe that this is always done through a router, instead of a bridge as the original question asked. A bridge will pass broadcast traffic, where a router (normally) won't. There are bridges and routers that do link aggregation, at least for multiple ethernet links, and I would presume also for T1 or E1. Because of the cost, it is not normal to try to match the ethernet speed. The assumption is that the actual need is much less than 10 or 100 megabits/second. For a LAN, the extra cost of a faster link is fairly small. This is not true for WAN links, though. Most likely there are already enough commercial devices. If this is for educational purpose, that is fine. You can run 10 E1 lines across the room for a reasonable price. You should still have the CSU/DSU (the device that can drive the signal though km's of cable and recover it at the other end). For short distance, though, you could get away with somewhat less, or maybe even none at all. Please describe the goals of the project, and we will have a better idea what to recommend. Also, look up "link aggregation" somewhere. -- glenArticle: 45763
At first I would like to thank to all of you for sharing your knowledge :-) You know, I don't have any practical experiences with real FPGA device (I didn't test any of my designs in real world, because i don't have such possibility now). Now I am trying to understand architecture of Xilinx SpartanII FPGA and learning to design FPGAs in theory. And this forum helps me a lot. Thanks again. :-)Article: 45766
Dear all, I know that there is a "starter version" of modelsim which is free. Where can i download and get the licence for "starter version"?? Thank a lot. RealaArticle: 45767
I posted this a while back, but haven't received any response.
When I produce the EDIF from Celoxica DK1.1 for the following code, I get a
single net that has no load. I cannot understand why this would be.
Any assistance appreciated.
Regards,
Elliot.
==========================
set clock = external ("P80");
unsigned int 1 bus_outtext;
interface bus_clock_in (unsigned int 1 pt) if_inputText() with {data =
{"P3"}};
interface bus_out () outputText(unsigned int 1 outtext = bus_outtext) with
{data = {"P5"}};
ram unsigned 1 rs[1];
void main () {
rs[0] = if_inputText.pt;
bus_outtext = rs[0];
}
Article: 45768Hi, I developed a design using two 22V10 using WARP by Cypress. Now, in the production phase, we would like to use the GAL by ATMEL, I tryed to use the ATMEL development sw but I am encontering a lot of problem to pass the Cypress VHDL description. After a lot of time I was able to pass the VHD source to an ATMEL program named PeakFPGA but this program will not produce the .JED file needed to the programmer. Is there someone able to help me with another more friendly tools or with a tool to pass the .Jed produced by WARP to the .Jed required by ATMEL (it seems that the two .jed are not equal). Thank you in advance -- ------------------------------------------------------------------------ ** Maurizio Stefani **Research&Development Manager ** ** ELE.SI.A. S.r.l. ** ISO 9001 CERTIFIED ** Tel. 39.06.8813320 (Int. 221) / Fax 39.06.8813352 ** http://www.elesia.it ------------------------------------------------------------------------Article: 45769
"Ramakrishnan" wrote > that , " how would i be able to download or include the > text file somehow in my program Which program? It's a hardware description. You can define a constant in your package. An array of integer which holds your values, or a std_logic_vector which holds your data in the form of zeros and ones. Then the syntheziser extracts a rom, which holds your data. Greetings, HolgerArticle: 45770
"Reala" <manfield.chow@scoreconcept.com> wrote in message news:ailbdp$n739@imsp212.netvigator.com... > Dear all, > > I know that there is a "starter version" of modelsim which is free. > Where can i download and get the licence for "starter version"?? > Thank a lot. http://www.xilinx.com XE stands for 'Xilinx Edition'. Leon -- Leon Heller, G1HSM leon_heller@hotmail.com http://www.geocities.com/leon_hellerArticle: 45771
Hi, does anybody know if there exists an FPGA soundchip? Maybe with FM synthesis? TIA Tim -- Tim Riemann octoate@-SPAMREMOVE-.tcs-software.deArticle: 45772
Hi, I have been simulating the gate level netlists the modelsim way, just as you suggest. But I wanted to confirm if the Quartus approach was what I thought. Also, I understand that with modelsim you should use the .sdo file. But is this file taken into consideration when working the Quartus way ? Thanks, Prashant "Xanatos" <fpsbb98@yahoo.com> wrote in message news:<S6k39.278432$WJf1.96674@news01.bloor.is.net.cable.rogers.com>... > Yes. > > You can (in the EDA Tools section) set up a simulator specific output > simulation file, which is a gate level netlist as well. I've used that quite > a bit (with Modelsim -> creates a vo file and sdo timing file), and seems to > work fine. > > Cheers, > Xanatos > > "Prashant" <prashantj@usa.net> wrote in message > news:ea62e09.0208041608.7e947420@posting.google.com... > > Hi, > > If I followed the Quartus II flow of compiling a design (includes > > synthesis, fitting of the circuit in an FPGA device and timing > > analysis) and then simulate the design in Quartus using its own > > simulator, would that be considered equal to gate level simulation ? > > > > Thanks, > > PrashantArticle: 45773
It Ain't Gonna Happen. I'm guessing you're trying to put 2x 22V10's into one Atmel-750. You will have to build a new architecture for the new part, cut and past the bits of logic from your working design to this one, fix the VHDL problems, re-simulate and re-compile. Have fun, SH7 On Mon, 5 Aug 2002 11:35:53 +0200, "Maurizio Stefani" <mstefani@elesia.it> wrote: >Hi, > >Is there someone able to help me with another more friendly tools or with a >tool to pass the .Jed produced by WARP to the .Jed required by ATMEL (it >seems that the two .jed are not equal). >
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