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Diab C/C++ compiler is the tool for embedded applications targeting to the PowerPC inside Virtex-II Pro. After the compilation, the embedded system dev tool chain can initialize the program memory or load the program memory with the executables, then PPC can execute the program. It is not a 'synthesis' tool that manipulate C/C++ into the fabric. -Winnie Kaplan wrote: > What exactly does the Wind River Diab XE compile down to? Does it > target the Virtex II-Pro core PowerPC, or does it actually manipulate > the FPGA fabric? > Any help understanding this will be most appreciated. > > Thanks!Article: 45501
I need someone to do a small design and prototype building job using a Programmable Gate Array. I am in Sydney Australia please email me at peter.boot@ihug.com.auArticle: 45502
Now come on Ray. You know that was worth at least $1.98. I guess you were having a special? Thanks for the tips. Ray Andraka wrote: > > My 2 cents worth on this thread: > > First, some tools such as synplify will infer the SRL16's, and will even put a > register at the output, which improves the clock to Q considerably. What it does > not do well is adding a register between each SRL16 in the chain. Personally, I > prefer to instantiate them using the SRL16 primitive in the unisim library. That > way I can put the registers between where they belong, and If I want I can add RLOCs > as well as non-zero initial values. Set the timingcheckson generic to false (it > defaults to true) to avoid problems in functional simulation, and put the generics > inside a syn_translate pragma to avoid possible problems with inference as a black > box. Only the output of a register or the flip-flop following it (if you put them > in there, which I advise) are visible. If you need to get somewhere in between, > then you'll need to adjust your delays to get to the tap you desire. VirtexII has a > nice feature that adds an always available output out of the last tap useful for > cascade chains. If you dynamically control the shift length, you'll probably want > to split up and duplicate the address drivers. > > If you were not using the block RAMs for something else, you could use them in 16 > bit wide mode as a delay queue by using one port for read and one for write. The > read address and write address have to be offset for it to work correctly. > Depending on your data rate frequency, you may also be able to run the BRAM on a 2x > or even 4x clock in order to get 2 accesses per clock in order to double the > available width. At 1x, and with a 64 deep queue, you can only use 1/4 of the > memory per block RAM, so a 4x memory clock would be ideal provided it does not > exceed the capabilities of the BRAM. > > John_H wrote: > > > Go to http://toolbox.xilinx.com/docsan/xilinx4/manuals.htm and look at the > > "Libraries Guide" which has all the primitives listed. You can use an SRL16 > > with or without enable. > > > > Of you need to tap off a fixed diagonal, the task is pretty straightrorward but > > the coding (3 levels of module hierarchy) isn't as clean. Do you know about > > parameterized modules? > > > > You can have a chain of 4 SRL16s to get your 64 bit delay. To "tap" an element > > in the middle at a fixed address, you can either daisy-chain two shorter SRL16s > > together (you can program them for delays of 1 to 16, inclusive) or you can tap > > off the feed between the 16 long delays and feed an SRL16 in parallel with the > > fixed chain. You can hard code the address or select which of those 16 taps you > > want dynamically if necessary (but the bits that make the selection could have a > > HUGE fanout! 384 bits?!). > > > > John Hovell wrote: > > <excerpt> > > > > > I'm hunting around right now for the instatiation syntax for an SRL's on the > > > net... Is there a primative that I can call so one of these is inferred? It > > > seems the PRNG (Xilinx app 211) just uses some fancy compiler ifdef > > > statements to get the right piece of hardware inferred. I'm sure I can find > > > this info on the 'net so I don't want to bother anyone with simple > > > questions... however if someone feels compelled to clue me in, I certainly > > > won't mind ;-). > > > > > > The only reason SRL's might not work is that I need to read *some* values in > > > the delay pipe (i.e. the first column and a sort of diagonal row through the > > > first half of it: Total bits: 384*2 = 768). Hopefully I can read values > > > that are in the shift registers.... > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 45503
Uwe Bonnes wrote: > > Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> wrote: > : Klaus Vestergaard Kragelund <KlausKVIK@hotmail.com> wrote: > > : : Yes. The comparator is checking the status of the output of a fast 8bit ADC > : : (80MSa/s). The purpose of looking at the data is to provide a digital > : : trigger signal (like the analog one you would use in a analog oscilloscope). > : : When the trigger signal arrives a counter counts down to zero storing data > : : in the SRAM memory and stops when zero is reached. > > ... > > : Yes, either interleaf or pipeline. > > Experimenting a little more, what about registering both input, comparing the > registered values and registering the result. That way you get a pipeline > delay of two clock, but the design fit reports a maximum clock of 93 MHz, > 3.5 ns Clock to Output delay and 3.7 ns Setup for the Input. > > Bye > -- > Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- I don't know the part in question all that well, but if it is a CPLD type part, the performance hinges on keeping the logic for any one FF in a single macrocell. I am pretty sure you can get to 200 MHz that way. Most macrocells have at least 8 inputs, so it would be simple to design a compare circuit that compares two four bit hunks in the first cell (lsbs) which feeds to a second cell. If that cell can handle at least 9 bits in, then you compare the remaining 4 bits and gate with the output from the 4 lsbs. This should get you the full speed of the part. Of course this also assumes the inputs are registered. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 45504
Hi I need a 8bit magnitude comparator (just A>B). I can buy a 74AS885 from TI for 8$, but my question is if this can be done/fit in a XC9536XL/XC9572XL Xilinx CPLD part while keeping the delays at 5ns? Thanks KlausArticle: 45505
Dear Kevin, Thank you for your detailed reply. I am now more understand about FPGA/ASIC design. Thank a lot ^_^ Reala "Kevin Brace" <killspam4kevinbraceusenet@killspam4hotmail.com> wrote in message news:ahn6d7$bnn$1@newsreader.mailgate.org... > > > > Reala wrote: > > > > Dear Kevin, > > > > Thank you for your detailed reply. > > Actually, I work in a IC design company. My boss want to develop a low-end > > DSP chip. However, we are less experience in this. > > We think that one of the important building block is 16X16 small size, > > single cycle multiplier. > > I write simple verilog and synthesis by Xilinx Web pack tools. It seems that > > work. > > Assuming it is work, I want to open some output files to see what "circuit" > > is synthesised, because I will design a DSP chip. But i do not know which > > output files mention the netlist of the "systhesised design" in gate level. > > > > > I will assume that you are trying to develop a 16 X 16 > multiplier IP core. > When doing that, you should turn off (uncheck) "Add I/O Buffer" option > (Or something that sounds like that.) of the synthesis tool, so that the > multiplier block can be attached to rest of the logic. > When using the multiplier IP core from another design, you will need to > instantiate a blackbox of it when synthesizing that design, and also > tell NGDBUILD where the netlist of the multiplier IP core is located. > > > > > I guess that the verilog code will be synthesised by synthesis according to > > synthesis tool's library. Am I correct? Can i force the synthesis tool to > > synthesis the verilog code without using library? (I means the design is > > systhesis in gate level ...AND OR XOR.....) Then, can i see the netlist in > > gate level such that I can study the design synthesised by the synsthesis > > tool? > > > > > Assuming that you are using ISE WebPACK's synthesis tool XST, > you cannot do that because it doesn't support schematic viewing of the > synthesized design, although I heard a rumor recently that the soon to > be released ISE 5.x will support this feature (I believe a Xilinx > employee said so in this newsgroup recently.). > If you are willing to pay for Synplify or LeonardoSpectrum, I believe > they have the capability to let you see the gate level equivalent of the > synthesized design. > The reason I just said, "the gate level equivalent of the synthesized > design" is because in Xilinx FPGAs, LUT (Look Up Tables) emulate logic > gates (AND, OR, NOT, XOR, etc.) > Normally, if you ask a Xilinx about looking at the netlist > generated by XST, they will tell you that, "Sorry, XST of ISE 4.x can > only generate an encrypted netlist (.NGC file). To generate an EDIF > netlist (.EDN or .EDF), you will have to buy a third-party synthesis > tool," but following the instructions of the posting I made, you will be > able to generate an EDIF netlist from XST. > > http://groups.google.com/groups?hl=en&lr=&ie=UTF-8&threadm=aceeac%249fj%241% 40newsreader.mailgate.org&rnum=1&prev=/groups%3Fq%3DBrace%2BEDIF%2BXST%26hl% 3Den%26lr%3D%26ie%3DUTF-8%26selm%3Daceeac%25249fj%25241%2540newsreader.mailg ate.org%26rnum%3D1 > > > Again, in Xilinx FPGA synthesis tools, gates (AND, OR, NOT, XOR, > etc.) get converted to LUTs, so having an EDIF netlist still won't help > you see the gate-level representation of the synthesized circuit. > > > > > You say that: > > >To make sure the synthesized design was synthesized correctly, > > >do a gate-level simulation of the synthesized design. > > >You should be able to run the same testbench code you used for an RTL > > simulation. > > > > I am not really understand because I am a beginner of IC design. > > what is the meaning of gate-level simulation? by what kind of tools? > > Modelsim? Xilinx? or other? > > > > > Gate-level simulation in this case means a post synthesis > simulation (Xilinx calls it "Post translate simulation."). > What you are trying to do is to make sure the synthesis tool correctly > converted your synthesizable RTL (Register Transfer Level) code to > gates. > Although it doesn't happen that often, synthesis tools do have bugs, and > messes up the synthesis. > If you are a beginner (I think you mentioned that.), try using > ModelSim XE-Starter that comes with ISE WebPACK for simulating your > design. > The only limitation of ModelSim XE-Starter is that the simulation slows > down after 500 lines of code, but it still simulates your design even if > you exceed the limit. > > > > > > What is RTL (Register Tran...Logic) I know the name but not really know the > > meaning? What tools for RTL synthesis? > > > > Thank again ^_^ > > Reala > > > > > RTL stands for "Register Transfer Level." > Someone else already explained what it is, so I won't get into that > here. > If you are using ISE WebPACK, XST (Xilinx Synthesis Technology) is the > synthesis tool you have been using. > There are other synthesis tools like Synplicity's Synplify, Mentor > Graphics LeonardoSpectrum, and Synopsys FPGA Compiler II. > > > > Kevin Brace (In general, don't respond to me directly, and respond > within the newsgroup.)Article: 45506
Hi,
I serached the related web sites, but cannot find it or
found isn't suitable for me. Plz tell kindly me.
Thanks!
Article: 45507Klaus Vestergaard Kragelund wrote: <SNIP> > Thanks for the fast response. I a newbee at PLD design - it is correct to > say that each XOR of a bit will "occupy" a PLD register and the final > compare of these 8 XOR outputs needs another register - using a total of 9 > macrocells in a Xilinx CPLD? There are many possible packings/mappings: ( This assumes two variables compared, if the Trigger can be 'hard coded' as a constant, these reduce further ) 8 x XOR = 2 Product Terms wide, then an 8 PT wide merge, for '>' create, does this in 9 MCells, and 24 PT. Some of the Equ nodes can be collapsed, to something like 3 MCells of 16.16.15 PT each. ( plus there are many options in-between..) It depends on the CPLD, and the PT width per macrocell, and the cost of 'widening that'. You may decide that for a trigger, you do not need full 8 bits wide, which can also reduce resource. > > Could you recommend a good reference or book on the practical > inplementations of logic into programmable ICs? For things like adders/comparitors, a TTL Reference manual is good, as you need to shuffle the nodes and logic to most efficently pack into CPLDs. -jgArticle: 45508
"John_H" <johnhandwork@mail.com> wrote in message news:3D3F11E8.EC4A61A1@mail.com... > If there's anything in your system that would allow a different look at > things, you might achieve your end goal. I don't think you can do a straight > 8 bit A vs B in anywhere close to 5ns because of the cascade of logic > required. If you're comparing to a constant, however, the situation could > turn to your favor. If you can register the comparison and get the result on > the next clock, there are more possibilities still. > > Any room for relaxing the spec? > Yes. The comparator is checking the status of the output of a fast 8bit ADC (80MSa/s). The purpose of looking at the data is to provide a digital trigger signal (like the analog one you would use in a analog oscilloscope). When the trigger signal arrives a counter counts down to zero storing data in the SRAM memory and stops when zero is reached. I need a CPLD anyway to divide the datastream into two 8bits words at 40MHz instead (the SRAM gets cheaper and the external design-constrains get simpler). I may even go for 4 8bit words at 20MHz because I would like to be able to drop-in a faster ADC at some time. So perhaps two 8 bit comparators each clocked at 40MHz? That should be doable? Anyway of doing another trick? Also the response need not be superfast - it just has to trigger a output if a certain value is exceeded. Thanks Klaus > > > Klaus Vestergaard Kragelund wrote: > > > Hi > > > > I need a 8bit magnitude comparator (just A>B). I can buy a 74AS885 from TI > > for 8$, but my question is if this can be done/fit in a XC9536XL/XC9572XL > > Xilinx CPLD part while keeping the delays at 5ns? > > > > Thanks > > > > Klaus >Article: 45509
"Uwe Bonnes" <bon@elektron.ikp.physik.tu-darmstadt.de> wrote in message news:ahn3d3$601$1@news.tu-darmstadt.de... > Klaus Vestergaard Kragelund <KlausKVIK@hotmail.com> wrote: > : Hi > > : I need a 8bit magnitude comparator (just A>B). I can buy a 74AS885 from TI > : for 8$, but my question is if this can be done/fit in a XC9536XL/XC9572XL > : Xilinx CPLD part while keeping the delays at 5ns? > > I just checked witch the simple verilog statement and got following result: > > Synthesizing Unit <magcomp>. > Related source file is magcomp.v. > Found 8-bit comparator greater for signal <c>. > Summary: > inferred 1 Comparator(s). > Unit <magcomp> synthesized. > > cpldfit: version E.38 Xilinx Inc. > Fitter Report > Design Name: magcomp Date: 7-24-2002, 10:23PM > Device Used: XC9536XL-5-PC44 > Fitting Status: Successful > > Performance Summary: > > Pad to Pad (tPD) : 10.1ns (2 macrocell levels) > Pad 'a<1>' to Pad 'c' > > -------------------------------------------------------------------------- ------ > Pad to Pad (tPD) (nsec) > > \ From a a a a a a a a b b b b > \ < < < < < < < < < < < < > \ 0 1 2 3 4 5 6 7 0 1 2 3 > \ > > > > > > > > > > > > > \ > \ > \ > To \------------------------------------------------------------------------ > > c 10.1 10.1 9.4 6.0 5.7 5.7 9.4 9.4 10.1 10.1 10.1 6.0 > > -------------------------------------------------------------------------- ------ > > So it seem you don't meet your spec with that simple approch. As synthesize > inferred a comparator, I guess it is quite optimized.. > Thanks for the fast response. I a newbee at PLD design - it is correct to say that each XOR of a bit will "occupy" a PLD register and the final compare of these 8 XOR outputs needs another register - using a total of 9 macrocells in a Xilinx CPLD? Could you recommend a good reference or book on the practical inplementations of logic into programmable ICs? Cheers Klaus > Btw: A 16 bit comparator has the same seed... > > Bye > > -- > Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 45510
> In your post, you say:
> > Webpack will only target Xilinx's FPGA parts, which means it'll always
> > target some kind of Xilinx primitives library. (That's mostly the LUT4
> > cell primitive.) Someone correct me if I'm wrong If your ASIC-vendor
> > truly offers a 'FPGA->ASIC conversion flow', they surely will accept the
> > Xilinx netlist 'as is.' The ASIC-vendor will worry about the logical
> > remapping between FPGA-library and ASIC-library.
>
> If the netlish including LUT4, then, how to change this into "circuit" when
> I implement this in ASIC? Is it done by ASIC-vender? You says that
> ASIC-vender will worry remapping?
As I stated, the companies who offer an 'FPGA->ASIC conversion service'
will usually handle the conversion as part of the service. You might
want to take a look at www.atmel.com and www.flextronics.com -- both
companies offer 'FPGA->ASIC conversion services.' Both companies will
directly accept a Xilinx netlist (they want EDIF format instead of
Verilog.
I know the commercial Xilinx Foundation ISE can generate the EDIF file,
but I'm not familiar with Webpack.)
Read each company's product brochure. Each company presents a
high-level
overview of their conversion service. I think this will answer many of
your questions.
> So, what is the normally development flow
> for ASIC starting at Verilog?
Starting from the beginning, here's an typical flow. Note that
development flows vary from company to company, and even project to
project within the same company. The 'exact' flow depends on
the project's requirements and perhaps resource availability.
#1) 'functional specification.'
Your functional specification describes the circuit's function in
abstract or general terms. For example, given an input 'X', the
DSP will perform some mathematical operation 'A', in order to
produce a final output 'Y'. "Y[n] = A * X[n];"
#2) Develop a hardware architecture for your functional spec. Now
you're starting to partition the DSP's mathematical formulas
into hardware building blocks, i.e., physical structures which
implement the specified function.
At this stage, you might decide 'ok, we need several multipliers,
adders, a register file, and the control unit.' You've named the
major architectural components of the DSP, but so far, you haven't
actually built anything yet.
Sometimes, companies will run hardware-simulations at this stage.
These 'behavioral' simulations use abstract models of the device
under test. A behavioral sim is sometimes used as a way to
explore alternative architectures (for example, what if you
want your DSP to have 2 multiply units instead of 1.) They
can offer a rough estimate of your system's performance, and
therefore can identify potential weaknesses or troublespots
in the design's high-level architecture.
(Ideally, you'd want to correct architectural problems *HERE*,
before you start implementing the real hardware.)
#3) *** Implement design *** Here's where you start writing your
Verilog RTL-code. Now you worry about things on a clock-cycle to
clock-cycle basis. For example, perhaps you've budgeted 1-clock
to fetch and decode an 'instruction,' 1 more clock for a multiply
operation, and 1 last clock to sum the product with an accumulator.
<<<Answer to your question after down below >>>
#4) Verify the design. Instantiate your DSP-processor in some
'testbench
environment.' Drive inputs into your DSP-model, then observe the
outputs. From your functional spec (step #1), you know the
expected output. Compare the expected-output with your simulation
output. Do they agree? No, time to go back and do some debugging.
Yes, ok ready to move to the next step.
Simulations run at this stage are often called 'RTL simulations'
(because they check the unsynthesized RTL-code.) Sometimes
engineers
call these 'functional simulations', because the RTL-code is
considered a functional description of the design.
#5) Synthesize the RTL-code into a 'gate netlist.'
The transformation your design from functional-code to a more
"physical
form" starts with the synthesis step.
The synthesis step accomplishes the following:
maps the RTL-code to a specific "ASIC process"
converts RTL-statements into elementary gates (which are part of
the "technology library")
#6) verify the synthesized netlist's 'logical equivalence.'
If your RTL multiplier performs "Z = X * Y;", you want to check the
netlist to ensure it's doing the same thing. Rarely, synthesis
tools can make logical mistakes. More often, the RTL-code has some
bug which doesn't show up with functional-simulations, yet causes
a problem during synthesis.
...
Steps #1-6 are fairly generic and apply to any type of logic design
(CPLD, FPGA, ASIC, etc.)
At this point, you have several choices...
You could either
(A) Tackle the 'back-end' (physical) design process yourself.
1) placement tool to map your gates to a geographical location on
the silicon die.
2) routing tool to connect the gates' input/outputs (with wires)
3) design-rule check on the
4) check 'timing' (the post-layout netlist has 'annotated delay'
information.)
After place/route, some nets have extra delay (due to distance
or other physical attributes). The net effect is a
performance deterioration (compared to the synthesis tool's
timing report.) Most people use a static-timing analysis tool
to ensure the setup/hold requirements on all flipflops still
fall within spec.
5) LVS/DRC (I don't know what these are...I think these are final
layout rule checks. ASIC processes generally have complicated
layout rules like 'wires must be a certain spacing from each
other, wires beyond a certain width must be slotted, no logic
allowed too close to I/O pads, etc. A good layout tool will
(from step #1 and 2) will produce very few LVS/DRC errors.
These errors are sometimes fixed manually (by hand.)
Some extra issues : testing? How will you check a
manufactured chip for defects? Most people add a 'built in self
test'
(BIST) to their chip design. The BIST circuit lets the foundry
diagnose the raw manufactured chips for defects. Defect chips are
thrown away (before packaging and assembly...)
(B) You've decided that 'back-end' work is too much for your company.
So you pick an ASIC-foundry who offers 'backend services' (LSI,
IBM,
Atmel, TI, etc.)
Instead of worrying about all the stuff I just described, you give
the foundry your synthesized netlist (from step #5). The foundry
takes care of the rest. If you're lucky, no problems will arise
during the foundry's back-end workflow, and your chip will go
straight to production.
The foundry service can do these things for you:
->layout, place and route
->design for testability (DFT),
this means the foundry worries about manufacturing testability
->offer an IP library (PLLs, certain types of I/O cells)
Did you use the FPGA's DLL circuit? Uh oh, you'd better
pray the foundry has an 'equivalent block' (or you have
redesign it yourself...or not use it.)
7) After you receive the manufactured chip from the foundry, you
re-run verification/debugging. This time, you're working
on the 'real silicon.' If your fortunes are good, everything works
and you're ready to sell parts :)
...
Article: 45511Great - so now I also know what pipelining is in PLDs (did a search on Google - produced this nice page: http://www.chipcenter.com/pld/pldf047.htm) If I understand it correctly its like having an intermediate result stored in registors and the result of this first stage would be the first XOR'ing of the full word length/wide? So in essense I would have 2 clock cycles of deadtime before the comparator would work? (this is perfectly OK for my application as the central microcontroller needs to process the data anyway meantime and the PLD can be reset with lots of time to spare) Nice stuff by the way guys - any good application notes/briefs that describe these tricks? For example what would be the design procedure in Xilinx Webpack - a schematic entry or VHDL (both)? Cheers Klaus "John_H" <johnhandwork@mail.com> wrote in message news:3D3F2897.FAAE80CD@mail.com... > If you're looking at the input data for the magnitude comparison for the trigger > and that's what loads the count-down value, you can register the trigger and > start counting from a value of one clock less. In this configuration you should > get significantly better results. In two stages of pipeline you might even hit > 200MHz performance (requiring a counter load with a value reduced by two). > > Getting to the real meat of the requirements and designing around them can > produce superb results. > > There's also the CoolRunner-II devices you might consider depending on price and > availability. > > > > > Klaus Vestergaard Kragelund wrote: > > > Yes. The comparator is checking the status of the output of a fast 8bit ADC > > (80MSa/s). The purpose of looking at the data is to provide a digital > > trigger signal (like the analog one you would use in a analog oscilloscope). > > When the trigger signal arrives a counter counts down to zero storing data > > in the SRAM memory and stops when zero is reached. > > > > I need a CPLD anyway to divide the datastream into two 8bits words at 40MHz > > instead (the SRAM gets cheaper and the external design-constrains get > > simpler). I may even go for 4 8bit words at 20MHz because I would like to be > > able to drop-in a faster ADC at some time. > > > > So perhaps two 8 bit comparators each clocked at 40MHz? > > > > That should be doable? Anyway of doing another trick? > > > > Also the response need not be superfast - it just has to trigger a output if > > a certain value is exceeded. > > > > Thanks > > > > Klaus > > > > > > > > > > > Klaus Vestergaard Kragelund wrote: > > > > > > > Hi > > > > > > > > I need a 8bit magnitude comparator (just A>B). I can buy a 74AS885 from > > TI > > > > for 8$, but my question is if this can be done/fit in a > > XC9536XL/XC9572XL > > > > Xilinx CPLD part while keeping the delays at 5ns? > > > > > > > > Thanks > > > > > > > > Klaus > > > >Article: 45512
Russell <rjshaw@iprimus.com.au> writes: > http://www.eedesign.com/story/OEG20020712S0074 [translate Verilog into a C/C++ model, then compile this model] Isn't this what Savant[1] is based on since the beginning, just that it takes VHDL as input? Cheers, Colin Footnotes: [1] http://www.ececs.uc.edu/~paw/savant/Article: 45513
Colin Marquardt wrote: > > Russell <rjshaw@iprimus.com.au> writes: > > > http://www.eedesign.com/story/OEG20020712S0074 > > [translate Verilog into a C/C++ model, then compile this model] > > Isn't this what Savant[1] is based on since the beginning, just that > it takes VHDL as input? I though most 'good' Simulators did this ? - if not to an 'open language', then to a compilable form, that is then compiled per session, in order to get the speeds up. -jgArticle: 45514
Hi Jim, when I looked at the error-message I saw that it was giving "TRUE" and "FALSE" in double-quotes. I had something similar with the phase-shift on a DCM once when I declared it as integer. When I declared the attribute as string and gave the integer value as string (e.g. "17" instead of 17) everything went through fine. If I were you I'd stick with XST and just change the attributes to string. I'm quite confident that this will make your design get over that point. Regards, MartinArticle: 45515
Dear no_one, It is grateful that to receive your detailed reply. Now, based on design precedure provided by you, I know what relevant resources I should find in internet. I have one more quesiton: Our company have modelsim and Tanner L-edit, What other tools I need for complete IC development? Which part of tools is free and which must buy? (Personally, I am interested to design a chip for practise, so, I do not need powerful tools for me). Thanks again. With best regards, Reala "no_one" <no_one@nowhere.net> wrote in message news:3D3F8244.5BC3C138@nowhere.net... > > In your post, you say: > > > Webpack will only target Xilinx's FPGA parts, which means it'll always > > > target some kind of Xilinx primitives library. (That's mostly the LUT4 > > > cell primitive.) Someone correct me if I'm wrong If your ASIC-vendor > > > truly offers a 'FPGA->ASIC conversion flow', they surely will accept the > > > Xilinx netlist 'as is.' The ASIC-vendor will worry about the logical > > > remapping between FPGA-library and ASIC-library. > > > > If the netlish including LUT4, then, how to change this into "circuit" when > > I implement this in ASIC? Is it done by ASIC-vender? You says that > > ASIC-vender will worry remapping? > > As I stated, the companies who offer an 'FPGA->ASIC conversion service' > will usually handle the conversion as part of the service. You might > want to take a look at www.atmel.com and www.flextronics.com -- both > companies offer 'FPGA->ASIC conversion services.' Both companies will > directly accept a Xilinx netlist (they want EDIF format instead of > Verilog. > I know the commercial Xilinx Foundation ISE can generate the EDIF file, > but I'm not familiar with Webpack.) > > Read each company's product brochure. Each company presents a > high-level > overview of their conversion service. I think this will answer many of > your questions. > > > So, what is the normally development flow > > for ASIC starting at Verilog? > > Starting from the beginning, here's an typical flow. Note that > development flows vary from company to company, and even project to > project within the same company. The 'exact' flow depends on > the project's requirements and perhaps resource availability. > > #1) 'functional specification.' > Your functional specification describes the circuit's function in > abstract or general terms. For example, given an input 'X', the > DSP will perform some mathematical operation 'A', in order to > produce a final output 'Y'. "Y[n] = A * X[n];" > > #2) Develop a hardware architecture for your functional spec. Now > you're starting to partition the DSP's mathematical formulas > into hardware building blocks, i.e., physical structures which > implement the specified function. > At this stage, you might decide 'ok, we need several multipliers, > adders, a register file, and the control unit.' You've named the > major architectural components of the DSP, but so far, you haven't > actually built anything yet. > > Sometimes, companies will run hardware-simulations at this stage. > These 'behavioral' simulations use abstract models of the device > under test. A behavioral sim is sometimes used as a way to > explore alternative architectures (for example, what if you > want your DSP to have 2 multiply units instead of 1.) They > can offer a rough estimate of your system's performance, and > therefore can identify potential weaknesses or troublespots > in the design's high-level architecture. > > (Ideally, you'd want to correct architectural problems *HERE*, > before you start implementing the real hardware.) > > #3) *** Implement design *** Here's where you start writing your > Verilog RTL-code. Now you worry about things on a clock-cycle to > clock-cycle basis. For example, perhaps you've budgeted 1-clock > to fetch and decode an 'instruction,' 1 more clock for a multiply > operation, and 1 last clock to sum the product with an accumulator. > > <<<Answer to your question after down below >>> > > #4) Verify the design. Instantiate your DSP-processor in some > 'testbench > environment.' Drive inputs into your DSP-model, then observe the > outputs. From your functional spec (step #1), you know the > expected output. Compare the expected-output with your simulation > output. Do they agree? No, time to go back and do some debugging. > Yes, ok ready to move to the next step. > > Simulations run at this stage are often called 'RTL simulations' > (because they check the unsynthesized RTL-code.) Sometimes > engineers > call these 'functional simulations', because the RTL-code is > considered a functional description of the design. > > #5) Synthesize the RTL-code into a 'gate netlist.' > The transformation your design from functional-code to a more > "physical > form" starts with the synthesis step. > The synthesis step accomplishes the following: > maps the RTL-code to a specific "ASIC process" > converts RTL-statements into elementary gates (which are part of > the "technology library") > > #6) verify the synthesized netlist's 'logical equivalence.' > If your RTL multiplier performs "Z = X * Y;", you want to check the > netlist to ensure it's doing the same thing. Rarely, synthesis > tools can make logical mistakes. More often, the RTL-code has some > bug which doesn't show up with functional-simulations, yet causes > a problem during synthesis. > > ... > > Steps #1-6 are fairly generic and apply to any type of logic design > (CPLD, FPGA, ASIC, etc.) > > At this point, you have several choices... > You could either > (A) Tackle the 'back-end' (physical) design process yourself. > 1) placement tool to map your gates to a geographical location on > the silicon die. > 2) routing tool to connect the gates' input/outputs (with wires) > 3) design-rule check on the > 4) check 'timing' (the post-layout netlist has 'annotated delay' > information.) > After place/route, some nets have extra delay (due to distance > or other physical attributes). The net effect is a > performance deterioration (compared to the synthesis tool's > timing report.) Most people use a static-timing analysis tool > to ensure the setup/hold requirements on all flipflops still > fall within spec. > 5) LVS/DRC (I don't know what these are...I think these are final > layout rule checks. ASIC processes generally have complicated > layout rules like 'wires must be a certain spacing from each > other, wires beyond a certain width must be slotted, no logic > allowed too close to I/O pads, etc. A good layout tool will > (from step #1 and 2) will produce very few LVS/DRC errors. > > These errors are sometimes fixed manually (by hand.) > > Some extra issues : testing? How will you check a > manufactured chip for defects? Most people add a 'built in self > test' > (BIST) to their chip design. The BIST circuit lets the foundry > diagnose the raw manufactured chips for defects. Defect chips are > thrown away (before packaging and assembly...) > > (B) You've decided that 'back-end' work is too much for your company. > So you pick an ASIC-foundry who offers 'backend services' (LSI, > IBM, > Atmel, TI, etc.) > > Instead of worrying about all the stuff I just described, you give > the foundry your synthesized netlist (from step #5). The foundry > takes care of the rest. If you're lucky, no problems will arise > during the foundry's back-end workflow, and your chip will go > straight to production. > > The foundry service can do these things for you: > ->layout, place and route > ->design for testability (DFT), > this means the foundry worries about manufacturing testability > ->offer an IP library (PLLs, certain types of I/O cells) > Did you use the FPGA's DLL circuit? Uh oh, you'd better > pray the foundry has an 'equivalent block' (or you have > redesign it yourself...or not use it.) > > > 7) After you receive the manufactured chip from the foundry, you > re-run verification/debugging. This time, you're working > on the 'real silicon.' If your fortunes are good, everything works > and you're ready to sell parts :) > > ...Article: 45516
Daryl, I'm a coplete novice here, but one thing struck me; can you pipeline the compare? The first pipeline stage could be xor'ing n bits, the second stage could or toghether the xor outputs. If the oring of 14 bits is a problem, make a tree structure of it and put the different tree levels in different pipeline stages. If you can afford increased signal latency, the throughput might be improved. With only two-port logic the pipeline could look like this: 14 two-input xors, 7 two-input ors, 3 two-input ors and a single-bit buffer, 1 two-input or and a single-bit buffer, 1 two-input or, output is 0 if the two numbers were equal. But I guess it would make better sense to use the building blocks available in the FPGA/CPLD/whatever than the two-port logic above. Regards, BørgeArticle: 45517
> Not a good cringe. Twisted pair is dispersive, coax much less so. I can see that coax is a better cable for carrying RF signals , otherwise all our aerial connections would be twisted pair! But... > More important, coax cables reject external fields a whole lot better > than twisted pair, How come? Unless the co-ax shielding is ferromagnetic, surely a co-axial pair will present a greater area to any local magnetic fields => induced currents. This area will be hugely reduced with a twisted pair.Article: 45518
When I try to instantiate output LVDS buffer OBUFDS in VHDL, Leonardo adds a new buffer to mine. What can I do to remove this buffer? The no_buff attribute works for input only. Thank you for your help s. brudererArticle: 45519
I am interfacing a DSP to xilinx fpga. The DSP writes to a fifo in the fpga. The timing report gives very good setup time but large hold time. The DSP doesn't introduce hold time but can have wait states. Can any one suggest a way in which I can reduce the hold time requirement. AnjanArticle: 45520
You can do a magnitude compare using the carry chain by doing a
subtraction and using the carry out to determine greater than or equal.
For equality compare, you can use the carry chain for a fast wide AND
gate. That said, if you are looking to compare a single value in the
count sequence, you are better off using a second counter set up as a
loadable downcount. The MSB out can be used as the terminal count.
Sniper Daryl wrote:
> Here,
>
> I am Daryl and I have to trouble you. :-)
>
> When I design a chip used for optical network, a lot of effort must
> be made to increase the clock speed and reduce the chip resource cost.
> In a timing interface module, there is a counter with 14-bit width to
> provide timing to the outgoing frame. So, a comparator used to compare
> the counter word with a series of registers set by the controller.
> I've notice that the slices cost increases seriously and the maxinum
> clock speed decreases a lot, when the counter and the comparator get
> wider.
>
> Troubled with it, I firstly tried a wider counter(14-bit) and a
> narrower comparator(4-bit) and got 20MHz upgrade of speed and more
> than 20 slices saving. Then, a 4-bit counter and 14-bit comparator
> with a result of 10MHz upgrade and about 10 slices saving. So, I think
> the critical factor is the wide comparator. This is proved by studying
> the report and schematics from the synthesis tools(FCII3.6.1 and
> Synplify Pro with Amplify).
>
> To improved the performance, I've tried to use CoreGen tool to
> generate a core of comparator. But,after implement, the result is no
> better than from myselft code.
>
> The synthesis tool I used is FCII 3.6.1, the device is
> VirtextII1000, implement by ISE4.2SP3. Here is the result of my trials
> :
>
> 14-bit counter, 14-bit comparator and other logic : 63
> slices used(36 FFs and 105 LUTs); 95MHz
>
> 4-bit counter, 14-bit comparator and other logic : 50
> slices used(26 FFs and 85 LUTs); 115MHz
>
> 14-bit counter, 4-bit comparator and other logic : 41
> slices used(26 FFs and 62 LUTs); 127MHz
>
> Would you give me some advice about it from your experience? Or
> some resource to study?
>
>
>
> Thanks in advance for you time!
>
> Daryl
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 45521
Wednesday special. Tips are appreciated :-)
rickman wrote:
> Now come on Ray. You know that was worth at least $1.98. I guess you
> were having a special?
>
> Thanks for the tips.
>
> Ray Andraka wrote:
> >
> > My 2 cents worth on this thread:
> >
> > First, some tools such as synplify will infer the SRL16's, and will even put a
> > register at the output, which improves the clock to Q considerably. What it does
> > not do well is adding a register between each SRL16 in the chain. Personally, I
> > prefer to instantiate them using the SRL16 primitive in the unisim library. That
> > way I can put the registers between where they belong, and If I want I can add RLOCs
> > as well as non-zero initial values. Set the timingcheckson generic to false (it
> > defaults to true) to avoid problems in functional simulation, and put the generics
> > inside a syn_translate pragma to avoid possible problems with inference as a black
> > box. Only the output of a register or the flip-flop following it (if you put them
> > in there, which I advise) are visible. If you need to get somewhere in between,
> > then you'll need to adjust your delays to get to the tap you desire. VirtexII has a
> > nice feature that adds an always available output out of the last tap useful for
> > cascade chains. If you dynamically control the shift length, you'll probably want
> > to split up and duplicate the address drivers.
> >
> > If you were not using the block RAMs for something else, you could use them in 16
> > bit wide mode as a delay queue by using one port for read and one for write. The
> > read address and write address have to be offset for it to work correctly.
> > Depending on your data rate frequency, you may also be able to run the BRAM on a 2x
> > or even 4x clock in order to get 2 accesses per clock in order to double the
> > available width. At 1x, and with a 64 deep queue, you can only use 1/4 of the
> > memory per block RAM, so a 4x memory clock would be ideal provided it does not
> > exceed the capabilities of the BRAM.
> >
> > John_H wrote:
> >
> > > Go to http://toolbox.xilinx.com/docsan/xilinx4/manuals.htm and look at the
> > > "Libraries Guide" which has all the primitives listed. You can use an SRL16
> > > with or without enable.
> > >
> > > Of you need to tap off a fixed diagonal, the task is pretty straightrorward but
> > > the coding (3 levels of module hierarchy) isn't as clean. Do you know about
> > > parameterized modules?
> > >
> > > You can have a chain of 4 SRL16s to get your 64 bit delay. To "tap" an element
> > > in the middle at a fixed address, you can either daisy-chain two shorter SRL16s
> > > together (you can program them for delays of 1 to 16, inclusive) or you can tap
> > > off the feed between the 16 long delays and feed an SRL16 in parallel with the
> > > fixed chain. You can hard code the address or select which of those 16 taps you
> > > want dynamically if necessary (but the bits that make the selection could have a
> > > HUGE fanout! 384 bits?!).
> > >
> > > John Hovell wrote:
> > > <excerpt>
> > >
> > > > I'm hunting around right now for the instatiation syntax for an SRL's on the
> > > > net... Is there a primative that I can call so one of these is inferred? It
> > > > seems the PRNG (Xilinx app 211) just uses some fancy compiler ifdef
> > > > statements to get the right piece of hardware inferred. I'm sure I can find
> > > > this info on the 'net so I don't want to bother anyone with simple
> > > > questions... however if someone feels compelled to clue me in, I certainly
> > > > won't mind ;-).
> > > >
> > > > The only reason SRL's might not work is that I need to read *some* values in
> > > > the delay pipe (i.e. the first column and a sort of diagonal row through the
> > > > first half of it: Total bits: 384*2 = 768). Hopefully I can read values
> > > > that are in the shift registers....
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930 Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> > "They that give up essential liberty to obtain a little
> > temporary safety deserve neither liberty nor safety."
> > -Benjamin Franklin, 1759
>
> --
>
> Rick "rickman" Collins
>
> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design URL http://www.arius.com
> 4 King Ave 301-682-7772 Voice
> Frederick, MD 21701-3110 301-682-7666 FAX
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 45522> > > More important, coax cables reject external fields a whole > > > lot better than twisted pair, > > > > How come? Unless the co-ax shielding is ferromagnetic, > > surely a co-axial pair will present a greater area to any > > local magnetic fields => induced currents. This area will > > be hugely reduced with a twisted pair. > > It is the symmetry - in a coaxial cable the outer conductor is > perfectly symmetrically arranged around the inner conductor, so they > both see exactly the same magnetic field, and the pickup is zero > over-all. Do the math. I agree with this completely for a *single-ended* signal, but what about *differential* signalling? Your original reply was: > More important, coax cables reject external fields a whole lot better > than twisted pair, and routing a differential pair of signals along > physically coupled pair of coax cables will do a better job than > routing the same signal along a shielded twisted pair. At a much > higher price .... I'm assuming that you mean that the co-axial *pair* is arranged so that the two polarities of the differential signal are travelling side-by-side in physically separated, shielded cables. Maybe I'm missing something, but I can't see how this presents less loop area to an external field? Thanks for you interest and help.Article: 45523
Is it just me, or can the WebPack icon "Edit Implementation Constraints (Constraints Editor)" be a little touchy? I'm really a novice when it comes to FPGA programming, so having somewhere to point and click is a nice start. But when I add new signals (which I want to map to pins) to my source code, they don't appear in the list in the Constraints Editor. Initially, in a brand new project, it finds several signals and lets me assign pins to them. But as I keep working, making the Constraints Editor find, and not least save, my signals gets increasingly difficult. When I add a signal/pin in my source code, and the Constraints Editor fails to see it, I rather edit the ucf file. If I hit the Constraints Editor again after updating the ucf, the constraints editor refuses to start, stating that my newly added signal does not exist. I'm all ears if you have any suggestion regarding what I should do about the Constraints Editor. I'd like to use it if I could only find it trustworthy. But the best thing would be to put the constraints into my verilog code. I mean, your modules could go with a verilog testbench for simulation and a verilog constraints file for implementation. Regards, Børge The error message and code are inserted below. ERROR:NgdBuild:397 - Could not find NET 'resetl' in design 'implementation'. NET entry is 'NET "resetl" LOC = "D8"; ' ERROR:Parsers:11 - Encountered unrecognized constraint while parsing. ERROR:NgdBuild:19 - Errors found while parsing constraint file "implementation.ucf". while the top of my code reads module implementation (clk_100, resetl, button, segment2, segment1, led, countednumber); input clk_100; input resetl; input button; output [6:0] segment2, segment1; // two seven-segment displays output led; output [2:0] countednumber; show dice (clk_100, resetl, countednumber, segment1, segment2); // shows selectednumber as dice eyes numbergenerator counter (clk_100, resetl, countednumber, button, led); // count while button is pressed endmodule The "resetl" signal was added after I had been working on the code for a while. And if you wonder, the code implements an electronic dice. numbergenerator counts on clk_100 as long as I keep button pressed. show continuously translates the generated number into dice eyes.Article: 45524
Ah, now I thing I got it, the software thinks for me, and if there's a signal that doesn't do anything, it does not exist.... Is there some way I can turn this off? Børge
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