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I have a design that uses dual port block ram in a Viretx E. It simulates beautifully at the RTL level, including the RAM. However, the device doesn't operate beautifully, the RAM is very suspect. So, I did a gatelevel simulation, and things looked funny. However, now I don't know if it's a problem with the testbench or a problem with the gatelevel design. Do I need to do anything special to simulate the block ram at the gatelevel? Any extra files or libraries I need? Thanks, DaveArticle: 45476
Prashant wrote:
>
> Hi,
> I'm looking to prototype my design on an evaluation board. But I have
> some questions.
>
> 3. Is it possible to give inputs real time from a PC to an FPGA on a
> dev board ? I wouldn't think so, but let me know if the technology
> allows.
>
> Thanks,
> Prashant
PCI bus is probably the bus you are talking about (Or maybe
USB.), but dealing with PCI is tricky because either it costs a lot to
license one or takes a lot of time to develop your own PCI IP core.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 45477
Klaus Vestergaard Kragelund <KlausKVIK@hotmail.com> wrote:
: Hi
: I need a 8bit magnitude comparator (just A>B). I can buy a 74AS885 from TI
: for 8$, but my question is if this can be done/fit in a XC9536XL/XC9572XL
: Xilinx CPLD part while keeping the delays at 5ns?
I just checked witch the simple verilog statement and got following result:
Synthesizing Unit <magcomp>.
Related source file is magcomp.v.
Found 8-bit comparator greater for signal <c>.
Summary:
inferred 1 Comparator(s).
Unit <magcomp> synthesized.
cpldfit: version E.38 Xilinx Inc.
Fitter Report
Design Name: magcomp Date: 7-24-2002, 10:23PM
Device Used: XC9536XL-5-PC44
Fitting Status: Successful
Performance Summary:
Pad to Pad (tPD) : 10.1ns (2 macrocell levels)
Pad 'a<1>' to Pad 'c'
--------------------------------------------------------------------------------
Pad to Pad (tPD) (nsec)
\ From a a a a a a a a b b b b
\ < < < < < < < < < < < <
\ 0 1 2 3 4 5 6 7 0 1 2 3
\ > > > > > > > > > > > >
\
\
\
To \------------------------------------------------------------------------
c 10.1 10.1 9.4 6.0 5.7 5.7 9.4 9.4 10.1 10.1 10.1 6.0
--------------------------------------------------------------------------------
So it seem you don't meet your spec with that simple approch. As synthesize
inferred a comparator, I guess it is quite optimized..
Btw: A 16 bit comparator has the same seed...
Bye
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de
Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Article: 45478If there's anything in your system that would allow a different look at things, you might achieve your end goal. I don't think you can do a straight 8 bit A vs B in anywhere close to 5ns because of the cascade of logic required. If you're comparing to a constant, however, the situation could turn to your favor. If you can register the comparison and get the result on the next clock, there are more possibilities still. Any room for relaxing the spec? Klaus Vestergaard Kragelund wrote: > Hi > > I need a 8bit magnitude comparator (just A>B). I can buy a 74AS885 from TI > for 8$, but my question is if this can be done/fit in a XC9536XL/XC9572XL > Xilinx CPLD part while keeping the delays at 5ns? > > Thanks > > KlausArticle: 45479
Reala wrote:
>
> Dear Kevin,
>
> Thank you for your detailed reply.
> Actually, I work in a IC design company. My boss want to develop a low-end
> DSP chip. However, we are less experience in this.
> We think that one of the important building block is 16X16 small size,
> single cycle multiplier.
> I write simple verilog and synthesis by Xilinx Web pack tools. It seems that
> work.
> Assuming it is work, I want to open some output files to see what "circuit"
> is synthesised, because I will design a DSP chip. But i do not know which
> output files mention the netlist of the "systhesised design" in gate level.
>
I will assume that you are trying to develop a 16 X 16
multiplier IP core.
When doing that, you should turn off (uncheck) "Add I/O Buffer" option
(Or something that sounds like that.) of the synthesis tool, so that the
multiplier block can be attached to rest of the logic.
When using the multiplier IP core from another design, you will need to
instantiate a blackbox of it when synthesizing that design, and also
tell NGDBUILD where the netlist of the multiplier IP core is located.
> I guess that the verilog code will be synthesised by synthesis according to
> synthesis tool's library. Am I correct? Can i force the synthesis tool to
> synthesis the verilog code without using library? (I means the design is
> systhesis in gate level ...AND OR XOR.....) Then, can i see the netlist in
> gate level such that I can study the design synthesised by the synsthesis
> tool?
>
Assuming that you are using ISE WebPACK's synthesis tool XST,
you cannot do that because it doesn't support schematic viewing of the
synthesized design, although I heard a rumor recently that the soon to
be released ISE 5.x will support this feature (I believe a Xilinx
employee said so in this newsgroup recently.).
If you are willing to pay for Synplify or LeonardoSpectrum, I believe
they have the capability to let you see the gate level equivalent of the
synthesized design.
The reason I just said, "the gate level equivalent of the synthesized
design" is because in Xilinx FPGAs, LUT (Look Up Tables) emulate logic
gates (AND, OR, NOT, XOR, etc.)
Normally, if you ask a Xilinx about looking at the netlist
generated by XST, they will tell you that, "Sorry, XST of ISE 4.x can
only generate an encrypted netlist (.NGC file). To generate an EDIF
netlist (.EDN or .EDF), you will have to buy a third-party synthesis
tool," but following the instructions of the posting I made, you will be
able to generate an EDIF netlist from XST.
http://groups.google.com/groups?hl=en&lr=&ie=UTF-8&threadm=aceeac%249fj%241%40newsreader.mailgate.org&rnum=1&prev=/groups%3Fq%3DBrace%2BEDIF%2BXST%26hl%3Den%26lr%3D%26ie%3DUTF-8%26selm%3Daceeac%25249fj%25241%2540newsreader.mailgate.org%26rnum%3D1
Again, in Xilinx FPGA synthesis tools, gates (AND, OR, NOT, XOR,
etc.) get converted to LUTs, so having an EDIF netlist still won't help
you see the gate-level representation of the synthesized circuit.
> You say that:
> >To make sure the synthesized design was synthesized correctly,
> >do a gate-level simulation of the synthesized design.
> >You should be able to run the same testbench code you used for an RTL
> simulation.
>
> I am not really understand because I am a beginner of IC design.
> what is the meaning of gate-level simulation? by what kind of tools?
> Modelsim? Xilinx? or other?
>
Gate-level simulation in this case means a post synthesis
simulation (Xilinx calls it "Post translate simulation.").
What you are trying to do is to make sure the synthesis tool correctly
converted your synthesizable RTL (Register Transfer Level) code to
gates.
Although it doesn't happen that often, synthesis tools do have bugs, and
messes up the synthesis.
If you are a beginner (I think you mentioned that.), try using
ModelSim XE-Starter that comes with ISE WebPACK for simulating your
design.
The only limitation of ModelSim XE-Starter is that the simulation slows
down after 500 lines of code, but it still simulates your design even if
you exceed the limit.
> What is RTL (Register Tran...Logic) I know the name but not really know the
> meaning? What tools for RTL synthesis?
>
> Thank again ^_^
> Reala
>
RTL stands for "Register Transfer Level."
Someone else already explained what it is, so I won't get into that
here.
If you are using ISE WebPACK, XST (Xilinx Synthesis Technology) is the
synthesis tool you have been using.
There are other synthesis tools like Synplicity's Synplify, Mentor
Graphics LeonardoSpectrum, and Synopsys FPGA Compiler II.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 45483Edward Moore wrote: > > You can gate the clock using the enable pin on the Virtex-E global clock buffer. > > You would need to create a hard macro in Fpga Editor containing a > GCLKBUF with the I, O and CE i/o's as external pins. I suggest driving > the CE pin from a FF clocked off the falling edge of the ungated clock. > > Beware : there seems to be a bug with the GCLKBUF primitive due to swapped > configuration bits; the workaround is to set the CEMUX option to '1' not CE. > > I have tried this. It works. > > -- > Edward Moore > > Jason Crawford <jace@cisco.com> wrote in message news:<3D3BAC69.A03017A@cisco.com>... > > Hi, > > > > Apart from using clock-enables, does anyone know of any > > way to use clock-gating in Virtex-E parts? > > > > We have a design that is partially written for an ASIC > > target and expects to see a gated clock. Rather than have > > to get the designers to pour throught the code and add > > clock enables to all flip flops (I can hear teeth gnashing > > already) I am hoping against hope that someone has an > > alternate answer to this rather difficult problem. > > > > yours in hope, > > Jason. hmmm... wonder why there's an enable pin if you can't get to it unless you go through the "backdoor" ? any reason why you shouldn't use a latch i.e. something like this always@(clk or enable) if(!clk) enable_q <= enable; assign gatedclk = clk & enable; -Lasse -- // Lasse Langwadt Christensen // Aalborg, DanmarkArticle: 45485
"Børge Strand" wrote:
>
> The pride of getting hello world (dip switches to seven-segment displays)
> working in Verilog on my SpartanIIe board has been replaced by a bunch of
> new questions. I hope you can help me out a bit on these ones;
>
> I'm a bit at a loss when it comes to handling the different constraints
> files and constraints databases in WebPack.
>
> What I do is change the name of an input or output in my .v file, hit "Edit
> Implementation Constraints (Constraints Editor)", and have it reporting
> errors when parsing the .ucf-file. What is the recommended way to maintain
> constraints?
>
When I did my first FPGA design about a year ago, I used the
constraints editor to enter constraints, but as I got used to ISE
WebPACK, I no longer use the constraint editor.
You should download Constraints Guide (cgd.pdf) from Xilinx which
explains all the UCF file constraints.
The UCF file name should normally match the name of the top module.
> Also, how should I enter timing and compactness constraints? And equally
> imprtant, which report do I read to find out what timing can be expected
> from the actual implementation?
>
> Thanks,
>
> Børge
Most of the time, timing related issues will be dealt in the
backend flow (Place & Route), but the density of the design is usually
dealt in the frontend flow (synthesis).
If you are using ISE WebPACK, XST (Xilinx Synthesis Technology) handles
the frontend flow, and NGDBUILD, MAP, and PAR handle the backend flow.
When you first generate a UCF (User Constraint File) file, it
explains the syntax of a UCF file.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 45486Hello! Strange, but we 've got the same problem with a 20K400E FBGA. The problem was solved by supplying VCC I/O before VCC core in our design. But, we have'nt seen anything related to this serious problem in altera website. Pascal "Henning Trispel" <henning.trispel@kielnet.net> a écrit dans le message news: 3D2875F6.6000905@kielnet.net... > Hello all! > > The Altera APEX20KE use a VCC supply for I/O and for the core (1V8). In > the datasheets Altera claims, that any sequence of supply power-up is > allowed. However, the prototypes of a new board we designed in the > company I work for showed a very strange behaviour: About half of the > FPGA burned to death (obviously some kind of latch-up and taking > whatever was supplied by the power-supply, which was about 70Watts into > the BGA 652pin package). Strange enough, the rest worked ok. Several > discussions with Altera applications made us assume a configuration > problem - which it was not. > > [... two weeks of failure cause searching ...] > > The result was that it actually DOES matter, which supply rises first. > In our application, VCC core is up about 50ms before VCC I/O. Although > _all_ BGAs where from the same production lot, several (4 pcs) did not > like that, while the other three worked ok. When we changed the > power-supply design and assured that VCC I/O is up at latest when VCC > core rises, we had no failure since. I am using Altera for over 10 year > now, but never had such a "misleading" datasheet. > > So if you design with the Apex 20KE - make sure that VCC core is not up > before VCC I/O. Finally, the part is quite nice, but if the datasheet > would have been more correct on this, it would have saved at least two > weeks in the lab. > > Have a nice and successful working week, > Henning Trispel >Article: 45489
hull wrote:
>
> Another problem of this core is that if I use XST to synthesize, the result is
> wrong(the overflo turn to state of X when computing).
Since your are using a blackbox in your design, you may want to
turn on "Keep Hierarchy" option of XST.
If that doesn't help, turn off or disable bunch of other synthesis
options.
> When using synplify,the result is correct when the clock frequency less than
> 60Mhz, if the clk frequency more
>
> than 60MHz, the result is wrong just like when using XST, why?
Did you P&Red the design?
What is the maximum frequency (Sometimes called minimum period) you
achieved?
If you are running your design above the maximum frequency, it probably
won't work.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 45490
hi,
This is a stupid question: I am using Spartan 2 E and I am going to use
2 DLL for generating /4 and /16 clk.
so,
If I instantiate the component CLKDLL
like this
component CLKDLL
-- use divide by 16 clk = 3.0Mhz
-- STARTUP_WAIT -> Device Config DONE signal waits until
-- the DLL locks before going to high
generic ( CLKDV_DIVIDE : real := 16.0;
STRATUP_WAIT : Boolean := TRUE);
port ( CLKIN : in std_ulogic := '0';
CLKFB : in std_ulogic := '0';
RST : in std_ulogic := '0';
CLK0 : out std_ulogic := '0';
CLK90 : out std_ulogic := '0';
CLK180 : out std_ulogic := '0';
CLK270 : out std_ulogic := '0';
CLK2X : out std_ulogic := '0';
LOCKED : out std_ulogic := '0');
end component;
..........Then the question is what can I do for instantiation the second
CLKDLL with CLKDV_DIVIDE = 4?
Thanks
Jim
Article: 45491Jim Raynor wrote: > hi, > > This is a stupid question: I am using Spartan 2 E and I am going to use > 2 DLL for generating /4 and /16 clk. > > so, > > If I instantiate the component CLKDLL > > like this > > component CLKDLL > -- use divide by 16 clk = 3.0Mhz > -- STARTUP_WAIT -> Device Config DONE signal waits until > -- the DLL locks before going to high > generic ( CLKDV_DIVIDE : real := 16.0; > STRATUP_WAIT : Boolean := TRUE); > port ( CLKIN : in std_ulogic := '0'; > CLKFB : in std_ulogic := '0'; > RST : in std_ulogic := '0'; > CLK0 : out std_ulogic := '0'; > CLK90 : out std_ulogic := '0'; > CLK180 : out std_ulogic := '0'; > CLK270 : out std_ulogic := '0'; > CLK2X : out std_ulogic := '0'; > LOCKED : out std_ulogic := '0'); > end component; > > > ..........Then the question is what can I do for instantiation the second > CLKDLL with CLKDV_DIVIDE = 4? That is only the declaration, before the "begin" in the architecture section. You only need that once, and you should not be providing all those default values here. Instead, below the "begin" where you actually instantiate the components, when you do the port map, also do a generic map. -- My real email is akamail.com@dclark (or something like that).Article: 45493
Klaus Vestergaard Kragelund <KlausKVIK@hotmail.com> wrote: : "John_H" <johnhandwork@mail.com> wrote in message :> :> Any room for relaxing the spec? :> : Yes. The comparator is checking the status of the output of a fast 8bit ADC : (80MSa/s). The purpose of looking at the data is to provide a digital : trigger signal (like the analog one you would use in a analog oscilloscope). : When the trigger signal arrives a counter counts down to zero storing data : in the SRAM memory and stops when zero is reached. : I need a CPLD anyway to divide the datastream into two 8bits words at 40MHz : instead (the SRAM gets cheaper and the external design-constrains get : simpler). I may even go for 4 8bit words at 20MHz because I would like to be : able to drop-in a faster ADC at some time. : So perhaps two 8 bit comparators each clocked at 40MHz? : That should be doable? Anyway of doing another trick? : Also the response need not be superfast - it just has to trigger a output if : a certain value is exceeded. Yes, either interleaf or pipeline. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 45494
If you're looking at the input data for the magnitude comparison for the trigger and that's what loads the count-down value, you can register the trigger and start counting from a value of one clock less. In this configuration you should get significantly better results. In two stages of pipeline you might even hit 200MHz performance (requiring a counter load with a value reduced by two). Getting to the real meat of the requirements and designing around them can produce superb results. There's also the CoolRunner-II devices you might consider depending on price and availability. Klaus Vestergaard Kragelund wrote: > Yes. The comparator is checking the status of the output of a fast 8bit ADC > (80MSa/s). The purpose of looking at the data is to provide a digital > trigger signal (like the analog one you would use in a analog oscilloscope). > When the trigger signal arrives a counter counts down to zero storing data > in the SRAM memory and stops when zero is reached. > > I need a CPLD anyway to divide the datastream into two 8bits words at 40MHz > instead (the SRAM gets cheaper and the external design-constrains get > simpler). I may even go for 4 8bit words at 20MHz because I would like to be > able to drop-in a faster ADC at some time. > > So perhaps two 8 bit comparators each clocked at 40MHz? > > That should be doable? Anyway of doing another trick? > > Also the response need not be superfast - it just has to trigger a output if > a certain value is exceeded. > > Thanks > > Klaus > > > > > > > Klaus Vestergaard Kragelund wrote: > > > > > Hi > > > > > > I need a 8bit magnitude comparator (just A>B). I can buy a 74AS885 from > TI > > > for 8$, but my question is if this can be done/fit in a > XC9536XL/XC9572XL > > > Xilinx CPLD part while keeping the delays at 5ns? > > > > > > Thanks > > > > > > Klaus > >Article: 45495
Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> wrote: : Klaus Vestergaard Kragelund <KlausKVIK@hotmail.com> wrote: : : Yes. The comparator is checking the status of the output of a fast 8bit ADC : : (80MSa/s). The purpose of looking at the data is to provide a digital : : trigger signal (like the analog one you would use in a analog oscilloscope). : : When the trigger signal arrives a counter counts down to zero storing data : : in the SRAM memory and stops when zero is reached. ... : Yes, either interleaf or pipeline. Experimenting a little more, what about registering both input, comparing the registered values and registering the result. That way you get a pipeline delay of two clock, but the design fit reports a maximum clock of 93 MHz, 3.5 ns Clock to Output delay and 3.7 ns Setup for the Input. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 45498
hi,
I always used XST for implementing my designs....However, for my current
design I used XST as well but it failed to complie because I have used some
Boolean and real variable and XST tool couldn't recognize them for some
reasons....
For the Boolean variable,
I have done something like that:
STARTUP_WAIT : Boolean := TRUE;
DUTY_CYCLE_CORRECTION : Boolean := TRUE;
but the XST gave errors:
ERROR:Pack:272 - Invalid "STARTUP_WAIT" property value of '1' found on
CLKDLL
symbol 'dlldiv16'. The only accepted values for "STARTUP_WAIT" are "TRUE"
or
"FALSE".
However, if I run the design using FPGA Express...it is all fine.
Could anyone tell me if I am missing something?? The library those I
used is as follows:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Thanks for all the help.
VHDL Rookie
Jim
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