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Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Hi,
I have a VHDL design with some ROM32X1 primitives and use the Synopsys synthesis tool.
To initialize the ROM's for a XC4000 FPGA i use the following in VHDL:
--synopsys dc_script_begin
--set_attribute {ROM} xnf_init "01234567" -type string
--synopsys dc_script_end
This works well, if i write out the design in XNF file. But for Virtex FPGA's the Xilinx
tool need EDIF file. If i write out the desing in EDIF file, the initialization is lost.
Knows someone a solution to initialze ROM primitves for Virtex???
Mathias
Article: 29301Expressive V3 from Expressive Systems Limited is now available in Europe from EuroEDA Limited. Expressive is a graphical hierarchy editor for VHDL and Verilog design that generates HDL to describe the structure and hierarchy of complex FPGA or ASIC designs. It is designed to complement existing text-based design flows and provides an intuitive framework for specifying, visualizing and documenting HDL design projects. http://www.euro-eda.com for more information and to download a demonstration version. --- EuroEDA Limited Phone: +44 (0)1933 676373 Fax: +44 (0)1933 676372 Email: info@euro-eda.com Web: http://www.euro-eda.comArticle: 29302
Perhaps I did not make myself clear in the message. What I want to know is whether a home made JTAG cable is OK to use or perhaps you need special cable made with say shielded flat ribbon cable and some other critical construction method, for it to be used reliably. Thanks. Pratip Mukherjee pratipm@hotmail.com "Klaus Falser" <kfalser@REMOVETHISdurst.it> wrote in message news:3a88e2cc.84736084@news.iunet.it... > On Tue, 13 Feb 2001 03:58:27 GMT, pratipm@hotmail.com (Pratip > Mukherjee) wrote: > > >I have just started learning how to design for CPLDs using VHDL. Now I want to > >try out using a real life problem by actually programming a chip (a CPLD like > >say XESS, in order to program or can I make my own JTAG cable with circuit > >say XESS, in order to program or can I make my own JTAG cable with circuit > >diagram from Xilinx web site and use Webpack software? Even if this means > >buying the chip from, say Insight, I figure it still cheaper. I am on a tight > >budget here since this is just for my hobby. > >Thanks. > > > >Pratip Mukherjee > >pratipm@hotmail.com > > You can build your JTAG Cable yourself. Look for the schematics of > the Parallel Cable III on the Xilinx web site. > The original cable however is not so expensive (about 100 $). > The Webpack software is needed in any case. > > Have fun > Klaus > Falser Klaus > R&D Electronics Department > Company : Durst Phototechnik AG > Vittorio Veneto Str. 59 > I-39042 Brixen > Voice : +0472/810235 > : +0472/810111 > FAX : +0472/830980 > Email : kfalser@IHATESPAMdurst.itArticle: 29303
Could some kind soul(s) explain what Specman does in terms suitable for an engineer rather than a computer scientist. A friend said something about constraint solving but didn't really help. Cheers, JonArticle: 29304
"Eric Jeandeau" writes: > Firstlly, thank you for your answer ( Now I know that I am not > the only Handel-C programmer !!!) You're not the only one. I've been using Handel-C version 2 for about 3 years. Only on Altera devices. I've ported some of my code to version 3 beta, but had enough problems with the compiler (crashes, failure to compile etc.) that I'm still using version 2 for now. I combine it with a little VHDL in places. A find the language pretty good, and compact too. It's timing is not as relaxed as some other hardware compilers, restricting some optimisations. But then the source is much smaller, and you know what's going on if you want to hand-optimise. I never found the company terribly responsive to the problems I had (even though they funded me), especially with Altera devices, so by now I am quite used to post-processing the netlists output by the Handel-C compiler. > But what I am looking for is (for instance) : > - Theses/Rapport with program sample program Handel-C > - internet topics : www or ftp or newsgroup Ahh.. can't help with that. Don't like writing reports :-) You might find some reference to applications at these places, but no decent source code. Hopefully I'll be allowed to publish some source one day but we're not there yet. http://www.tantalophile.demon.co.uk/reports/pparc.ps http://atlas.web.cern.ch/Atlas/project/cern/ep-atr/download/ethernet_tester/simple_enet32.html -- JamieArticle: 29305
Hi! I am a student of SDSMT and am studying configuration of FPGA using SPROM and for some reason I am unable to configure it to a simple design of Shift Register. INIT(active low) signal which should be actually high during configuration is low .We have connected to OE(active high)/RESET(active low)signal we think that there is a configuration error. So could anyone please let us know what is the error in the short report i am posting along with this mail. thank you sincerely, Radhika Procedure: 1. The bit file is generated by the Xilinx bit generator . 2. This bit file is formatted using the PROM file formatter. This gives us the .MCS file which can be loaded into the PROM. 3. XPGM is used to configure the PROM and prior to the configuration we need to make the RESET pin of the PROM active low signal since this is driven by the active low INIT signal and then it is configured to the design which in this case is shift register. 4. The PROM now has our design and this is connected to the FPGA using the above schematic which is Master Serial mode. 5. The mode pins M0,M1 and M2 are all made LOW for the FPGA to be in Master serial mode.Article: 29306
Check out the link below for a solution record on Xilinxs web site which describes how to do
this . . .
http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=4595
Best regards,
Chris
Mathias Schmalisch wrote:
> Hi,
>
> I have a VHDL design with some ROM32X1 primitives and use the Synopsys synthesis tool.
> To initialize the ROM's for a XC4000 FPGA i use the following in VHDL:
>
> --synopsys dc_script_begin
> --set_attribute {ROM} xnf_init "01234567" -type string
> --synopsys dc_script_end
>
> This works well, if i write out the design in XNF file. But for Virtex FPGA's the Xilinx
> tool need EDIF file. If i write out the desing in EDIF file, the initialization is lost.
>
> Knows someone a solution to initialze ROM primitves for Virtex???
>
> Mathias
Article: 29307I'd register the pulse output. That'll solve the glitching problem. rk wrote: > > Falk Brunner wrote: > > > > karenwlead@my-deja.com schrieb: > > > > > > thanks for the reply. i use schematic entry ? > > > > So get professional and use VHDL. > > Just kidding. > > ;-))) > > > > So, simply take a 8 bit counter (outputs q7-q0), and your pulse output > > is HIGH when the counter is on 1,2 or 3 > > This means, take a 2-input AND gate, the 2 inputs are feed by a 6-input > > AND gate which is feed with > > > > /Q7 /Q6 /Q5 /Q4 /Q3 /Q2 (/Qx means inverted) > > > > and a 2-input OR which is feed with > > > > Q1 Q0 > > > > This should work. > > How about when the counter counts? > > 01111111 > 10000000 > > Hint for the h-work kid: look up static hazard in your logic book. > > ----------------------------------------------------------------------- > rk A designer has arrived at perfection > stellar engineering, ltd. not when there is no longer anything > stellare@erols.com.NOSPAM to add, but when there is no longer > Hi-Rel Digital Systems Design anything to take away - Bentley, 1983Article: 29308
Hi! I am a student of SDSMT and am studying configuration of FPGA using SPROM and for some reason I am unable to configure it to a simple design of Shift Register. INIT(active low) signal which should be actually high during configuration is low .We have connected INIT to OE(active high)/RESET(active low)signal we think that there is a configuration error. So could anyone please let us know what is the error in the short report i am posting along with this mail. thank you sincerely, Radhika Procedure: 1. The bit file is generated by the Xilinx bit generator . 2. This bit file is formatted using the PROM file formatter. This gives us the .MCS file which can be loaded into the PROM. 3. XPGM is used to configure the PROM and prior to the configuration we need to make the RESET pin of the PROM active low signal since this is driven by the active low INIT signal and then it is configured to the design which in this case is shift register. 4. The PROM now has our design and this is connected to the FPGA using the above schematic which is Master Serial mode. 5. The mode pins M0,M1 and M2 are all made LOW for the FPGA to be in Master serial mode. 6.connections for the FPGA pins connected DATA(of SPROM) to DIN; CCLK to CLK (of SPROM) INIT to OE/RESET; A short low pulse on PROG pin; DONE connected to Vcc using 4.7k; LDC to CE(of SPROM); M0,M1 and M2 to GND using 4.7K ;Article: 29309
Austin Franklin wrote: > > Typically, people make custom symbols, separated into functional groups, > with actual signal names on the pins, not one generic XCV2000E-BG560C > symbol... At least that's the way I've been doing it, and everyone else, > but one person I know has been too... I'm with Austin on this. If someone gave me a D-size schematic shrunk down to B-size with a 560-pin FPGA plopped down in the middle, and a rat's nest of lines going every which way, I'd use the schematic to line the cat box. It's that useful. -andyArticle: 29310
Article: 29311
Rick Filipkiewicz wrote: > > Andy Peters wrote: > > > Brian, > > > > Oh, wait, now I remember. They were the 740 and the 780 series parts? > > Named after Volvos. Interesting. > > > > Don't be so sarcastic about these parts. To be honest, I only remember them because I found a databook when cleaning up because I was changing jobs. But, I mean, the part numbers ARE interesting, eh? I've seen a whole bunch of products with part numbers like "911" and "944" and such. Me, I'd call it the 666. -andyArticle: 29312
This is a multi-part message in MIME format. --------------23852F421A2576DEFD4977A3 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> If I remember correctly, that version of s/w had only initial support for Virtex devices. Basically you need the M1.5i service packs, or a later version of s/w. Current version is 3.3.07i... <p>Dave <p>Eddy Sambuaga wrote: <blockquote TYPE=CITE>I'm using the Virtex XCV300. When trying to Implement (running flow engine in the Design Manager), it fails in the last step, Configure. <br>It says Bitgen only supports DRC for the particular device, so <br>what should I do to get it to generate bitfile? <p>Eddy. <p>================================================ <p>bitgen ds104.ncd -l -w -f bitgen.ut <p>Loading device database for application Bitgen from file "ds104.ncd". <br> "ds104" is an NCD, version 2.27, device xcv300, package bg352, speed -4 <br>Loading device for application Bitgen from file 'v300.nph' in environment <br>d:/xilinx. <br>Opened constraints file bigand.pcf. <p>BITGEN: Xilinx Bitstream Generator M1.5.19 <br>Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved. <p>Thu Feb 08 18:46:36 2001 <p>Running DRC. <br>DRC detected 0 errors and 0 warnings. <br>WARNING:basbs:134 - bitgen only supports DRC on this device.</blockquote> </html> --------------23852F421A2576DEFD4977A3 Content-Type: text/x-vcard; charset=us-ascii; name="dhawke.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for David Hawke Content-Disposition: attachment; filename="dhawke.vcf" begin:vcard n:Hawke;David Hawke tel;cell:(+44) 778 875 5002 tel;work:(+44) 870 7350 517 x-mozilla-html:TRUE org:<br><img src="http://www.xilinx.com/images/smvirtex.gif" alt="Xilinx"> version:2.1 email;internet:dhawke@xilinx.com title:XILINX Field Applications Engineer adr;quoted-printable:;;Xilinx Northern Europe=0D=0ABenchmark House;203 Brooklands road;Weybridge;; x-mozilla-cpt:;2672 fn:David Hawke end:vcard --------------23852F421A2576DEFD4977A3--Article: 29313
_________________________________________________________________________ Get Your Private, Free E-mail from MSN Hotmail at http://www.hotmail.com. -- Posted from [143.117.60.33] by way of f264.law4.hotmail.com [216.33.148.142] via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 29314
The best place to start is probably the configuration problem solver at: http://service.xilinx.com/support/cgi-bin/webcgi.exe?New,KB=config There could be a few things up that is why I won't list every possible reason, if the work has already been done in that link. Chris radhika wrote: > Hi! > I am a student of SDSMT and am studying configuration of FPGA using SPROM and for some reason I am unable to configure it to a simple design of Shift Register. INIT(active low) signal which should be actually high during configuration is low .We have connected INIT to OE(active high)/RESET(active low)signal we think that there is a configuration error. So could anyone please let us know what is the error in the short report i am posting along with this mail. > thank you > > sincerely, > Radhika > > Procedure: > 1. The bit file is generated by the Xilinx bit generator . > 2. This bit file is formatted using the PROM file formatter. This gives us the .MCS file which can be loaded into the PROM. > 3. XPGM is used to configure the PROM and prior to the configuration we need to make the RESET pin of the PROM active low signal since this is driven by the active low INIT signal and then it is configured to the design which in this case is shift register. > 4. The PROM now has our design and this is connected to the FPGA using the above schematic which is Master Serial mode. > 5. The mode pins M0,M1 and M2 are all made LOW for the FPGA to be in Master serial mode. > 6.connections for the FPGA pins > connected DATA(of SPROM) to DIN; > CCLK to CLK (of SPROM) > INIT to OE/RESET; > A short low pulse on PROG pin; > DONE connected to Vcc using 4.7k; > LDC to CE(of SPROM); > M0,M1 and M2 to GND using 4.7K ;Article: 29315
Terje Mathisen <terje.mathisen@hda.hydro.com> writes: >glen herrmannsfeldt wrote: >> One thing that was noted for the 91 was that it rounded instead of >> truncated so it was more accurate but didn't follow the S/360 >> definition of FP divide. I don't know if this is a problem in IEEE >> or not. Does IEEE require specific rounding rules for division? >Is the Pope a Catholic? >Yes, IEEE does require fdiv to follow _all_ the rules, which means >returning the exact same results as all other conforming >implementations, for all possible in-range inputs. That is what I thought. The iterative divide algorithm would tend to have different rounding than using a fixed number of guard bits with a more conventional divide algorithm. It tends to give more accurate results. -- glenArticle: 29316
Andy Peters wrote:
>
> I'd register the pulse output. That'll solve the glitching problem.
Yes, I'd agree.
----------------------------------------------------------------------
rk Historically, disruptive technologies
stellar engineering, ltd. involve no new technologies; they
stellare@erols.com.NOSPAM consist of components built around
Hi-Rel Digital Systems Design proven technologies and put together
in a novel product architecture ...
-- Clayton M. Christensen
Article: 29317People have been doing this since at least 94. It always works. I believe there is a state machine that samples prog. If the device salmples the signal and it is low the ram clearing process starts and the signal goes away but by that time it is too late. Steve Casselman "Peter Alfke" <peter.alfke@xilinx.com> wrote in message news:3A847357.3BA64E3C@xilinx.com... > If I remember right, I was the one coming up with the idea of self-initiated > reconfiguration. > I see no reason why this should be any different in Virtex. > The idea is that the internal logic creates a Low output on Progr ( if necessary > through a pc-board connection ). > The paranoid pessimist might say that we cannot guarantee to maintain that Low > long enough, but the realist knows that there is a causal relationship between > the new configuration having started and the output losing its drive. Once > started, the configuration will just go on. > So it has to work because of this, to hell with the spec. > > Peter Alfke, Xilinx Applications > ======================================= > Kons Henrik Bohre wrote: > > > Record 4296 in the Answer Database states that newer devices after the > > 4000 series > > are not able to control their own reconfiguration due to other > > requirements on the > > PROGRAM pin. > > > > However, the Virtex series conforms to the 300 ns requirement on the > > PROGRAM pin, > > so does anyone know if it is possible to safely initiate a > > reconfiguration by > > pulling the PROGRAM pin low with its own logic? > > > > Best Regards, > > /Henrik Bohre >Article: 29318
1st Call for Papers
2001 MAPLD Conference
JHU/APL - Laurel, Maryland
September 11-13, 2001
The 4th annual Military and Aerospace Applications of Programmable
Devices and Technologies International Conference will address devices,
technologies, usage, reliability, fault tolerance, radiation
susceptibility, and applications of programmable devices and adaptive
computing systems in military and aerospace systems.
This year's Conference will also include papers and an emphasis on
CPU design (both traditional processors as well as those embedded
in ASICs/SoC and programmable devices), logic design, and device
reliability.
The program will consist of oral and poster technical presentations
and industrial exhibits. This conference is open to US and foreign
participation and is unclassified. Select papers will be published
in the AIAA Journal of Spacecraft and Rockets.
Two tutorials/seminars will be given:
1. Programmable Logic Devices and Architectures
2. Advanced Design: Designing for Reliability
Invited Speakers include:
Arthur F. Obenshain, NASA Goddard Space Flight Center
Director, Applied Engineering & Technology Directorate
Lieutenant General Ronald T. Kadish, United States Air Force
Director, Ballistic Missile Defense Organization
Dr. Roger D. Launius, Chief Historian, NASA
Dr. James E. Tomayko, Carnegie Mellon University
Dr. David A. Bearden, The Aerospace Corporation
Dr. Steve Guccione, Xilinx Corporation
The conference is sponsored by:
NASA Goddard Space Flight Center
JHU/Applied Physics Laboratory
National Security Agency
Electronics Radiation Characterization Project
Digital Engineering Institute
Military & Aerospace Programmable Logic Users Group
American Institute of Aeronautics and Astronautics
IEEE Aerospace & Electronic Systems Society (AESS)
Air Force Research Labs
For further information, please see the conference www home page at:
http://rk.gsfc.nasa.gov/richcontent/MAPLDCon01/MAPLDCon01.html
Article: 29319Hi, as the FPGA chip itself is permanently shrinking (still have designs with a RQFP240 with less capacity than my BGA in newer designs), I'd like to have similar trends by Conf-Eproms. Unfortunately the only changes are EPROMS with more capacity to fit the needs of greater devices, but no smaller footprints. Comparing a Fine-Line BGA 256Pin and the Conf.EPROM, the Eprom is too great IMHO. I'd like to have a conf.EPROM in SO8 or even better being integrated on Chip in the FPGA (no more external devices). As e.g. the EPC2 of ALTERA are programmable by JTAG, they are ISP and thus there seems to be no need for cases which could be put into separate programmers. What's Your opinion about this? CU, CarlhermannArticle: 29320
: I'd like to have a conf.EPROM in SO8 or even : better being integrated on Chip in the FPGA (no more external : devices). : As e.g. the EPC2 of ALTERA are programmable by JTAG, they are : ISP and thus there seems to be no need for cases which could be : put into separate programmers. :=20 : What's Your opinion about this? :=20 The Atmel "Secure-FPSLIC" will have the configuration memory internally and this is used both for the AVR and the FPGA portion. Issue closed :-) --=20 Best Regards Ulf at atmel dot com These comment are intended to be my own personal view and may or may not be shared by my Employer Atmel Sweden.Article: 29321
Sorry if I painted an overly negative tone there... We're continuing to use Handel-C because it's pretty damn useful. We do hack it to bits to do some unusual things :-) but we've used VHDL and AHDL too, and compared to them Handel-C wins hands down for our FPGA work. The beta version 3 does have problems on our tricky code, but then it's a beta, and distribution is restricted. If the final product fixes the specific problems we've found (and it probably will), we'll be using Handel-C 3 for future projects. (And no I'm not funded by them any more -- I'm free to choose chips and tools). cheers, -- JamieArticle: 29322
HI. I also built the ZILINX jtag programmer cable. I built it when drunk (you can tell very easy just from looking at the boards...) on 2 separate veroboards with long cables between them. For parallell cable I used 1.5 meter old printercable. It works very fine. / Daniel NilssonArticle: 29323
Hi all!
I'm using pipelined divider in my design.
Parameters are :
Dividend 16 bits
Divisor 14 bits
Clk/div 8
Signed
Frequency 100MHz
Latency is given by : Dividend width+remainder width+4=34 in datasheet
Vdhl simulation respect this output latency but in post-implementation
simulation, result data
arrives 6 clock before.
How to explain difference between datasheet and signal observed after
post-implementation ?
Pascal Delouche
Article: 29324
Hi,
I took a look at my Xilinx Foundation translation logfile and found a
warning about "duplicate definitions" of timing constraints. I do not
know where one of the duplicates come from. The definition, that is kept
is from my .ucf file. But where does the other come from ? How can I
turn off the other spec ?
Here is the logfile:
------
Release 3.3.06i - ngdbuild D.25
Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved.
Command Line: ngdbuild -p xcs40xl-4-pq208 -uc iser4_1.ucf -dd ..
D:\FPGA\ISER4_1\iser4_1.edf iser4_1.ngd
Launcher: Executing edif2ngd "D:\FPGA\ISER4_1\iser4_1.edf"
"d:\fpga\iser4_1\xproj\ver1\iser4_1.ngo"
Release 3.3.06i - edif2ngd D.25
Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved.
Reading NCF file "D:/FPGA/ISER4_1/iser4_1.ncf"...
Writing the design to "d:/fpga/iser4_1/xproj/ver1/iser4_1.ngo"...
Reading NGO file "d:/fpga/iser4_1/xproj/ver1/iser4_1.ngo" ...
Reading component libraries for design expansion...
Loading design module "D:/FPGA/ISER4_1/ts_counter24.ngc"...
Annotating constraints to design from file "iser4_1.ucf" ...
Checking timing specifications ...
WARNING:Ngd:706 - Duplicate definitions found for "TS_LCLK".
Keeping definition: PERIOD LCLK 40.000 nS HIGH 20000.000000 pS
Ignoring definition: PERIOD "LCLK" 40000.000000 pS HIGH 20000.000000
pS ;
WARNING:Ngd:706 - Duplicate definitions found for "TS_P2P".
Keeping definition: FROM PADS TO PADS 27.000 nS
Ignoring definition: FROM "PADS" TO "PADS" 40000.000000 pS ;
Checking expanded design ...
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Writing NGD file "iser4_1.ngd" ...
Writing NGDBUILD log file "iser4_1.bld"...
-----
Thanks
Matthias
--
-------------------------------------------------
\ Matthias Fuchs \
\ esd electronic system design Gmbh \
\ Vahrenwalder Straße 205 \
\ D-30165 Hannover \
\ email: matthias.fuchs@esd-electronics.com \
\ phone: +49-511-37298-0 \
\ fax: +49-511-37298-68 \
--------------------------------------------------
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