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Anthony Ellis wrote: > Anyone know where I can get a VHDL bus interface model (functional only) > for a PowerPC 603E. I need such for use in a test bench. > Thanks Anthony Synopsys LMC software/hardware models is just right option for you. For details please visit http://www.synopsys.com. UtkuArticle: 31601
Hello yes i think the same thing but i don't know what i have to do I launch project manager I add source files (my 5 file .vhd) And when i compile one the logiciel don't look the other file and i have a messsage ( file .vhd not found) Fred "Kent Orthner" <korthner@hotmail.nospam.com> a écrit dans le message news: wklmnf2m2a.fsf@hotmail.nospam.com... > Hi, Frederic. > > It sounds to me like you are missing a top level file. You should have a > top-level file somewhere that 'instantiates' all the other blocks. That > top level will have one set of input & output pins that you can connect > to the sub-blocks input & outputs any way you feel like. > > Hope this helps. > -Kent > > "Frederic Darre" <darre@irit.fr> writes: > > Hello, I have many files .vhd that I downloaded on the net. > > But when I compile them, I can't specifiy in project manager to see all the > > files in the same time (cause warning and error). > > How to use 5 files in vhdl for one chip (a serial port RS232) if someone > > have a prog for this please help me. > > Thanks Fred > > (excuse my english i am a poor french)Article: 31602
I suspect that there is one files that is a "top-level" file. That file is your one chip. That file will include sub-blocks. The description of those other sub-blocks will likely be other vhdl files. Usually a synthesizer/simulator can only synthesize/simulate one top-level block at a time, but that one block can call many other blocks. It sounds to me like you need to take a look at a VHDL book or a tutorial. I'm afraid that I don't know where you would find one in french. Je suis desolee! -KentArticle: 31603
Thanks you for all you do. Fred "Kent Orthner" <korthner@hotmail.nospam.com> a écrit dans le message news: wkzobtx20j.fsf@hotmail.nospam.com... > I suspect that there is one files that is a "top-level" file. That file is > your one chip. That file will include sub-blocks. The description of those > other sub-blocks will likely be other vhdl files. > > Usually a synthesizer/simulator can only synthesize/simulate one top-level > block at a time, but that one block can call many other blocks. > > It sounds to me like you need to take a look at a VHDL book or a tutorial. > I'm afraid that I don't know where you would find one in french. > > Je suis desolee! > > -Kent > >Article: 31604
Thanks Tim and Kolja for the answers. Yesterday I found that last issue of J. of VLSI Signal Processing is dedicated to reconfigurable computing. I will spend some time reading those interesting articles. Regards. Tim wrote: > Look at SRC computers, the latest in the Cray lineage. > > A problem may be that they are pretty secretive over results. > > Also, check the archives for thsi group. > > Roberto R. Osorio wrote in message <3B14EAD0.1CBDF5E8@imec.be>... > >This is just a question. > > > >Is anybody using FPGAs to execute scientific programs? > >Is it possible to find small cores in the programs that can > >be mapped onto a FPGA and obtain good speed-up? > >Which is the main problem, computing or IO bandwidth? > > > >If you are doing that, which are the results? Which kind > >of programs are you focused in: optimization, genetics, > >matrix computation, simulation, weather forecast...? > >Article: 31605
Thanks Renaud, you confirmed my suspicions. I apoligize for my use of 'compiler', when I meant 'synthesizer'. As you've probably guessed by now, I come from a software background. Kris N. Renaud Pacalet wrote: > Kris Nichols a écrit : > > > > Hey, > > I have a few concerns with regards to support for the IEEE VHDL > > libraries in HDL compilers. > > Hi Kris, > > First of all "compiler" is an ambiguous word. For most software > people and for some hardware it's a tool that converts a source > code (C, C++, Java, VHDL, Verilog, etc) in a binary object code > that is in turn converted in executable form by a linker. So it > leads to simulation. For some hardware guys it means synthesizer: > a tool that interprets the source code and tries to build a logic > gates network that implements the same behavior. There are a lot > of differences between synthesizers and true compilers but one > that is meaningful to you is that compilers usually accept the > whole syntax of while synthesizers can only handle a small subset. > > > I'm currently using Synopsys FPGA Express > > v3.3 (that comes with Xilinx Foundation 2.1i), > > That is, a synthesizer, not a compiler. > > > and have found that this > > compiler does not support the 'math_real' IEEE library for real (i.e. > > floating point) numbers, or the divide "/" function from the > > 'numeric_std' IEEE library. > > Because real stuff is not synthesizable logic synthesizers. Same > with dividers. The reason being that a FPU or a divider are too > large modules with too many different possible hardware > architectures. If you code your real operations at a too high > level of abstraction (S := A * B; S, A and B beeing floats) you > don't give enough informations about the hardware architecture you > want. So, if you really need floating point in your hardware > either use an already designed FPU or design your own (and then > you'll have to deal with sign, exponent and mantissa, left and > right shifts, infinity, not a number, zero+, zero-, etc). > > > I was wondering if anyone knows if current > > versions of Synopsys FPGA Compiler II or Synopsys FPGA Express have > > support for these libraries? Does the Xilinx XST Compiler support these > > libraries? What other professional HDL compilers are offered, which > > provide this kind of support? If these libraries aren't yet supported > > in any compilers, why is this the case? Thanks for your time. > > Every true compiler supports reals and dividers (and pointers, files, > etc). Their names are Leapfrog, Ncsim, Modelsim, VSS, etc. Not FPGA > Compiler, MAX+II, Quartus, dc_shell, ac_shell, etc. The frequent > confusion (even in this group) comes from post-synthesis simulation > capabilities of some synthesizers. MAX+II, for instance, lets you > define waveform stimulus, simulate your design and analyze the > resulting waveforms. But first of all it synthesizes your source > code because it's not a true compiler-linker-simulator, it's what we > call a gate-level simulator, all it can "simulate" is a network of > gates, a netlist. So it cannot simulate reals and dividers while > Ncsim from Cadence can. Hope it helps. > > Regards, > -- > Renaud Pacalet, ENST / COMELEC, 46 rue Barrault 75634 Paris Cedex 13 > Tel. : 01 45 81 78 08 | Fax : 01 45 80 40 36 | Mel : pacalet@enst.frArticle: 31606
Sorry the second chip is a 74FCT16952T registered transceiver. "Chuck Woodring" <woodringfam@earthlink.net> wrote in message news:yIgR6.4206$S2.244083@newsread2.prod.itd.earthlink.net... > I am building a FPDP interface in a XC4000xl chip, but the FPDP spec calls > out specific FCT logic for the interface. The 20 MHz TTL strobe calls for a > FCT806A clock driver from IDT and the DVALID and SYNC signals use a FCT15962 > ?? 16 bit register chip. > > I was hoping to bring the FPDP strobe and control signals directly into > the FPGA. Is this unrealistic? I have terminated the strobe as called for > 220 to VCC and 330 to gnd. My card is only a Receiver or Receiver master > but I am sending back the SUSPEND and NRDY signals. > > I have a XESS proto card with the interface programmed in but when I look at > the signal they look pretty distorted. The strobe actually looks ok but the > DATA VALID is shakey at best. I am unsure if it is the protocard grounding > or the fact that I haven't used the chips called for in the spec? > > Any help/thoughts appreciated. > > Thanks > > Chuck > >Article: 31607
I'm pretty frustrated with the "fancy" Java based Xilinx Software
Installer. It takes two days to install SP8 on my SUN Ultra Enterprise
450. The files reside on a Linux based RAID server, but the NFS
performance is not *that* bad.
Is there a simple tar/cpio script I can use rather than the Java
application?
Petter
--
________________________________________________________________________
Petter Gustad 8'h2B | (~8'h2B) - Hamlet http://www.gustad.com
#include <stdio.h>/* compile/run this program to get my email address */
int main(void) {printf ("petter\100gustad\056com\nmy opinions only\n");}
Article: 31608Frederic Darre wrote: > > Thanks you for all you do. > Fred > > "Kent Orthner" <korthner@hotmail.nospam.com> a écrit dans le message news: [...] > > It sounds to me like you need to take a look at a VHDL book > > or a tutorial. I'm afraid that I don't know where you would > > find one in french. > > Je suis desolee! I've got a nice .pdf file from the EPFL called "Modelisation de Systemes Numeriques Integres - Introduction à VHDL" It's a bit big (1.7M) though -- Nicolas MATRINGE IPricot European Headquarters Conception electronique 10-12 Avenue de Verdun Tel +33 1 46 52 53 11 F-92250 LA GARENNE-COLOMBES - FRANCE Fax +33 1 46 52 53 01 http://www.IPricot.com/Article: 31609
> In your case, you have CCLK doing the configuring, then your ( I assume > totally unrelated ) user clock takes over, and inow the global reset that > kept everything quiet during configuration gets released. But that release > is not instantaneous. It is a signal travelling all over the chip, and it > may take 30 ns to do so. In the meantime your clock is clocking all over > the chip. Things could get messed up. FLAME ON... And this is a HUGE beef I've had with Xilinx for nearly ten years! Why is the global reset signal NOT hard routed using a LOW SKEW net? Come on, this isn't rocket science guys! I characterized this back on the 4k series in the early 90's. I actually found that the GSR in a 4010 had nearly 80ns skew across the part! You've got lots of clocks routed with low skew nets, why has this not been done with the global reset? And then Xilinx tells users to NOT use the global reset even in the current series parts, but TO burn routing resources in the chip for a reset signal! This causes other issues, simply because the routing resources that are taken up by this reset signal can significantly effect performance of the design. I have always been able to use the GSR and accommodate the shortcomings of the bad GSR routing with careful logic design. If you did follow Xilinx "advice" and provide your own reset signal, take a look using FPGA Editor at how much routing resources it takes! My compile times went from forty five minutes to TEN minutes by using the GSR instead of a routed reset signal. FLAME turned down...but still burning with a trigger finger....Article: 31610
Allan, Good point. I actually used a frequency around 16 MHz for the system I built. Austin Allan Herriman wrote: > Austin Lesea wrote: > > > > Allan, > > > > I second that. > > > > I worked for a company that build BITS clocks for SONET, and the switchover was > > not a pretty spec. You could move less than X ns in y ms, which led to PLL's > > with poles at > 0.1 Hz. This led to really bad short term stability problems > > from the PLL having such a terrible and slow response time. > > > > If I had it to do over again, I would use a synthesizer running at 300 MHz to > > synthesize the 51.84 MHz (a digital locked loop with the A or B 51.85 as a > > reference input to be tracked), and then digitally slew the DDFS synthesizer > > from one frequency to the other. I would then remove the synthesis jitter with > > a PLL following. > > Hi Austin, > > Since you need an analog PLL following the digital frequency > synthesiser, you can digitally synthesise a much lower frequency, and > multiply up in the PLL. This is much easier to do, and saves power > without compromising performance (if designed properly, of course). > I believe that's the way the commercial ASICs work. E.g. that Semtech > chip I mentioned used a 12.8MHz reference osc. I designed one once that > used 20.0MHz as the reference clock for the NCO. > The trick is to choose the reference frequency such that the jitter you > get from sampling the various other frequencies doesn't alias close to > DC (where it can't be filtered out by the DPLL). > > Regards, > Allan.Article: 31611
Hello, We want to plug our Xilinx PCI development board in our compactPCI bacplane. Are there any passive form factor adapters out there for this kind of 'wild' testing? Thanx in advance! StevenArticle: 31612
> to develop a W2K driver > for the Spartan II PCI core. Why would you need a driver for the PCI core?Article: 31613
As a first stab, I'd consider generating a 32 bit value to logically shift
in the following two stages, allowing the masking to take place ahead of
time in one clock. The equivalents should also be as follows for a 32 bit
concatenation:
a ROR b == {a,a}>>b;
a ROL b == {a,a}>>(16-b);
a SRL b == {0,a}>>b;
a SLL b == {a,0}>>(16-b);
a SRA b == (a<0?{-1,a}:{0,a})>>b;
With stage 1 generating the {left_modified_a,right_modified_a}
concatenation (and optional 16-b), the following two shift stages (no
longer rotation) will take care of the operation.
As a next stab, I'd try to leverage the Xilinx architecture to integrate
the first stage into the following stage(s). A 4:1 mux to implement the
shift would typically use two LUTs and an F5 mux. You could use an
individual LUT per bit in the shifter and get an F5/F6 mux combination to
select from the four LUTs instead. More resources, but better speed.
Another thought, perhaps cleaner. Since there are two ROT stages in your
implementation, consider applying your masks within those stages. The
16x16 ROM can generate the *rotated* mask which is combined at the mux.
If the output is registered (rather than fed into a RAM, for instance) the
set/reset of the bits could be applied at the register as well.
With the right (intense) manipulations, you might get the entire system
down to two stages.
Good luck!
- John
Jean-Paul Smeets wrote:
> Hi,
>
> I have just finished a CPU in which the shift/logical ALU is the
> critical path.
>
> The shift ALU is 16 bits wide and implements SLL, SRL, SRA, ROL and
> ROR over 0..15 positions.
>
> Usign the following equivalences:
> a ROR b= = a ROL (16 - b)
> a SLL b == (a ROL b) AND (X"FFFF" SLL b)
> a SRL b == (a ROL (16 - b)) AND (X"FFFF" SRL b)
> ar == (others => a(15)
> a SRA b == ((a ROL (16 - b)) AND (X"FFFF" SRL b)) OR (ar AND (X"FFFF"
> SRL b))
>
> Note: X"FFFF" SLL b is generated by 16x16 ROM
>
> The basic architecture is
> stage 1:ROL 0,4,8,12
> stage 2: ROL 0,1,2,3
> stage 3A: AND with mask (SLL and SRL)
> stage 3B: AND with mask OR with replicated MSB (SRA)
>
> In a Virtex-E this requires about 15ns, which is too slow.
>
> Any ideas for speeding this up?
>
> J.P. Smeets
> business:
> Ellips
> Woenselsestr 352A
> 5623 EG Eindhoven
> tel: +31-40-2456540
> fax: +31-40-2467183
> email: jeanpaul@ellips.nl
> home:
> Loondermolen 23
> 5612 MH Eindhoven
> tel: +31-40-2465105
> email: jpsmeets@xs4all.nl
Article: 31614Try something in your UCF file of the form TIMESPEC TS_padtopad = FROM PADS TO PADS 15nS; or similar syntax. If you need to specify certain paths (as opposed to all that feed combinatorially through the device) you can narry down the pads that are constrained by using a form like PADS( "Data[*]" "Reset" ) rather than just "PADS" for each of the input and output directions. - John Kent Orthner wrote: > Hi, guys. > > Does anyone know of a way to specify a timing constraint on > a path from an input pad, maybe thrught a CLB, maybe not, to > an output pad? ie. a simple propogation delay? > > All of the timing constraints I can find seem to be referenced to > a clock. > > Note: Using Xilinx Spartan-II, ISE 3.3i SP8. > > Thanks in advance. > -KentArticle: 31615
Can someone please advise me what place and route tools to use for Xilinx virtex series FPGAs ? The ones you use to download netlist files onto the FPGA. I understand that Xilinx Alliance is one such software but I don't have any information about it. SandraArticle: 31616
I am completing the (thankfully) the final build of an old design and am
short of at least one
Altera EPX780QC132-10 or Intel KUFX780-10
Can anybody suggest a source ?
I am in the UK.
Jon
Article: 31617Since I am being quoted... An asynchronous FIFO using a dual-ported RAM has an obvious amd trivial data path. Just use one port for read and the other one for write. Detecting FULL and EMPTY is the problem, and involves address comparison, which is best done with Gray-coded addresses. Now comes the interesting part: FULL is the of interest only to the Write logic, and FULL goes active as a result of a write operation. So, the rising edge of FULL is actually a synchronous signal in the clock domain where it is to be used. But the falling edge of FULL is caused by Read, and is therefore asymchronous to the write clock. This can easily be fixed with one flip-flop: Use the combinatorially-derived FULL signal as an asynchronous PRESET and also as D input to the flip-flop, and clock it with the write clock. Do the symmetrically equivalent with EMPTY. Metastability can now only occur at the trailing edge of FULL and EMPTY, where it is irrelevant. At worst you get one unnecessary wait cycle. Hope this helps. VHDL code is in the works. Unfortunately I have to rely on others to generate it. I am a "schematosaurus", apparently a dying breed. Sigh. Peter Alfke, Xilinx Applicationc =================================== Kent Orthner wrote: > Hi, Ben. > > Peter Alfke from Xilinx has covered this topic in a number > of App notes. I suggest that you take a look at the following: > > http://www.xilinx.com/xapp/xapp051.pdf > http://www.xilinx.com/xapp/xapp175.pdf > > You may wlaso want to look at the following for some metastbility theory. > > http://www.ednmag.com/ednmag/reg/1994/062394/13df2.htm > > -KentArticle: 31618
John_H wrote: > The most effecient way to clear a block of RAM: find an FPGA that offers that > functionality... I haven't seen one. > It's all a matter of economics. CLEAR would add one transistor to the storage latch, plus the metal routing to drive it. Memory designers are not willing to make that sacrifice, especially since the world has been living with RAMs without clear for so long. Note however, slightly off-topic, that you can define the content of Virtex BlockRAM as well as distributed LUT-RAMs through configuration. So they come up all pretty and loaded at the end of configuration. And they can also be re-loaded through partial reconfiguration, but not in one clock cycle... Peter Alfke, Xilinx ApplicationsArticle: 31619
Hi,
there is one other way out: Use Virtex-II.
The 18 x 18 twos-complement multiplier with 36 outputs can (obviously) be used
as a 16-bit arithmetic shifter, and there are ways to do barrel shift also.
The delay through the multiplier, when used as a shifter is less than 4 ns.
(not yet documented in the speeds files, but will be. It's just too juicy an
application...)
Peter Alfke, Xilinx Applications
==========================
John_H wrote:
> As a first stab, I'd consider generating a 32 bit value to logically shift
> in the following two stages, allowing the masking to take place ahead of
> time in one clock. The equivalents should also be as follows for a 32 bit
> concatenation:
>
> a ROR b == {a,a}>>b;
> a ROL b == {a,a}>>(16-b);
> a SRL b == {0,a}>>b;
> a SLL b == {a,0}>>(16-b);
> a SRA b == (a<0?{-1,a}:{0,a})>>b;
>
> With stage 1 generating the {left_modified_a,right_modified_a}
> concatenation (and optional 16-b), the following two shift stages (no
> longer rotation) will take care of the operation.
>
> As a next stab, I'd try to leverage the Xilinx architecture to integrate
> the first stage into the following stage(s). A 4:1 mux to implement the
> shift would typically use two LUTs and an F5 mux. You could use an
> individual LUT per bit in the shifter and get an F5/F6 mux combination to
> select from the four LUTs instead. More resources, but better speed.
>
> Another thought, perhaps cleaner. Since there are two ROT stages in your
> implementation, consider applying your masks within those stages. The
> 16x16 ROM can generate the *rotated* mask which is combined at the mux.
> If the output is registered (rather than fed into a RAM, for instance) the
> set/reset of the bits could be applied at the register as well.
>
> With the right (intense) manipulations, you might get the entire system
> down to two stages.
>
> Good luck!
> - John
>
> Jean-Paul Smeets wrote:
>
> > Hi,
> >
> > I have just finished a CPU in which the shift/logical ALU is the
> > critical path.
> >
> > The shift ALU is 16 bits wide and implements SLL, SRL, SRA, ROL and
> > ROR over 0..15 positions.
> >
> > Usign the following equivalences:
> > a ROR b= = a ROL (16 - b)
> > a SLL b == (a ROL b) AND (X"FFFF" SLL b)
> > a SRL b == (a ROL (16 - b)) AND (X"FFFF" SRL b)
> > ar == (others => a(15)
> > a SRA b == ((a ROL (16 - b)) AND (X"FFFF" SRL b)) OR (ar AND (X"FFFF"
> > SRL b))
> >
> > Note: X"FFFF" SLL b is generated by 16x16 ROM
> >
> > The basic architecture is
> > stage 1:ROL 0,4,8,12
> > stage 2: ROL 0,1,2,3
> > stage 3A: AND with mask (SLL and SRL)
> > stage 3B: AND with mask OR with replicated MSB (SRA)
> >
> > In a Virtex-E this requires about 15ns, which is too slow.
> >
> > Any ideas for speeding this up?
> >
> > J.P. Smeets
> > business:
> > Ellips
> > Woenselsestr 352A
> > 5623 EG Eindhoven
> > tel: +31-40-2456540
> > fax: +31-40-2467183
> > email: jeanpaul@ellips.nl
> > home:
> > Loondermolen 23
> > 5612 MH Eindhoven
> > tel: +31-40-2465105
> > email: jpsmeets@xs4all.nl
Article: 31620Austin Franklin wrote: > > In your case, you have CCLK doing the configuring, then your ( I assume > > totally unrelated ) user clock takes over, and inow the global reset that > > kept everything quiet during configuration gets released. But that release > > is not instantaneous. It is a signal travelling all over the chip, and it > > may take 30 ns to do so. In the meantime your clock is clocking all over > > the chip. Things could get messed up. > > FLAME ON... > > And this is a HUGE beef I've had with Xilinx for nearly ten years! Why is > the global reset signal NOT hard routed using a LOW SKEW net? Come on, this > isn't rocket science guys! I characterized this back on the 4k series in > the early 90's. I actually found that the GSR in a 4010 had nearly 80ns > skew across the part! You've got lots of clocks routed with low skew nets, > why has this not been done with the global reset? > > And then Xilinx tells users to NOT use the global reset even in the current > series parts, but TO burn routing resources in the chip for a reset signal! > This causes other issues, simply because the routing resources that are > taken up by this reset signal can significantly effect performance of the > design. > > I have always been able to use the GSR and accommodate the shortcomings of > the bad GSR routing with careful logic design. If you did follow Xilinx > "advice" and provide your own reset signal, take a look using FPGA Editor at > how much routing resources it takes! My compile times went from forty five > minutes to TEN minutes by using the GSR instead of a routed reset signal. > > FLAME turned down...but still burning with a trigger finger.... Maybe this will be fixed with the Linux s/w release ?Article: 31621
Does anybody know of a second source for the Altera EPC1 or EPC2 configuration PROMs? The company that makes my device programmer (Needhams) stopped supporting Altera, and I need to program some serial PROMs. Thanks, -- Wade D. Peterson Silicore CorporationArticle: 31622
Hi, It's me again. How may I use the same clock signal in two components? (with Xilinx WebPack) If I define it (the clock signal) as a port of a component, I get the warning: "Gated clock is not a good design practice....". Thanks, Gonzalo AranaArticle: 31623
Hi Peter, Peter Alfke wrote: > > I am a "schematosaurus", apparently a dying breed. Sigh. > > Peter Alfke, Xilinx Applicationc There are some yongesters out here that still follow the art of "Schematosaurus". It may be in my head on the back of a data sheet that is turned into VHDL, But we still think the same! I hope one day I'll be half as good as you are!? 8o) Cyber_spook_manArticle: 31624
See the current thred "[Q]setup-time violation" cyber_spook_man Jamil Khatib wrote: > Hi, > I am trying to implement a FIFO buffer with two different clocks for > read and write. I am going to use Dual port memory core but I do not > know how to handle the flags and how to track number of bytes in the > buffer. > moreover how can I avoid metastability on the flags > > Regards > Jamil Khatib
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