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Hi, I was wondering whether anyone knew if a core module took up less or more space than its primitive counterpart (without actually having to generate etc.). In particular, I need the use of an accumulator for the Spartan II. There is an accumulator primitive, aswell as a core generated accumulator (which claims to optimise space used on FPGA etc. etc.). Does anyone know which is better? Thanks AdrianArticle: 32501
It seems that you can set DONE signal to wait until DCMs are locked in the VirtexII FPGA startup process according to Xilinx Handbook,Is this true? If DCM input clock is not prepared then DONE will never be asserted to low? Thank you! Best regards 6/28/2001Article: 32502
We had a discussion about different kind of clock muxes, but I can't find it anymore. I'm looking for a designa that selects the active of two clocks with the same frequency. I know there are different kinds of situation where some of the designs might not work, but if you have any, thanks a lot. Homann -- Magnus Homann, M.Sc. CS & E d0asta@dtek.chalmers.seArticle: 32503
Hi, my way of instancing a Xilinx Core Subtractor causes an "FPGA-LINK-7" warning in FPGA Compiler 2 on all bus-ports of the Core (one warning for each bus). The non-bus-ports don't produce that warning. FPGA-LINK-7 in words: Warning: The pin <xyz> of <instance> has no correspondence port in the design <core_whatever>. Not linked. The component-declarition is directly taken from the VHO-file generated by the CoreGen - in CoreGen everything is set to VHDL and Synopsys. Taking a look in the Core-EDF-file also everything seems to be ok. If you have any ideas, please let me know. Thanks, Andreas The Code: LIBRARY ieee; USE ieee.std_logic_1164.all; library XilinxCoreLib; use XilinxCoreLib.all; entity F_SUB11 is port( A, B : in std_logic_vector(10 downto 0); CLK : in std_logic; R : out std_logic_vector(11 downto 0) ); end F_SUB11; architecture F_SUB11_A of F_SUB11 is component sub11 port ( A: IN std_logic_vector(10 downto 0); B: IN std_logic_vector(10 downto 0); Q: OUT std_logic_vector(11 downto 0); CLK: IN std_logic); end component; -- FPGA Express Black Box declaration attribute fpga_dont_touch: string; attribute fpga_dont_touch of sub11: component is "true"; begin comp1: sub11 port map(A=>A, B=>B, Q=>R, CLK=>CLK); end F_SUB11_A; -- pragma translate_off library xilinxcorelib; configuration F_SUB11_CONF of F_SUB11 is for F_SUB11_A for all : sub11 use entity XilinxCoreLib.C_ADDSUB_V4_0(behavioral) generic map( c_sinit_val => "0", c_a_type => 0, c_sync_enable => 0, c_has_ainit => 0, c_sync_priority => 1, c_b_type => 0, c_has_c_out => 0, c_has_sinit => 0, c_has_c_in => 0, c_has_b_out => 0, c_ainit_val => "0000", c_b_width => 11, c_add_mode => 1, c_has_sset => 0, c_bypass_low => 0, c_has_q_ovfl => 0, c_bypass_enable => 0, c_has_ovfl => 0, c_has_s => 0, c_has_q => 1, c_has_a_signed => 0, c_has_aset => 0, c_has_add => 0, c_has_sclr => 0, c_latency => 1, c_has_q_c_out => 0, c_pipe_stages => 1, c_b_value => "0", c_out_width => 12, c_a_width => 11, c_has_q_b_out => 0, c_has_b_in => 0, c_b_constant => 0, c_has_ce => 0, c_low_bit => 0, c_has_b_signed => 0, c_has_bypass => 0, c_has_aclr => 0, c_high_bit => 11, c_enable_rlocs => 1); end for; end for; end F_SUB11_CONF; -- pragma translate_onArticle: 32504
The configuration problem when a VirtexII is not at the end of a chain has been acknowledged by Xilinx. It is a problem with promgen (prom file formatter). A patch is supposed to be available soon (problem exist with SP8). EricArticle: 32506
Roger, In ES material, this feature does not work. In production material, what you say is correct. Personally, I would never use this feature, but rather always have logic to deal with the case that the DCM's were unable to lock. Inability to lock may occur because the input clock is missing, or has excessive jitter. In designs that I used to do, this is a reason to turn in an alarm, with a type, and information about the failure .... not an opportunity to sit and wait for someone to figure it out. Some designers have a different style, and if it won't LOCK, it won't work anyway, so who cares if it doesn't work. DONE isn't high, or LOCKED isn't high, the result is the same.....doesn't work! Austin "Roger.chen" wrote: > It seems that you can set DONE signal to wait until DCMs are locked > in the VirtexII FPGA startup process according to Xilinx Handbook,Is this true? If DCM input clock is not prepared then DONE will never be asserted to low? > Thank you! > Best regards > 6/28/2001Article: 32507
Pete, Hats off! Many satellites use Actel parts, succesfully. Austin pete dudley wrote: > Consider Actel. > > Their one time programmable parts are quite easy to use and the > configuration cannot be upset. You can mitigate upsets in the data by using > triple redundancy in critical registers such as state machines. They even > publish a synthesis library that will automatically insert TMR logic. > > Sorry to break up the Xilinx love fest but my experience using Actel > antifuse parts for satellite customers has been really positive. > > -- > Pete Dudley > > Arroyo Grande Systems > > "Michael Boehnel" <boehnel@iti.tu-graz.ac.at> wrote in message > news:3B386F7F.C29974E0@iti.tu-graz.ac.at... > > Hi, all! > > > > State machines (SM) are made more secure with additional logic which > > detects an illegal state. If an illegal state occurs the SM is forced to > > a special state (trap state; reset state) from where it can start > > working correctly again. So far so good. > > > > What happens, if the additional logic is placed in LUTs of an FPGA? > > Aren't the LUTs vulnerable from radiation too? > > Is there a better protection for the configuration than for the FPGA's > > FFs? > > > > Michael > > > >Article: 32508
Magnus Homann schrieb: > > We had a discussion about different kind of clock muxes, but I can't > find it anymore. I'm looking for a designa that selects the active of > two clocks with the same frequency. I know there are different kinds > of situation where some of the designs might not work, but if you have > any, thanks a lot. We had this question here some weeks ago. Again, my advice have a look at the Xcell articles in ahhh, damit I forgot it again (I think it was 24) were Peter published a small nice, glitch free clock mux. There is even a patent for this ;-) (I had a look at the US patent website) -- MFG FalkArticle: 32509
qlyus wrote: > I have been thinking to switch back to Synopsys because I have full version > of Xilinx Foundation. Synopsys is slower in synthesis, its schematic view > is not really viewable. But it at least synthesizes correctly and you only > focus on your RTL code whenever there is problem, instead of chasing the > ghost as I did with Synplicity. Synopsys is worse. I wonder if they ever fixed the Xilinx clock-polarity-mux bug I found a year ago. Or the Xilinx-IOB-tristate-enable-polarity-mux bug. For those that are wondering what the hell I'm talking about, the chips have a mux in front of each flop's clock, to select the triggering edge. There's also a mux in front of the IOB's tristate enable, to select whether the output enable is active high or active low. In both cases, FPGA Express 3.4 blew it. A CLB inverter, followed by a BUFG, is inferred if you used falling-edge clocks in XC4K parts. (Look at the timing reports -- whaddaya mean, skew? Where's the two-phase clock note?) An inverter is also inferred if you write active-high output enables. ---aArticle: 32510
Try Rochester Electronics www.rocelec.com Rochester is the Altera approved manufacturer for this obsolete device. I think they have sales office in the UK. On Thu, 31 May 2001 19:07:32 +0100, Jon Schneider <jschXXneXXider@cix.co.uk> wrote: >I am completing the (thankfully) the final build of an old design and am >short of at least one > >Altera EPX780QC132-10 or Intel KUFX780-10 > >Can anybody suggest a source ? > >I am in the UK. > > Jon >Article: 32512
Here is what I got from somebody in Applications, while he was traveling. A bit vague, but may help "It is possible to attach an external clock to a global clock net, have it visit a macrocell flop configured as a Toggle, and get a divide by two. The Q of that flop can be subsequently divided again (might not want to use of a second global net, but at least two more are available). The T configuration is local to the flop and doesn't route back into the interconnect structure thereby degrading the fMAX. We don't spec the toggle frequency, which is greater than fMAX of fSYS. Those specifications are with standard interconnect delays rather than the local flip flop configuration delays. I believe the simulator gives correct timing behavior for this configuration." Peter Alfke ==================================== Falk wrote: > Nice to hear that my idea isnt that bad. But how about the toggle rate of the FFs in the 95288XL? Will it work, if I configure on FF as an T-FF and clock it via a global clock net (155 MHz, duty cycle somewere 40% or so, with only one FF connected to it) ??. > > Regards > FalkArticle: 32513
Here is what I got from somebody in Applications, while he was traveling. A bit vague, but may help "It is possible to attach an external clock to a global clock net, have it visit a macrocell flop configured as a Toggle, and get a divide by two. The Q of that flop can be subsequently divided again (might not want to use of a second global net, but at least two more are available). The T configuration is local to the flop and doesn't route back into the interconnect structure thereby degrading the fMAX. We don't spec the toggle frequency, which is greater than fMAX of fSYS. Those specifications are with standard interconnect delays rather than the local flip flop configuration delays. I believe the simulator gives correct timing behavior for this configuration." Peter Alfke ==================================== Falk wrote: > Nice to hear that my idea isnt that bad. But how about the toggle rate of the FFs in the 95288XL? Will it work, if I configure on FF as an T-FF and clock it via a global clock net (155 MHz, duty cycle somewere 40% or so, with only one FF connected to it) ??. > > Regards > FalkArticle: 32514
Here is my personal opinion, not confirmed, edited or censored by Xilinx Marketing It does not make any sense to use XC4000 parts for new design ( unless there are strange circumstances, like no 3.3-V supply available, which would be a weird situation today ). You get better price, performance, density with more modern parts. Xilinx has a tradition of keeping the main-stream families in production for a long time. We obsoleted XC2000 only after >13 years in production. And we always give plenty of "last buy" warning, and then turn the die over to an "after-life supplier". I personally dislike the big XV parts, Virtex is so much better. And Spartan in any flavor beats XC5200 hands-down. 5-V parts will bite the dust long before 3.3-V parts. Always check software support, since it disappears earlier than the parts ( yes, you can always use old software, but who wants to?) I often explain FPGA evolution as being at least 15 times faster than human aging. So, Virtex being 3 years old, is in its mid-life (bulging waist, hairline receding...), pushed along by the more virile Virtex-E. And any XC4000 is really a very senior citizen. The original XC4000 was introduced ten years ago. But all these parts can live to be 200, they will just not be competitive. :-) We use rapidly declining prices on the new parts as an incentive to discourage you from starting anything with the old families, which cannot be price reduced, since their technology is stagnant. Old-technology wafers don't get any cheaper... Just random thoughts. Peter Alfke ======================================= finish wrote: > hello, > > with the outcome of virtex,virtex-e, virtex-II, should we have the > right to still speak about Xc4k design ? > for how long will you expect the Xc4k to still exist? > which type precisely, E?,EX,XV > thanksArticle: 32515
Brian Drummond wrote: > I have resorted to reading .edf files and comparing parts that worked > with parts that don't. Typically: the individual output enables (ENBFF) > have been optimised away leaving a single signal; or they have the wrong > polarity (they must be active low); or the (INFF/OUTFF) flop was part of > a chain that has been optimised into a SRL; or the (OUTFF) flop has been > combined with an identical one whose output was used internally; or > something like that. > You can go one better and use the post-synth Verilog/VHDL netlist instead of the EDIF. and still one better if you can afford the $$$ for something like Synplify's HDL Analyst [I'll get my colleagues to give up their summer holidays eventually]. > > Modifying the design into one that the synthesiser won't screw up has > been, for me, a tedious and iterative process (not helped by the poor > diagnostics) Absolutely right. Its tedious in the extreme and there no guarantee that when you fixed it in one place it won't pop up again some bloody where else and then, when you take your eye off it, back it comes in the first place with the next rev of the synth tool. Its nice (?!) to know its not just Synplify that makes this basic Xilinx architectural error.Article: 32516
--------------06C6D15E170BDB132B974894 Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit Falk Brunner wrote: > We had this question here some weeks ago. Again, my advice have a look > at the Xcell articles in ahhh, damit I forgot it again (I think it was > 24) were Peter published a small nice, glitch free clock mux. There is > even a patent for this ;-) (I had a look at the US patent website) > The circuit is described at http://www.xilinx.com/xcell/xl24/xl24_20.pdf and a variation is implemented in the Virtex-II Global Clock Buffer. And any designer is hereby given a license in perpetuity to use this trick in any Xilinx part. Just so we don't restart the patent discussion... :-( Peter --------------06C6D15E170BDB132B974894 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> <p>Falk Brunner wrote: <blockquote TYPE=CITE>We had this question here some weeks ago. Again, my advice have a look <br>at the Xcell articles in ahhh, damit I forgot it again (I think it was <br>24) were Peter published a small nice, glitch free clock mux. There is <br>even a patent for this ;-) (I had a look at the US patent website) <br> </blockquote> The circuit is described at <p><u><A HREF="http://www.xilinx.com/xcell/xl24/xl24_20.pdf">http://www.xilinx.com/xcell/xl24/xl24_20.pdf</A></u><u></u> <p>and a variation is implemented in the Virtex-II Global Clock Buffer. <p>And any designer is hereby given a license in perpetuity to use this trick in any Xilinx part. <p>Just so we don't restart the patent discussion... :-( <p>Peter <br> </html> --------------06C6D15E170BDB132B974894--Article: 32517
The HDL analyst is an invaluable tool for looking at what the synthesizer produces. The "technology view will tell you at a glance if synthesis made an IOB break the rules. Still, better reproting either in the synthesis or in the xilinx mapper would be good things. Brian Drummond wrote: > On Wed, 27 Jun 2001 09:13:20 -0400, Keith R. Williams > <krw@attglobal.net> wrote: > > >In article <9hb26c$jav$1@slb6.atl.mindspring.net>, > >austin@da98rkroom.com says... > >> > >> > The xilinx > >> > mapper will push the FF's to the IOBs if you set the IOB FF's option > >> > appropriately provided the rules are met for the IOB FFs. > >> > >> That's what I do. It is the "pr -b" option to map: > >> > >> map -pr b filename > > > >I've tried all of the above and it still appears the flops aren't > >getting pushed into the IOBs (this is a XCS40XL-BG256). Map reports: > > > > Number of External IOBs 190 out of 224 92% > > Flops: 0 > > Latches: 0 > > > >---- > > Keith > > map -pr b doesn't always map IOB flops. > > Using my synthesis tool (Leonardo) I had a frustrating time getting the > IO flops where I wanted them. If it doesn't happen right away, there > will be a reason, somewhere, that prevents the mapping. Typically you > express a desing that allows the mapping, but the synthesis tool > optimises it into one that doesn't. And in my opinion the diagnostics > are seriously lacking .... MAP probably knows why it can't move that FF > into that IOB, but it isn't going to tell you... > > I have resorted to reading .edf files and comparing parts that worked > with parts that don't. Typically: the individual output enables (ENBFF) > have been optimised away leaving a single signal; or they have the wrong > polarity (they must be active low); or the (INFF/OUTFF) flop was part of > a chain that has been optimised into a SRL; or the (OUTFF) flop has been > combined with an identical one whose output was used internally; or > something like that. > > Modifying the design into one that the synthesiser won't screw up has > been, for me, a tedious and iterative process (not helped by the poor > diagnostics) > > Keith: you could check your design for the abovementioned conditions > (not an exhaustive list) and see if fixing them corrects the problem. > > XILINX: > 1) You could improve the MAP diagnostics to say why flops couldn't be > mapped ... e.g. > <pin>: ENBFF - not mapped into IOB, shared enable signal. > <pin>: OUTFF - not mapped into IOB, shared output signal. > etc... > > 2) You could actually describe the UCF constraints in the documentation > (I only found out about IOBDELAY from the answers database, looking for > something else. Try searching for it in the supplied documentation...) > > Synthesis vendors: you could improve the behaviour (or at least > diagnostics) to attributes/constraints (preserve_signal) etc. I have had > mixed luck with these attrributes, and never quite gotten to the bottom > of why. (somehow, the signal I was preserving was optimised away anyway. > Do you need both "noopt" and "preserve_signal", or what?) > > - Brian -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 32518
Take a look at the multipliers page on my website. There are many ways to build the multiplier, and which is best for an XC4K depends on how many clocks per multiply you have. Your best bet, assuming serializing and then using a scaling accumulator is too slow, is to go with the computed partial product construction. In most cases, you'll do fine just using the multipliers generated by coregen. finish wrote: > hello, > > i want to implement parallel-parallel multiplier for Xc4k,( > coefficient variable ), which architecture will you recommend ? > > how coding this in VHDL, using just C=a*b > how performant will be if we just code it in vhdl using the equation > Out=A*B, has someone done any investigation in the matter ? > > thanks -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 32519
Peter Alfke schrieb: > > Here is what I got from somebody in Applications, while he was traveling. > A bit vague, but may help > > "It is possible to attach an external clock to a global > clock net, have it visit a macrocell flop configured as > a Toggle, and get a divide by two. The Q of that flop > can be subsequently divided again (might not want > to use of a second global net, but at least two more > are available). The T configuration is local to the flop > and doesn't route back into the interconnect structure > thereby degrading the fMAX. We don't spec the toggle > frequency, which is greater than fMAX of fSYS. Those > specifications are with standard interconnect delays > rather than the local flip flop configuration delays. I believe > the simulator gives correct timing behavior for this > configuration." > > Peter Alfke Thanks a lot for you efford, but the guys working on this project are too afraid of this "tricks" (this one and the low-cost ECL converter), too less time to do some test and so on . . . too much sissis around ;-) -- MFG FalkArticle: 32520
--------------86891A175B59E6E64F3FC32D Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit As they say in America: "No guts, no glory". Peter Falk Brunner wrote: > Thanks a lot for you efford, but the guys working on this project are > too afraid of these "tricks" (this one and the low-cost ECL converter), > too little time to do some test and so on . . . too many sissis around ;-) > > -- > MFG > Falk --------------86891A175B59E6E64F3FC32D Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> As they say in America: <br><b>"No guts, no glory".</b> <br>Peter <p>Falk Brunner wrote: <blockquote TYPE=CITE>Thanks a lot for you efford, but the guys working on this project are <br>too afraid of these "tricks" (this one and the low-cost ECL converter), <br>too little time to do some test and so on . . . too many sissis around ;-) <p>-- <br>MFG <br>Falk</blockquote> </html> --------------86891A175B59E6E64F3FC32D--Article: 32521
A non-techie question.... With the current down turn in profits and stock prices falling. The Job market here in the UK has started to get flooded with engineers that are being laid off and people are starting to get very unsettled. All this is tempting me to move to the USA as I constantly see more interesting job advertised and for good money. I also know that your house prices are better then ours and petrol (gas) is a lot lower. So my question is... What's the catch? do you all sleep well at night knowing that there is enough in the bank to pay the bills? The grass looks very green and very tasty from this side of the pond! Regards Cyber_spook_manArticle: 32522
There are three basic issues: 1. You have to find a job, i.e. an employer 2. You have to get a visum, i.e. work permit. The US is not part of the EU, so this is a major, major hurdle and headache, but it can be done. 3. You have to keep you spouse/girlfriend happy. She is much more severely exposed to the cultural difference of any foreign environment than you are. I have seen many "re-migrants" because the wife ( and kids ) could not cope. I have done it twice, first Germany to Sweden, then -10 years later- Sweden to US. It can be very rewarding, but it is not a "piece-of-cake". Peter Alfke ---------------------------------------------- cyber_spook wrote: > A non-techie question.... > > With the current down turn in profits and stock prices falling. The Job > market here in the UK has started to get flooded with engineers that are > being laid off and people are starting to get very unsettled. > > All this is tempting me to move to the USA as I constantly see more > interesting job advertised and for good money. I also know that your > house prices are better then ours and petrol (gas) is a lot lower. > > So my question is... What's the catch? do you all sleep well at night > knowing that there is enough in the bank to pay the bills? The grass > looks very green and very tasty from this side of the pond! > > Regards > > Cyber_spook_manArticle: 32523
"cyber_spook" <pjc@cyberspook.freeserve.co.uk> wrote in message
news:3B3BA005.8DEC43F9@cyberspook.freeserve.co.uk...
> A non-techie question....
>
> With the current down turn in profits and stock prices falling. The Job
> market here in the UK has started to get flooded with engineers that are
> being laid off and people are starting to get very unsettled.
>
> All this is tempting me to move to the USA as I constantly see more
> interesting job advertised and for good money. I also know that your
> house prices are better then ours and petrol (gas) is a lot lower.
>
> So my question is... What's the catch? do you all sleep well at night
> knowing that there is enough in the bank to pay the bills? The grass
> looks very green and very tasty from this side of the pond!
>
> Regards
>
> Cyber_spook_man
**************************************************
First, you will have to change your "handle." Anything with
"spook_man" might get your arse kicked in certain parts of the USA.
Second, when the grass looks very green on the other side, usually the
water bill is very high.
Although it may not seem that way from the ads that you are seeing, I
am seeing engineers getting layed off here in the USA as well. Every month
I hear of engineers getting layed off and looking. If you come over with a
company sponsoring you, you may be safe for a year and everyone is hoping
that the market picks up after that. There was an article in Newsweek about
a month ago about foreign engineers who are being let go and have no place
to go because they can only work for the company that sponsored them and
layed them off. Althought he article was somewhat biased, I did see some
merit in it. If I were a foreign engineer, my preference would be to come
to the USA when the market is good. That way, you can establish yourself
and be more secure when hard times come.
Simon Ramirez, Consultant
Synchronous Design, Inc.
Oviedo, FL
USA
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