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Hi Matt; Thanks for your reply. At the same time I posted here, I asked my local Xilinx FAE about it. A correct version of the UCF has made it to my inbox. In your opinion, am I taking a risk from a timing perspective by moving the core to a single quadrant? I am too early in the design to run it through place and route to check for myself. Regards, Jamie "Matthieu Cossoul" <Matt.Cossoul@xilinx.com> wrote in message news:3B257AEC.3932EFAB@xilinx.com... > Jamie, > > That's a feature and a bug: > . the feature: the TBUF placement algorithm is assuming that the datapath (ADs > and CBEs) is surrounding RDY signals, which makes some sense timing wise. > . the bug: the test that was supposed to enforce this didn't report an error as > it was supposed to. > > Gathering all PCI signals on a single bank is freeing up a bank where a > different IO standard could be used. The new version of the UCF Generator to be > released this Friday would now allow you to do that. Meanwhile, I could > generate for you the UCF you need. > > Sorry for the inconvenience, > - MattArticle: 32126
Martin, please tell us *when* INIT goes Low. Peter Alfke Martin Forest wrote: > We observe a problem when programming a Virtex II XC2V1000 if the device is not at the end of the configuration chain. > > We used a concatenated configuration bitstream (generated by Xilinx PROM file formatter). During the configuration, the XC2V1000 FPGA receive the appropriate bitstream but don't transfer by DOUT pin the next bitstream to the next device of the chain. In more the INIT pin is drived low to indicate an error. > > -> Our configuration clock is 4MHZ > -> We used the ServicePack #8 > -> The configuration EEPROM is XC18V04vq. > > If someone have an idea, could you share it. > martin_forest@nmss.com > > ThanksArticle: 32127
Jamie, In the Virtex-II part you're using, it does meet timing with the Ping reference design (which is provided with the core) in a -4 speed grade. So that looks pretty safe. Regards, - Matt Jamie Sanderson wrote: > Hi Matt; > > Thanks for your reply. At the same time I posted here, I asked my local > Xilinx FAE about it. A correct version of the UCF has made it to my inbox. > > In your opinion, am I taking a risk from a timing perspective by moving the > core to a single quadrant? I am too early in the design to run it through > place and route to check for myself. > > Regards, > JamieArticle: 32128
Hi B.E, I checked all the settings from your report file, and they seem to be the defaults that match what i used. I've reinstalled maxplus2 and the patch, but that didn't fix it. Do you have just the 10.0-10.01 patch applied, or are there other patches? TIA bob elkind wrote: > > As I mentioned in previous followup, your source code compiled without > problems on my machine. One place to look for clues is the logic synthesis > settings section of the report file, and another place to check would be > pin assignments (in the .ACF file). > > -- Bob Elkind, the e-team fpga design, consulting > > Russell Shaw wrote: > > > bob elkind wrote: > > > > > > Hmmm.... I had no probs with 10.0 (no patch). I wonder if the patch > > > may be a problem. Maybe someone else listening in on this thread might > > > have some data to help correlate our experiences. Also, I was targeting > > > only 6K and Acex1K devices. > > > > Hi, > > > > I had the problem with maxplus2 10.0. I applied the latest patch to > > get 10.01, but still get the same problem. The file that causes the > > quartus fitter to crash when doing an auto acex1k device is: > > > > INCLUDE "lpm_fifo_dc.inc"; > > > > SUBDESIGN fifo > > ( > > data[7..0] : INPUT; > > wrreq : INPUT; > > rdreq : INPUT; > > rdclock : INPUT; > > wrclock : INPUT; > > q[7..0] : OUTPUT; > > rdempty : OUTPUT; > > ) > > > > -- rest of design source code snipped -- ___ ___ / /\ / /\ / /__\ / /\/\ /__/ / Russell Shaw, B.Eng, M.Eng(Research) /__/\/\/ \ \ / Victoria, Australia, Down-Under \ \/\/ \__\/ \__\/Article: 32129
Russell, I've not installed *any* patches to Max+2 10.0. We could be here forever. Why don't you just email me your .ACF file and your .TDF file(s). I'll see if it compiles on my machine. If it does compile, then you may want to re-install MAX+2 without any patches, see if it runs, then install a patch and see if it still runs, etc. etc. -- Bob Elkind, the e-team, fpga/design consulting. Russell Shaw wrote: > Hi B.E, > > I checked all the settings from your report file, and they seem to be > the defaults that match what i used. I've reinstalled maxplus2 and the > patch, but that didn't fix it. > > Do you have just the 10.0-10.01 patch applied, or are there other > patches? > TIAArticle: 32130
Hello, Thank you for your answer. I think this is a time an effort problem, I would like to convert all the gates to 'comprehensible' VHDL, maybe the fastest way is to understand the design and redesign it in VHDL without copying the schematics sheet by sheet and gate by gate. Anyway we'll see. Thanks all of you. "Ulises Hernandez" <ulisesh@ecs-telecom.removeplease.co.uk.invalid> wrote in message news:992445896.9765.0.nnrp-08.c2de5a16@news.demon.co.uk... > Hello to the group, > > I am currently working in FPGA designs. We are now investigating if is > possible to upgrade a design. This is an old design which was implemented in > a XC5215 FPGA and was built using schematics :-((, the schematics were done > using Mentor Graphics tools. This tool generates the EDF file which you use > for the build process, we will probably migrate this design to the Spartan > II family. But my personal challenge will be to pass them to VHDL. It is a > nightmare I know, os I would like to know if someone knows some software to > convert to VHDL a EDF file o convert to VHDL a schematic using Mentor tools. > There must be something, to pass it to Verilog will do but it much better to > VHDL. Maybe the VHDL generated is quite poor but easier to modify than the > schematics. > > Thank you to all in advance. > > Ulises Hernandez > Design Engineer > > > >Article: 32131
Hi, We are about to use a NIOS solution in an APEX 200E. Are there any known problems with the NIOS ? Is it really as performant as ALTERA says ? Are the developpement tools easy to use ? Are they powerfull ? In fact is it really worth using it rather than a small microcontroller with flash and ISP ??? Thanks. Stephane. Thales Microelectronics.Article: 32132
Try, http://www.fpga-guru.com/links.htm HTH, Srini juanjo wrote: > > I´m very interested in FPGAs. Where I can find a tutorial about FPGAs? > > Thank you -- Srinivasan Venkataramanan (Srini) ASIC Design Engineer, Chennai (Madras), IndiaArticle: 32133
> Thank you for your answer.
> I think this is a time an effort problem, I would like to convert all the
> gates to 'comprehensible' VHDL, maybe the fastest way is to understand the
> design and redesign it in VHDL without copying the schematics sheet by
sheet
> and gate by gate.
> Anyway we'll see.
>
> Thanks all of you.
>
> "Ulises Hernandez" <ulisesh@ecs-telecom.removeplease.co.uk.invalid> wrote
in
Ulises,
I agree with you. I think it would be worth the effort to convert an
old design to VHDL (or Verilog), especially since old designs tend to be
smaller than new designs. I have done several conversions with great
success.
One problem you might watch out for, though, is timing. If the old
design is completely synchronous, then a new design will work better,
because it is typically faster and will meet the clock to clock timings
easier. However, if the old design is asynchronous, which could involve
race conditions, the faster speeds and the randomness of an FPGA place and
route can cause problems. I suggest that you look for anything that is
asynchronous in nature and try to redesign it into a synchronous function.
Another problem area is internally generated clocks. They can generally be
designed out and replaced by more FPGA-friendly designs.
Good luck.
Simon Ramirez, Consultant
Synchronous Design, Inc.
Oviedo, FL USA
Article: 32134Here are some of the language support improvements in XST for the 4.1i release: Support generate statement (example: processes under generate) including "begin" key word in "if...generate" statement Support multi-dimensional constants Support multi-dimensional arrays Support "exit" statement Support "next" statement Support conditional signal assignment without ELSE Support functions in vector declarations Support such expressions like "funct(ND)(2 downto 0)", where funct is a function name Support "type'predifined_attribute" expressions Support description of control signals of FF when only one bit of the vector is used (ex: falling_edge(signal(i))) Configuration statement, generally used in simulation. Support "+", "-", etc. in the "use" statement etc. We are constantly working on improving the language coverage of XST and appreciate any feedback regarding such and indeed any other aspect of the tool. Brian. Ian Young wrote: > Brian Gogan <briang@xilinx.com> wrote: > > >Full support of VHDL'93 generate statements will be available in XST > >in the next release of the Xilinx tools, due the end of August. > > Interesting (and welcome). Can you say anything about any other parts > of VHDL'93 you're planning to tackle in the same release? > > -- IanArticle: 32136
On Thu, 14 Jun 2001 08:39:41 +0100, "Ulises Hernandez" <ulisesh@ecs-telecom.removeplease.co.uk.invalid> wrote: >Hello Rick, > >Thank you for your answer. > >I have tried to convert the NGD file to VHD file. >I have now a nice and incomprehensible file of 29000 lines of code with all >the simprims in it (and this is the smallest LCA). > >I tried to synthesize this file with Leonardo without converting the >primitives to VHDL RTL mode (Just trying). It didn't work as you probably >knew. If you're using Leonardo, can't it read the EDF file directly? (And write VHDL from Leonardo using the inbuilt Xilinx library, if you so want?) You may need to load the XILINX primitive library first... - BrianArticle: 32137
<!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> Dear Mr. Fuchs, <p>Please find enclosed 2 VHDL files which whows 2 different was to describe output FFs and tristate buffers: <ul> <li> In the first case (iobs_1.vhd) the 8-bit data register <b>data_reg</b> and the FF controlling tri-state buffers <b>control_ff</b> are described separately. I applied IOB attribute to the both of them and XST will replicate <b>control_ff</b> 7 times and attach IOB attributes in NCF file. You do not have to manually replicate <b>control_ff</b> in the HDL code. In the current release XST will remove these FFs. In the next release this has been fixed and there is an additional switch to prevent the removal of equivalent FFs.</li> <li> In the second case (iobs_2.vhd), to describe the same functionality I used a Synchronous OE template. In the current release this method will not work but will be available in the 4.1i release.</li> </ul> <p><br>Here are some additional notes concerning IOB constraint: <ul> <li> IOB constraint must be applied:</li> <ul> <li> to the FF instance, if the FF is directly instantiated in the HDL code</li> <li> to the output signal of the FF, if the behavioral description is used.</li> <br>NOTE: if FF is an output FF, then today XST does not allow you to apply this constraint directly to the output port. The user must: <ul> <li> declare the signal representing the FF as “signal” and not as an output port, and</li> <li> apply the IOB attribute to this signal.</li> </ul> The fix for this issue is done in 4.1i.</ul> </ul> <p><br>Please let me know if you have further questions. <br>Have a nice week-end <p>Sergei. <p>------------------------------------- <br>Sergei Storojev, <br>XST Technical Marketing Engineer <br>Grenoble, France <br>tel (direct): +33 4 76 70 51 04 <br> <p>========================== IOBS_1.VHD ============================= <br><tt>library ieee;</tt> <br><tt>use ieee.std_logic_1164.all;</tt> <br><tt>use ieee.std_logic_unsigned.all;</tt> <p><tt>entity design is</tt> <br><tt> port(clk : in std_logic;</tt> <br><tt> SEL : in std_logic;</tt> <br><tt> A,B : in std_logic_vector (7 downto 0);</tt> <br><tt> REZ : out std_logic_vector (7 downto 0)</tt> <br><tt> );</tt> <br><tt>end design;</tt> <p><tt>architecture archi of design is</tt> <p><tt> signal arith_res, data_reg : std_logic_vector (7 downto 0);</tt> <br><tt> signal control_ff : std_logic;</tt> <br> <p><tt> attribute IOB: string;</tt> <br><tt> attribute IOB of control_ff: signal is "true";</tt> <br><tt> attribute IOB of data_reg: signal is "true";</tt> <br><tt>begin</tt> <p><tt> arith_res <= A + B;</tt> <br> <p><tt> process(clk)</tt> <br><tt> begin</tt> <br><tt> if (clk'event and clk='1') then</tt> <br><tt> control_ff <= SEL;</tt> <br><tt> data_reg <= arith_res;</tt> <br><tt> end if;</tt> <br><tt> end process;</tt> <br> <p><tt> REZ <= data_reg when control_ff = '0'</tt> <br><tt> else "ZZZZZZZZ";</tt> <p>end archi; <br> <p>========================== IOBS_2.VHD ============================= <br><tt>library ieee;</tt> <br><tt>use ieee.std_logic_1164.all;</tt> <br><tt>use ieee.std_logic_unsigned.all;</tt> <p><tt>entity design is</tt> <br><tt> port(clk : in std_logic;</tt> <br><tt> SEL : in std_logic;</tt> <br><tt> A,B : in std_logic_vector (7 downto 0);</tt> <br><tt> REZ : out std_logic_vector (7 downto 0)</tt> <br><tt> );</tt> <br><tt>end design;</tt> <p><tt>architecture archi of design is</tt> <p><tt> signal arith_res, data_reg: std_logic_vector (7 downto 0);</tt> <p><tt> attribute IOB: string;</tt> <br><tt> attribute IOB of data_reg: signal is "true";</tt> <br><tt>begin</tt> <p><tt> arith_res <= A + B;</tt> <br> <p><tt> process(clk)</tt> <br><tt> begin</tt> <br><tt> if (clk'event and clk='1') then</tt> <br><tt> if (SEL = '0') then</tt> <br><tt> data_reg <= arith_res;</tt> <br><tt> else</tt> <br><tt> data_reg <= "ZZZZZZZZ";</tt> <br><tt> end if;</tt> <br><tt> end if;</tt> <br><tt> end process;</tt> <p><tt> REZ <= data_reg;</tt> <br> <p><tt>end archi;</tt> <br> <p>Matthias Fuchs wrote: <blockquote TYPE=CITE>Hi ! <p>How can I force tristate enable registers into IOBs (xilinx Spartan II) <br>? <p>The synthesis tool (XST) makes one register out of the following 16 <br>registers. But I want 16 registers directly in the IOBs ! How can I code <br>this without using the IOBUFs in the VHDL code ! <p>-- generate 16 tristate enable register <br>gen1: for i in 0 to 16-1 generate <br> process(clk, reset) <br> begin <br> if reset='1' then <br> ge_mem_oe_reg(i) <= '1'; <br> elsif rising_edge(clk) then <br> ge_mem_oe_reg(i) <= ge_mem_oe; <br> end if; <br> end process; <br> end generate; <p>-- 16 tristate enable buffer <br>gen2: for i in 0 to 16-1 generate <br> GE_MEM_D(i) <= ge_mem_out_reg(i) when ge_mem_oe_reg(i)='0' else 'Z'; <br> end generate; <p>Matthias</blockquote> </html>Article: 32138
I am going to describe the case because Martin is temporarily out of the office. The exact number of bits has not been counted but by the approximative time, it seems to go low at the end of the second bitstream. I don't know if it is related but we have 2 other different boards for which the VirtexII is the last in the chain and the people had to disable the CRC checking to be able to make the board work. In the current case, changing the CRC checking don't change anything. Thanks. Eric eric_lewis@nmss.comArticle: 32139
Hi, I would like to program the FPGA via the parallel port in slave parallel mode. I'm using a spartan-II. I'm thinking to conecct D0~D7 to parallelport D0~D7. Strobe to CCLK, Busy/Dout to Busy, nSelect to nWrite, nPinit to nCs. But I don't know what to do with nProgram. I vill use the parallel port after the FPGA is programed to boot a yprocessor so all parallel conections vill be conected all time. Is it ok to have CCLK moving when the device is programed? Is this somthing anyone of yoh have an idea of? /MikaelArticle: 32140
Hi there, I just got a Triscend A7 starter kit, and wanted to use one of the UARTs to talk to another machine. I'm a little confused by the documentation, and just wondered if someone could let me know if I have the right idea. As far as I can tell from the documentation, there are two UARTs on the A7, but they don't have any pins connected to them by default. To use one of the UARTs I'd need to take the side-band signals into the CSL and connect them to pins (as specified in the board doc) using the I/O->Input and I/O->Output modules in Fastchip. -- Michael Dales --- email: michael@dcs.gla.ac.uk --- tel: +44 141 330 6297 Department of Computing Science, University of Glasgow, Glasgow, G12 8QQArticle: 32141
It is a great product but keep in mind it is work in progress.
I also thought that a small microcontroller would do the job but after I had
to change my last 3 designs the flexilibility and speed of NIOS made my life
a lot easier.
With NIOS you get the following (at least):
Quartus II (which you can use for any 100k and 200k APEX device, I
think)
NIOS development board. After playing with the board I reconfigured in
and installed it in to one of my proto products.
NIOS HDK ver 1.1.
NIOS SDK (you can also use the Cygwin compiler to generate a toolset for
your own custom CPU).
You can use APEX20K, -20KE,-20KC and ACEX1K100 devices.
I recently designed a NIOS core with a 32bit RISC CPU, 2x 32 bit timers, 40x
I/O lines including 8 dual edge IRQs, 6x Uarts with setable prescalers. The
entire design was targeted for a APEX20k100 -240pin QFP device. Using a CPLD
(3128 device) as a config device and additional I/O the PCB now boasts with
80 I/O lines. The entire PCB is only 80mm x 110mm and contains a Real Time
Clock (with onboard CR2032 battery), WDT, 1 MB Flash, 256KB SRAM, ports for
4MB external SRAM and a option to use either a crystal or oscillator. If
you need more speed (e.g. MUL command ) you can always drop a peripheral or
2 and add the new functionalilty.
The compiler is free (within bounds) which means that you can supply you
NIOS board with a compiler to a client.
Known problems?
C++ support is stil dodgy, but since version 1.01 to 1.1 they sorted out
many bugs.
Interrupts feature from PIO peripheral is still very buggy. It tends to
skip interrupts (1% loss but bad enough) but I added my own VHDL patch to
the inputs (nice feature when your CPU is in a FPGA) to filter these
glitches. I have tested IRQs at about 20 000 per second without any
problems.
Cost? Looking at my new PCB the total cost actually dropped compared to my
multi-processor 8051 card. Also I can reuse the same PCB for other FPGA
designs reducing later development cycles.
Performance? If you compare it to something like a Pentium it will come last
if you look at features such as true 32bit code (NIOS is 16 bit CPU with
32bit datapath) and floating point (FP routines slows NIOS down
considerably). If you want to replace a big 8051 design or even leaning
towards a CPU like a 386EX NIOS might be for you.
When not to get involved: If you don't have any serious Altera FPGA
background be carefull!! To get the best of NIOS you must know how to add
you own functionality, otherwise a standard off the shelf CPU is still the
best option.
My new NIOS PCB will be ready middle of July and will cost about $600. Those
interested can reply to me directly for more info.
Victor Schutte
Zerksus Engineering CC
"stephane" <sjulhes@free.fr> wrote in message
news:3B29D349.8475700E@free.fr...
> Hi,
>
> We are about to use a NIOS solution in an APEX 200E.
>
> Are there any known problems with the NIOS ?
> Is it really as performant as ALTERA says ?
> Are the developpement tools easy to use ?
> Are they powerfull ?
>
> In fact is it really worth using it rather than a small microcontroller
> with flash and ISP ???
>
> Thanks.
>
> Stephane.
> Thales Microelectronics.
>
>
Article: 32142Hi Michael, Yes, there are 2 UARTS and you have to connect the sideband signals to the pins as you describe. I will forward your posting to our support guys, so you should expect a call soon. PLease let us know what part of the documentation you found confusing, so we can improve it. from the Triscend trenches... :-) "Michael Dales" <michael@dcs.gla.ac.uk> wrote in message news:n23d91kbuu.fsf@kettle.dcs.gla.ac.uk... Hi there, I just got a Triscend A7 starter kit, and wanted to use one of the UARTs to talk to another machine. I'm a little confused by the documentation, and just wondered if someone could let me know if I have the right idea. As far as I can tell from the documentation, there are two UARTs on the A7, but they don't have any pins connected to them by default. To use one of the UARTs I'd need to take the side-band signals into the CSL and connect them to pins (as specified in the board doc) using the I/O->Input and I/O->Output modules in Fastchip. -- Michael Dales --- email: michael@dcs.gla.ac.uk --- tel: +44 141 330 6297 Department of Computing Science, University of Glasgow, Glasgow, G12 8QQArticle: 32143
Hi My name is Kevin Timmons from NEC in Milton Keynes Yes we are looking for 1 more Engineer. Can you please answer the following questions too see if you are what we are looking for. 1) What ASIC Design experience do you have?(describe breifly) 2) Do you know about the following: Unix VHDL Verilog Modelsim Synopsys DC & Formality 3) What degree do you have?. Type and Class? 4) What salary are you expecting? We provide a very good package(including company car for non graduates(and graduates after 2 years) The work is also very interesting. If this does not suit you could get your hands on Electronics Weekly. All the best agencies are advertised here. I hope this helps good luck Kevin Timmons cyber_spook <pjc@cyberspook.freeserve.co.uk> wrote in message news:3B1FEE33.C2D5BF06@cyberspook.freeserve.co.uk... > Is anyone looking for an Hardware engineer? Or can anyone recommend a > good agent? > > I live in the South East of the UK > > Regards > > Cyber_spook_man > pjc@cyberspook.freeserve.co.uk >Article: 32144
I´m very interested in FPGAs. Where I can find a tutorial about FPGAs? Thank youArticle: 32145
Is there any particularly efficient way to implement a small fast CAM, perhaps eight entries, in a Xilinx Virtex or Spartan II FPGA? The obvious approach is to use eight registers, eight comparators, and an eight-input priority encoder. This uses a lot of CLBs. The slower approach is to use a RAM, a single comparator, and have a counter cycle through the addresses. But I think this is too slow for my current needs. But is there another approach that I've overlooked? Thanks! Eric SmithArticle: 32146
Eric, There are three different ways of implementing CAMs in Virtex/Spartan-II devices. You either use LUT (distributed memory), SRL16s or BlockRAMs to implement CAMs depending on how you want the read/write cycles. SRL16 and BlockRAM based CAMs will be faster and may meet your performance requirements. We have three app. notes describing these CAM implementations at http://support.xilinx.com/apps/virtexapp.htm Refer XAPP201, XAPP201, XAPP202 and XAPP203. Coregen also offers a CAM core based on SRL16 implementation which takes one cycle to read and 16 cycles to write. For further details, check the CAM datasheet at http://support.xilinx.com/ipcenter/coregen/updates.htm -Vikram Pasham Xilinx Applications Eric Smith wrote: > Is there any particularly efficient way to implement a small fast CAM, > perhaps eight entries, in a Xilinx Virtex or Spartan II FPGA? > > The obvious approach is to use eight registers, eight comparators, and > an eight-input priority encoder. This uses a lot of CLBs. > > The slower approach is to use a RAM, a single comparator, and have a > counter cycle through the addresses. But I think this is too slow for > my current needs. > > But is there another approach that I've overlooked? > > Thanks! > Eric SmithArticle: 32147
Check out http://support.xilinx.com/xapp/xapp201.pdf and you'll find a neat little way to use SRL16 elements to build up a cam among other suggestions. Eric Smith wrote: > Is there any particularly efficient way to implement a small fast CAM, > perhaps eight entries, in a Xilinx Virtex or Spartan II FPGA? > > The obvious approach is to use eight registers, eight comparators, and > an eight-input priority encoder. This uses a lot of CLBs. > > The slower approach is to use a RAM, a single comparator, and have a > counter cycle through the addresses. But I think this is too slow for > my current needs. > > But is there another approach that I've overlooked? > > Thanks! > Eric SmithArticle: 32148
I have a question regarding the Virtex II on-chip multipliers: I would like to use the Virtex II to implement some long FIR filters (512 or 1024 taps) with 24 bit coefficients stored in block RAM (it's an audio application). From what I can gather in the data sheets, the dedicated mults can be configured either as 18x18, or possibly as multiple 9x9's. Cascading 4 mults gives me 36x36 which seems a bit wasteful of resources considering data is only 24 bits wide. How can I get the most efficienct use out of these embedded multipliers? Since the data rate is slow (96kHz) I'll be using just a few multipliers per filter, with coeffs fetched sequentially from block RAM. I was thinking of perhaps sacrificing a bit of precision by limiting filter coeffs to 18 bits, and then the FIR stage consists of a 24x18 multiplier / adder, which could then be realised by a 18x18 cascaded with several 9x9's to get a 27x18 mult, and ignoring the last 3 bits... All suggestions welcome! I would really like to keep all filter coeffs on-chip as this cuts down the overall cost and need for external I/O. Maybe someone at Xilinx would care to comment? regards, Alistair Webb. p.s: Will probably be targetting the XC2V250 device. What is the target price for this device and when will it be available? Until then I may prototype on the smaller XC2V40 part and scale up later...Article: 32149
Here are some new informations regarding our problem of configuration with the VirtexII in the midlle of the chain. Unfortunately, the done pins for the 3 FPGAs are tied together and cannot be separated. The 3 FPGAs used are BGAs. By looking at the sequence of the bits before the moment where init goes low when there are 3 bitstreams in the concatenated file stored in the serial eeprom, we have determined that the last thing written is the CRC itself. Init going low is probably a CRC error detected by the VirtexII. We have tried to concatenate 2 bitstreams instead of 3 with the Prom File Formatter and the init signal don't go low at the end of the second bitstream. By comparing the files that contain 2 concatenated bitstreams and 3 concatenated bitstreams, we have seen that only the length after the write to the LOUT register was different. All other data up to the end of the second bitstream was the same (including the CRC). Do you have any idea of what can make a difference if the concatenated files are almost the same? We have verified the write to the COR register and the bit that define the CRC has not to be verified is 1. Why in this case the CRC verified? Thank. Eric eric_lewis@nmss.com
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