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"Jesse Kempa" <kempaj@yahoo.com> wrote in message news:95776079.0408200846.3dc3d77c@posting.google.com... > "Jerry" <nospam@nowhere.com> wrote in message news:<10iakepgo6i76bd@corp.supernews.com>... > > I replaced my NIOS I with a NIOS II and did a simulation. Hummm it seems > > to take a lot more CPU time with a NIOS II. Has anyone else experienced > > this? > > > > ARRRRRGGGGGHHHHH > > Jer > > The wonderful thing about simulation is that it shows you what > happens, in detail, in your system for debugging purposes. Things like > processor cache initialization, SDRAM controller initialization, and > other things required to a get a processor-based system from power-up > to main() take a while. > > That said we offer two things which you might be interested in if you > don't want to see every bit of detail: > - "Simulation" software libraries & crt0 code for use only with RTL > simulation (skips lengthy things like cache initlaization). > - The instruction set simulator. > > Both of these are described in the Nios II SW Dev Handbook & AN333 > (Simulating Nios II processor systems). > > Jesse Ok Jesse, come Monday I will look into these things you mention. ARRRRRRGGGGGGHHHHHHH JerArticle: 72501
Thank you all.. Leon's page about CPLD,FPGA etc on http://www.geocities.com/leon_heller/pld_starter.html contains a good summary about these units. > > Dear Roland, > > > > Thank you for your clear and easy to understand summary. > > > The best way to learn about the digital designs is to use the partly > > free > > > tools and do a design by yourself. > > Can you recomment a particular one to learn CPLD/FPGA and VHDL? > > I have a simple CPLD design on my webs site that may be used with the free > Xilinx Webpack software. > > Leon > -- > Leon Heller, G1HSM > http://www.geocities.com/leon_heller > >Article: 72502
Dear Mikeandmax THANK YOU VERY MUCH for your very valuable posting. I've enjoyed reading it and learnt alot in few paragraphs. Regards, "Mikeandmax" <mikeandmax@aol.com> wrote in message news:20040820105045.12055.00004128@mb-m01.aol.com... > manygates asked: > >GAL,PAL,PLD, CPLD,FPGA, (what else...?) > > > >GAL : Generic Logic Array > >PAL : Programmable Array Logic > >PLD : Programmable Logic Device > >CPLD : Complex Programmable Logic Device > >FPGA : Field Programmable Gate Array > > > >Can someone explain with comparison what is the difference between all these > >GAL,PAL,PLD, CPLD,FPGA, (what else...?) logic units? > > > >Can all these units can be programmable with VHDL ? > > This could take awhile :) > > The most basic thing all of these have in common is the ability to create > unique circuit configurations on a standard device, and with most, the ability > to erase these configurations, and create new ones. If we had a time machine > to go back - way back, we would find only devices with fixed architecture > elements, e.g. SSI devices(small scale integration) andgates(7408) > nandgates(7400), or gates (7432) inverters (7404) and then a big jump to MSI > (medium scale integration) like 7474(d flipflop with set/reset) counters (74161 > - 4bit counter) , and the industry continues into LSI, VLSI, ASICs, > uprocessors, memories, etc.... > > then this idea of PLD - programmable logic device > by using fuses in an array, speicific configurations can be accomplished- by > connecting traces in the metal layers on a device, making the gates connected > to them form new circuits - unfortunately, fuses only work once :) - testing by > the manufacturer was limited - after all, how do we test a fuse? > > PAL programmable array logic > early PALS were in preset configurations - where fuses could acitivate some > customization - the pal16l2, the pal16r4, had and/or gate structures, or > limited registers to certain points - > somewhere along the way - UVerasable arrived, displacing one time programmable > fuses - with a nice quartz window, so you could flood the connections with UV > to reset the programming cell - and use a nice paper label to cover it up when > programmed - and with UV, testing by the manufaturer improved, as a pattern > could be built, then removed, although with 30-60minute erase times, it was > still limited - > > GALs - neat concept - all possible PAL configurations could be > accomplished,e.g., 16v8 - Variable function, as the 'macrocell' for each output > pad had both combinatorial and registered capability, and even better, these > werre electrically erasable(EECMOS) and could easily be tested and erased in > milliseconds > > Along came FPGA and CPLD > > I know I am leaving out a bunch of detail - the various vendors do a superb job > of describing in detail in their literature - > > > CPLD - Complex Programmable Logic Device > early CPLD structures were closely related to the GAL/PAL idea, and created an > array of PALs ( think LAB, or GLB, or PALblock, or functionblock) in various > sizes and what not - > CPLDs at their most basic are this A COMPLEX LOGIC BLOCK - with anywhere from > 36 to 68 inputs available per block, with a range of PTERMS(and gate) from 1 to > 160, available to drive each macrocell - combinatorial or registered. > Mostly NONVOLATILE devices(EECMOS) with some newer devices also incorporating > SRAM as part of the architecture, decent clock structures, high performance for > large, single logic level functions - think statemachines, decoders, counters > etc - > Routing and interconnect is typically a single large central routing array - so > interconnecting logic has little penalty in routing - and within the LOGIC > BLOCK - there is full interconnect for the various elements > > FPGA Field programmable Gate Array - > FPGAs are devices which can achieve significantly larger logic gate counts, > with each logic element TYPICALLY being built with a 4input LUT(look up table - > which allows pretty much any combination of 4 inputs ) with a combinatorial > and/or registered output available per logic element - each vendor has thier > own 'tweek' on this with additinal logic for muxes, carrychainsfor arithmetic/ > counting functions, etc -I'm sure others will jump in here) - nad since the > logic element is small, a lot more fit on a device!. To interconnect these > logic cells requires significant routing, or interconnect, resources, to build > a larger function out of the many small functions. Much magic is required > here, by the silicon designers to balance resource requirements, and the SW > designers, to implement algorithms which efficiently connect the elements > together. > FPGAs generally offer additional elements, e.g. RAM BLOCKS, so that more > complex system functions can be implemented within the single device. As > technology has moved forward, many different elements have found their way into > FPGA - processors, SERDES, DSPBLOCKS etc. > > MOSTLY based on SRAM processes, they offer rapid reconfigurability as well, > with the burden of storage somewhere in the system for the datastreams required > to configure the device. There are Vendors with NONVOLATILE FPGAs as well, > running form FUSE BASED(one time programmable) to Flash and eecmos based > devices which incorporate flash and eecmos memory to carry the datastream for > configuration on chip. > > I hope this was a good start - Peter, Paul, Austin, Jim, Rick, Ray, Uwe, any > others out there want to expand on these points? > > Mike Thomas > Lattice SFAE NY/NJ > > > > > > > > > > > > > > > > > > >Article: 72503
Hello, in the slice definition in XDL file, i oberserve _PINMAP ... what is the significance and purpose of this directive.!? thanks in advance Regards Varun.Article: 72504
Sean Durkin <smd@despammed.com> wrote: > readback, everything was OK, so I assume it must've something to do with > the readback interfering with the program execution in some way... 'guess somebody will have to just try that one - should be simple enough. Maybe I get a chance next week. -gArticle: 72505
On Sat, 21 Aug 2004 18:08:26 +0000, Simon wrote: > Was wondering if anyone would be kind enough to help me out here - I've been > struggling with a synthesis problem in Webpack, and would appreciate being > pointed in the right direction :-) > > XST is telling me: > > WARNING:Xst:528 - Multi-source in Unit <cpu> on signal <data<31>> not > replaced by logic > Sources are: data<31>5:data<31>, data<31>4:data<31>, data<31>3:data<31>, > data<31>2:data<31>, data<31>1:data<31>, data<31>:data<31> > WARNING:Xst:528 - Multi-source in Unit <ramController> on signal > <dataOut<31>> not replaced by logic > Sources are: I181_0:O, I180_0:O Multi source errors occur because you are setting a signal in two different always blocks, the most common cause of this is doing the reset in one block and doing an assignment in a different block. This is legal behavioral code (although a bad idea) but it's not synthesizable which is why simulators don't object but synthesis tools to.Article: 72506
Was wondering if anyone would be kind enough to help me out here - I've been
struggling with a synthesis problem in Webpack, and would appreciate being
pointed in the right direction :-)
XST is telling me:
WARNING:Xst:528 - Multi-source in Unit <cpu> on signal <data<31>> not
replaced by logic
Sources are: data<31>5:data<31>, data<31>4:data<31>, data<31>3:data<31>,
data<31>2:data<31>, data<31>1:data<31>, data<31>:data<31>
WARNING:Xst:528 - Multi-source in Unit <ramController> on signal
<dataOut<31>> not replaced by logic
Sources are: I181_0:O, I180_0:O
WARNING:Xst:528 - Multi-source in Unit <soc> on signal <_n0017> not replaced
by logic
Sources are: c:data<31>, rc:dataOut<31>, mul:data<31>, timer1:data<31>
... I'm not sure what the syntax data<31>5:data<31> means, but there are 6
of them, and the only direct manipulation of 'data' (it's a module port) is:
assign data = `ADDSUB ? addsub : `MSB'bz;
assign data = `MULTIPLY ? multiply : `MSB'bz;
assign data = `DIVIDE ? divide : `MSB'bz;
assign data = `LOGIC ? logic : `MSB'bz;
assign data = `SHIFT ? shift : `MSB'bz;
assign data = `JAL ? pc : `MSB'bz;
... which (coincidentally?) has 6 assign statements... The definitions of
the `PARAMETERS are as follows:
`define ADDSUB (opMajor == 4'b0001)
`define MULTIPLY (opMajor == 4'b0100 & opMinor[1] == 1'b1)
`define DIVIDE (opMajor == 4'b0100 & opMinor[1] == 1'b0)
`define LOGIC (opMajor == 4'b0011)
`define SHIFT (opMajor == 4'b0111)
`define JAL ((opMajor == 4'b0000) & (opMinor == 4'b0000))
... which seem orthogonal. Is the synthesis tool complaining because there
are conflicts between the modules, then ? Icarus verilog seemed to handle it
all in its' stride while simulating (though I know that's no guarantee :-) I
was under the impression that a port declared inout could be assigned
multiple times, if it only has one driver at a time, and if all others drive
it to Z. Presumably I'm not managing to keep it to one driver across all the
modules, then ?
Cheers,
Simon
Article: 72507
> On Sat, 21 Aug 2004 18:08:26 +0000, Simon wrote:
>
> > Was wondering if anyone would be kind enough to help me out here - I've
been
> > struggling with a synthesis problem in Webpack, and would appreciate
being
> > pointed in the right direction :-)
> >
> > XST is telling me:
> >
> > WARNING:Xst:528 - Multi-source in Unit <cpu> on signal <data<31>> not
> > replaced by logic
> > Sources are: data<31>5:data<31>, data<31>4:data<31>, data<31>3:data<31>,
> > data<31>2:data<31>, data<31>1:data<31>, data<31>:data<31>
> > WARNING:Xst:528 - Multi-source in Unit <ramController> on signal
> > <dataOut<31>> not replaced by logic
> > Sources are: I181_0:O, I180_0:O
>
> Multi source errors occur because you are setting a signal in two
> different always blocks, the most common cause of this is doing the reset
> in one block and doing an assignment in a different block. This is legal
> behavioral code (although a bad idea) but it's not synthesizable which is
> why simulators don't object but synthesis tools to.
>
Thanks for the help:-)
I was going to write this ...
----8<----8<----- cut here ----8<----8<-----
There were no actual 'always' blocks, it was always assigned using 'assign'
with the same sort of construct as below, but I guess that could easily have
the same problems if the conditions were not mutually exclusive throughout
all the modules (though I thought they were...). To test, I commented out
all references to 'data' in the other modules or in fact the reference to
the modules themselves, and I now get only the single error related to this:
WARNING:Xst:528 - Multi-source in Unit <cpu> on signal <data<31>> not
replaced by logic
Sources are: data<31>5:data<31>, data<31>4:data<31>, data<31>3:data<31>,
data<31>2:data<31>, data<31>1:data<31>, data<31>:data<31>
ERROR:Xst:415 - Synthesis failed
The mentions of 'ramController' and 'soc' have disappeared as expected, but
the *only* reference to 'data' being written to within the 'cpu' module is:
assign data = `ADDSUB ? addsub : `MSB'bz;
assign data = `MULTIPLY ? multiply : `MSB'bz;
assign data = `DIVIDE ? divide : `MSB'bz;
assign data = `LOGIC ? logic : `MSB'bz;
assign data = `SHIFT ? shift : `MSB'bz;
assign data = `JAL ? pc : `MSB'bz;
... as in the first post, with the conditions being assigned orthogonal
values... still confused :-(
'data' appears as an input to another module within 'cpu', but that's just a
RAM and is defined as an 'input' not an 'inout' to the RAM module, so surely
couldn't have any impact on the sources to the 'data' bus...
----8<----- cut here ----8<----8<-----
... but I've just figured out that in a 32-bit-wide processor, `MSB is
defined to be 31 and the assign statements all need to be of the form:
assign data = `CONDITION ? value : 32'bz;
AAaaaarrrrgggghhhh. Talk about staring you in the face :-(( I'm guessing
then that the message data<31>.. only refers to the 32nd bit of the data
bus, and not [31:0] as I had assumed...
Cheers,
Simon
Article: 72508On Mon, 16 Aug 2004 22:47:24 GMT, maxfoo <maxfoo@punkassSPAM.com> wrote: >For the xilinx xc2c256 cpld tq-144 package, when connecting to a jtag header, >according to the table in the datasheet pin 8 is Vaux(jtag supply). >My question is do you need to connect the other vcc pins too, 1,37,84,etc... >or is pin 8 the only one needed? On the xc9572 all vcc pin are connected >together... > >TIA > Forget it, I figured it out for myself, if anyone's interested in my conclusion email me. If not... bye bye!Article: 72509
Ok, another problem, but this time it's a little less likely to be staring me in the face, I think :-) Any help/information/pointers to where I could figure it out from very gratefully received :-) I have a placed, routed, and statically-timed design, and I wanted to see if I could floorplan it into a slightly faster one - the tool's effort being pretty dire as usual. When you fire up the floorplanner in Webpack, you get the previous attempt (by the tools) in a read-only window, and your own blank-slate in an editable window. I started off by pulling a carry-chain into the editor window, finding luts that are associated and putting them into the same CLBs. This worked fine for the first carry chain, but the second one didn't (!) The tool's version has a brown-coloured chain extending for 31CY's, with LUTs packed in up and down the length of the chain. The stem of the chain name is 'c_core_Maddsub_addsub_inst_cy_XXX [CY] ...' and the stem of the LUTs is 'c_core_Maddsub_addsub_inst_lut3_XXXX [FG] ...' (where XXX varies depending on the element). It's pretty obvious they go together, and the tool manages to place them together. It won't let me do that though ? Whenever I try to drop a LUT that I can *see* next to the chain in the tool's window, it turns the mouse into a 'no-entry' cursor (circle with diagonal slash across) and won't let me place it there. I can put it anywhere else. Even more peculiarly, if I put it down on the grid elsewhere, then pick it up again, I *can* put it next to the chain... The fact that it's got [FG] after its name presumably means it's using both F and G function generators, but if I'm reading the datasheet correctly, that's not a problem: p12 of the 2nd spartan-3 datasheet: Main Logic Paths: 4 lines F1-F4 (or G1-G4 on the upper path) enter the slice ... The function generators data output D offers 5 possible paths: ... 4. With the carry chain, serve as an input to the XORF (or XORG) xor gate that performs arithmetic operations, producing a result on X (or Y) ... which is what I assume it's doing, so what am I missing ? In case it's relevant, the carry chain I could place has only 2 inputs (I0,I1) whereas this one has 4 (I0,I1,I2,I3). A 3-input chain can be easily placed just like the tool one as well... SimonArticle: 72510
On Sat, 21 Aug 2004 20:03:11 +0000, Simon wrote: > >> On Sat, 21 Aug 2004 18:08:26 +0000, Simon wrote: >> >> > Was wondering if anyone would be kind enough to help me out here - I've > been >> > struggling with a synthesis problem in Webpack, and would appreciate > being >> > pointed in the right direction :-) >> > >> > XST is telling me: >> > >> > WARNING:Xst:528 - Multi-source in Unit <cpu> on signal <data<31>> not >> > replaced by logic >> > Sources are: data<31>5:data<31>, data<31>4:data<31>, data<31>3:data<31>, >> > data<31>2:data<31>, data<31>1:data<31>, data<31>:data<31> >> > WARNING:Xst:528 - Multi-source in Unit <ramController> on signal >> > <dataOut<31>> not replaced by logic >> > Sources are: I181_0:O, I180_0:O >> >> Multi source errors occur because you are setting a signal in two >> different always blocks, the most common cause of this is doing the reset >> in one block and doing an assignment in a different block. This is legal >> behavioral code (although a bad idea) but it's not synthesizable which is >> why simulators don't object but synthesis tools to. >> > > Thanks for the help:-) > > I was going to write this ... > > ----8<----8<----- cut here ----8<----8<----- > There were no actual 'always' blocks, it was always assigned using 'assign' > with the same sort of construct as below, but I guess that could easily have > the same problems if the conditions were not mutually exclusive throughout > all the modules (though I thought they were...). To test, I commented out > all references to 'data' in the other modules or in fact the reference to > the modules themselves, and I now get only the single error related to this: > > WARNING:Xst:528 - Multi-source in Unit <cpu> on signal <data<31>> not > replaced by logic > Sources are: data<31>5:data<31>, data<31>4:data<31>, data<31>3:data<31>, > data<31>2:data<31>, data<31>1:data<31>, data<31>:data<31> > ERROR:Xst:415 - Synthesis failed > > The mentions of 'ramController' and 'soc' have disappeared as expected, but > the *only* reference to 'data' being written to within the 'cpu' module is: > > assign data = `ADDSUB ? addsub : `MSB'bz; > assign data = `MULTIPLY ? multiply : `MSB'bz; > assign data = `DIVIDE ? divide : `MSB'bz; > assign data = `LOGIC ? logic : `MSB'bz; > assign data = `SHIFT ? shift : `MSB'bz; > assign data = `JAL ? pc : `MSB'bz; > > ... as in the first post, with the conditions being assigned orthogonal > values... still confused :-( > > 'data' appears as an input to another module within 'cpu', but that's just a > RAM and is defined as an 'input' not an 'inout' to the RAM module, so surely > couldn't have any impact on the sources to the 'data' bus... > ----8<----- cut here ----8<----8<----- > > ... but I've just figured out that in a 32-bit-wide processor, `MSB is > defined to be 31 and the assign statements all need to be of the form: > > assign data = `CONDITION ? value : 32'bz; > > AAaaaarrrrgggghhhh. Talk about staring you in the face :-(( I'm guessing > then that the message data<31>.. only refers to the 32nd bit of the data > bus, and not [31:0] as I had assumed... > > Cheers, > Simon Use a case statement inside of an always block or a function.Article: 72511
hmurray@suespammers.org (Hal Murray) wrote in message news:<_sadnTQqu_1KsbvcRVn-iw@megapath.net>... > > I think you could plug some normal "master" card into the master slot, > say a PC. It will do the configuration setup work. Then just let > it sit there. > > Now you can play with your FPGA card and whatever else you have > installed. Your FPGA card can do PCI cycles to talk to other cards. I appreciate that this is so. However my PCI firmware now has to have config registers and my firmware has to go to somewhere (I have no knowledge of OS's) to find out where the other card is in the address map. There are many corners that can legitimately be cut in an embedded design. I have a device that HAPPENS to have a PCI bus that I want to connect directly to an FPGA. In the final design I can 1) Just do some writes to config registers in the other device. I know from the data sheets what a config read would get me so I won't do them. 2) As a slave I will get read and written to four locations. With complete control of the address map I can just decode AD31 and AD30. 3) I think I can do away with PAR and ignore the PERR signal but I need to check this. 4) The more that I read the more I think that I can even ignore most of IRDY and TRDY. As a master I need to set up DMA's by reading and writing registers which I think will allways be available, as a slave I might not be able to respond if my FIFOs are nearly full or empty and that is trivial. No one has moaned about spartan 3 availability for a while so hopefully I can get hold of one and throw together a PCB with a PCI site on it. ColinArticle: 72512
> assign data = `ADDSUB ? addsub : `MSB'bz; > assign data = `MULTIPLY ? multiply : `MSB'bz; > assign data = `DIVIDE ? divide : `MSB'bz; > assign data = `LOGIC ? logic : `MSB'bz; > assign data = `SHIFT ? shift : `MSB'bz; > assign data = `JAL ? pc : `MSB'bz; > Replace this portion with assign data = `ADDSUB ? addsub : `MULTIPLY ? multiply : `DIVIDE ? divide : `LOGIC ? logic : `SHIFT ? shift : `JAL ? pc : `MSB'bz; and it will work. You can't use multiple assigns on same wire variable. KelvinArticle: 72513
"Kelvin" <thefatcat28@hotmail.com> wrote in message news:cg99ef$289$1@reader01.singnet.com.sg... > You can't use multiple assigns on same wire variable. When each of the ?: values was all Z, this idiom used to correctly infer a set of TBUFs. Now that there are 0.25 TBUF/LUT and plenty of F5, etc. MUXes, this implementation style is inferior to implementing a MUX tree in LUTs. Jan Gray, Gray Research LLCArticle: 72514
hi, I think for the newer generation chips you need fpga express 3.6. Or using the free tools downloaded from Xilinx website. The last is probably the best thing to do, since Xinlinx doesn't sell fpga express anymore, and I believe that FPGA express is not on the market anymore. "Guenter Dannoritzer" <dannoritzer@web.de> wrote in message news:cg56f3$r5l$05$1@news.t-online.com... > Hello, > > I need to change some logic for a board with Spartan XL chip. I got ISE > 3.3 Foundation installed and when I want to synthesize, it tells me that > it cannot check out a license. Doing some diagnostics with the licenses > utility it tells me that the FPGA Express licenses expired in 2002. > > Does that mean I have to buy another FPGA Express licenses to do the > synthesis? > > Seems like synthesis is not for free for those old chips? I guess I > could try using a newer version, like 4.1, but I am not sure when the > FPGA Express licenses for this one will expire. > > I searched in the archives for similar postings. I found some older > postings from last year. I read from people keeping older versions of > the software. Do they buy an update of the FPGA Express license? > > Did I do something wrong with the FPGA Express licenses and I can > actually still use it? > > Thanks for the help. > > GuenterArticle: 72515
i thought multiple assign to same wire is a syntaz violation. put it in an always block, and replace assign, it's correct also. Kelvin "Jan Gray" <jsgray@acm.org> wrote in message news:Tl1Wc.115$Y%3.50@newsread2.news.atl.earthlink.net... > "Kelvin" <thefatcat28@hotmail.com> wrote in message > news:cg99ef$289$1@reader01.singnet.com.sg... > > You can't use multiple assigns on same wire variable. > > When each of the ?: values was all Z, this idiom used to correctly infer a > set of TBUFs. Now that there are 0.25 TBUF/LUT and plenty of F5, etc. > MUXes, this implementation style is inferior to implementing a MUX tree in > LUTs. > > Jan Gray, Gray Research LLC > >Article: 72516
Guenter is asking about the synthesis tools. The "classic" Xilinx tools do not include synthesis. They did back when they were current, but they no longer do. Vanheesbeke Stefaan wrote: > > hi, > > I think for the newer generation chips you need fpga express 3.6. > > Or using the free tools downloaded from Xilinx website. The last is probably > the best thing to do, since Xinlinx doesn't sell fpga express anymore, and I > believe that FPGA express is not on the market anymore. > > "Guenter Dannoritzer" <dannoritzer@web.de> wrote in message > news:cg56f3$r5l$05$1@news.t-online.com... > > Hello, > > > > I need to change some logic for a board with Spartan XL chip. I got ISE > > 3.3 Foundation installed and when I want to synthesize, it tells me that > > it cannot check out a license. Doing some diagnostics with the licenses > > utility it tells me that the FPGA Express licenses expired in 2002. > > > > Does that mean I have to buy another FPGA Express licenses to do the > > synthesis? > > > > Seems like synthesis is not for free for those old chips? I guess I > > could try using a newer version, like 4.1, but I am not sure when the > > FPGA Express licenses for this one will expire. > > > > I searched in the archives for similar postings. I found some older > > postings from last year. I read from people keeping older versions of > > the software. Do they buy an update of the FPGA Express license? > > > > Did I do something wrong with the FPGA Express licenses and I can > > actually still use it? > > > > Thanks for the help. > > > > Guenter -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 72517
Does anyone know of any inexpensive XC2V250 prototype boards for partial reconfiguration experiments with JBits? Inexpensive meaning about $300-$600 or thereabouts. The lists at Xilinx and fpga-faq.com have lots of cheap Spartans-3 (which are awful for reconfiguration) and large Virtex (2V1000+) boards, but little in the lower range Virtex-II except a $150 XC2V50 from Avnet. -- thank youArticle: 72518
Hi, rickman wrote: > Guenter is asking about the synthesis tools. The "classic" Xilinx tools > do not include synthesis. They did back when they were current, but > they no longer do. > > > Vanheesbeke Stefaan wrote: > >>hi, >> >>I think for the newer generation chips you need fpga express 3.6. >> >>Or using the free tools downloaded from Xilinx website. The last is probably >>the best thing to do, since Xinlinx doesn't sell fpga express anymore, and I >>believe that FPGA express is not on the market anymore. >> >>"Guenter Dannoritzer" <dannoritzer@web.de> wrote in message >>news:cg56f3$r5l$05$1@news.t-online.com... >> >>>Hello, >>> >>>I need to change some logic for a board with Spartan XL chip. I got ISE >>>3.3 Foundation installed and when I want to synthesize, it tells me that >>>it cannot check out a license. Doing some diagnostics with the licenses >>>utility it tells me that the FPGA Express licenses expired in 2002. >>> >>>Does that mean I have to buy another FPGA Express licenses to do the >>>synthesis? >>> >>>Seems like synthesis is not for free for those old chips? I guess I >>>could try using a newer version, like 4.1, but I am not sure when the >>>FPGA Express licenses for this one will expire. >>> >>>I searched in the archives for similar postings. I found some older >>>postings from last year. I read from people keeping older versions of >>>the software. Do they buy an update of the FPGA Express license? >>> >>>Did I do something wrong with the FPGA Express licenses and I can >>>actually still use it? >>> >>>Thanks for the help. >>> >>>Guenter > > What option do I have? I seems like the newest versions of synthesis tools like Precision do not include the Spartan XL chip either? Can I buy a license for an old version? So FPGA Express does not work either because Xilinx does not sell it anymore? Thanks. GuenterArticle: 72519
Hi Keith, Keith R. Bolson wrote: > Does anyone know of any inexpensive XC2V250 > prototype boards for partial reconfiguration > experiments with JBits? Inexpensive meaning > about $300-$600 or thereabouts. The lists at > Xilinx and fpga-faq.com have lots of cheap > Spartans-3 (which are awful for reconfiguration) > and large Virtex (2V1000+) boards, but little > in the lower range Virtex-II except a $150 XC2V50 > from Avnet. -- thank you I don't have a specific board to suggest - just something else you want to consider for partial reconfiguration experiments. The layout of the IO on the device is crucial, due to the rules of signals crossing reconfigurable modules, and "ownership" of IOBs by columns and so on. Ideally you probably want a board that has system-level IO on the left and right edges, and module-level IO along the top and bottom edges. I'm not sure if anyone has a board that's really laid out for partial-reconfig experimentation. Regards, JohnArticle: 72520
Guenter Dannoritzer wrote: > > Hi, > > rickman wrote: > > Guenter is asking about the synthesis tools. The "classic" Xilinx tools > > do not include synthesis. They did back when they were current, but > > they no longer do. > > > > What option do I have? I seems like the newest versions of synthesis > tools like Precision do not include the Spartan XL chip either? > > Can I buy a license for an old version? > > So FPGA Express does not work either because Xilinx does not sell it > anymore? > > Thanks. > > Guenter Try contacting Synopsis. I think they still sell FPGA Express and if your older chip is not supported, maybe they can sell you a "classic" copy? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 72521
"Jesse Kempa" <kempaj@yahoo.com> wrote in message news:95776079.0408200856.67f3f2fb@posting.google.com... > > The memory involved was pipelined synchronous static ram, so it needed > > things like latency settings. It's quite possible that I could have got > > something to work using the flash memory wizard (or is there a ram memory > > wizard that I missed?), but I don't think that would cover the latency. > > Incidently, are the Nios II masters latency-aware? And how about the DMA > > controller? I have a vague feeling the first answer is no, but I don't know > > about the second. It's just that if they are latency aware, they could read > > my ram chips at 3-1-1-1... timing rather than 3-3-3... I must say, though, > > that I like the way the master and slave are independant and don't need to > > know how the other side works - burst will work for masters that support it, > > and not for other masters. > > > > Aha, > > My apologies, I forgot you mentioned this was SSRAM (for some reason I > was thinking it was async). You're right about latency; this currently > requires a PTF entry to speciy max pending read transfers. > > About your question: The Nios (and Nios II) instruction master is > latency aware; after getting the first 'n' reads through the pipe, you > get a word per clock (assuming that the memory can handle it). The > data master is not latency aware. DMA controller is on both of its > masters. > This is not, as far as I can see, documented anywhere. Latency-awareness can make a big difference (it will tripple the continuous read speed from my ssram) in some applications - indeed, a particular use of the DMA is to get that sort of full burst speed. > However, this should not affect your slave peripheral design! (You > shouldn't need wait states unless your SSRAM can't handle the desired > clock speed). A master is "latency aware" if it has the > "readdatavalid" pin (Avalon spec has more detail on this). Masters > which aren't latency aware are just told to "wait" until the data > comes back (and can therefore only issue one access at a time). This > is the beauty of the whole system - masters designed with performance > in mind can get it from slaves despite pipelining between the two; > masters designed for low logic usage need not impose wait states on > the otherwise high-speed memory. > That is definitely one of the nice things about the bus. I made my ssram peripheral latency-aware, and I am currently making a latency-aware master, knowing that both would seemlessly integrate with non-latency-aware masters and slaves. > JesseArticle: 72522
Keith R. Bolson <krbolson@visi.com> wrote: > Does anyone know of any inexpensive XC2V250 > prototype boards for partial reconfiguration > experiments with JBits? Inexpensive meaning > about $300-$600 or thereabouts. The lists at If you can get JBits to work with V2Pro, there's a cheap xc2vp4-board from Memec/Insight for $199. You'ld also have to ask them for the schematics because AFAIK they are not readily available off the net (unless you bought the kit and are willing to register on their web site with the serial no. of it). (I'm really not a big JBits user, does it support V2Pro these days? If not, I guess my post becomes pretty pointless.) regards, -g -- In crustulum beatitas.Article: 72523
Hello, I have a CL = 2.5 DDR module that I drive with the plb_ddr_1.00.c. To get the CL = 2.5, I have to program the mode register of the ddr with 6. The problem is that the plb_ddr_1.00.c doesn't make the translation and make a CL = 6 ! How can I specify a CL = 2.5 to the plb_ddr_1.00.c controller ? Thank you. Stephane.Article: 72524
Synplify still supports these parts. A single vendor 1 year TBL is available. - Ken McElvain rickman wrote: > Guenter Dannoritzer wrote: > >>Hi, >> >>rickman wrote: >> >>>Guenter is asking about the synthesis tools. The "classic" Xilinx tools >>>do not include synthesis. They did back when they were current, but >>>they no longer do. >>> >> >>What option do I have? I seems like the newest versions of synthesis >>tools like Precision do not include the Spartan XL chip either? >> >>Can I buy a license for an old version? >> >>So FPGA Express does not work either because Xilinx does not sell it >>anymore? >> >>Thanks. >> >>Guenter > > > Try contacting Synopsis. I think they still sell FPGA Express and if > your older chip is not supported, maybe they can sell you a "classic" > copy? >
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