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Hi, I'd like to design a small board with a Spartan 3 and some Dynamic RAM memory. Since I'd like not to be limited by memory bandwith, I was thinking to use DDR. However I'm not an exepert in High speed board design and don't have big tool to simulate my board signal integrity, cross talk, ... I've seen some "amateur" (in the good sense of the term) board with SDRAM and simple SDRAM controller in VHDL. However for DDR, not much. So I'd like to know if it's possible to do one that would be clocked at 100Mhz DDR ( 200Mhz ) 32 bits, without eating 2000 slice of my FPGA for the DDR controller ... I'm willing to give about 500 slices for it. Of course, I've seen Xilinx app notes, but they say to simulate it all with IBIS models and I have no clue ... So just by doing a careful routing of signals ( ensure same length for all signals, preferably short, with minimum vias ), should it be possible ? Any advice ? Thanks, Sylvain MunautArticle: 71826
Hi ng, i try to understand the Xilinx Spartan2 pinout data sheet. Some VCCO's at different banks have the same pin number. See: http://direct.xilinx.com/bvdocs/publications/ds001_4.pdf E.g. XC2S100-TQ144 pin16 or pin53 and many others. The mistakes are so regularly, that i wonder if i miss anything here... Thanks for any eye openings. MIKEArticle: 71827
"M.Randelzhofer" <techseller@gmx.de> wrote in message news:2n4qrgFt0iucU1@uni-berlin.de... > Hi ng, > > i try to understand the Xilinx Spartan2 pinout data sheet. > Some VCCO's at different banks have the same pin number. > > See: > http://direct.xilinx.com/bvdocs/publications/ds001_4.pdf > > E.g. XC2S100-TQ144 pin16 or pin53 and many others. > > The mistakes are so regularly, that i wonder if i miss anything here... > > Thanks for any eye openings. I raised this with Xilinx some time ago and was told that it's intentional - something to do with getting all the packages in the same table. You should see that for the packages with more pins, they have two pins, one for each bank. IIRC you use the first of the banks, where they are duplicated for the same pin. For instance, for the XC2S15 in the VQ100 package, P26 is Vcco for bank 6, but for the TQ144, P106 is Vcco for bank 6 and P107 is Vcco for bank 5. They really ought to add an explanatory note, as it's rather confusing. LeonArticle: 71828
Sylvain Munaut wrote: > Hi, > > I'd like to design a small board with a Spartan 3 and some Dynamic RAM > memory. Since I'd like not to be limited by memory bandwith, I was > thinking to use DDR. > > However I'm not an exepert in High speed board design and don't have big > tool to simulate my board signal integrity, cross talk, ... > > I've seen some "amateur" (in the good sense of the term) board with SDRAM > and simple SDRAM controller in VHDL. However for DDR, not much. > > So I'd like to know if it's possible to do one that would be clocked at > 100Mhz DDR ( 200Mhz ) 32 bits, without eating 2000 slice of my FPGA for > the DDR controller ... I'm willing to give about 500 slices for it. > > Of course, I've seen Xilinx app notes, but they say to simulate it all > with IBIS models and I have no clue ... So just by doing a careful routing > of signals ( ensure same length for all signals, preferably short, with > minimum vias ), should it be possible ? Any advice ? For 100 Mhz this should be rather trivial. Biggest concern is how many memory chips you decide to drive. e.g. what will be your configuration for the 32 bits. Will you use a single chip (not sure if they make them that wide), two 16 bit chips or 4 8 bit chips. If you go for 4 or more, it will be tough to do the layout without proper tools and previous knowledge how to do it. If you stick to two chips and follow all the regular recommendations (short, balanced traces, etc) you shouldn't have any problems. Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and Synthesis > > > Thanks, > > Sylvain MunautArticle: 71829
The option you are looking for is AUTO_IMPLEMENT_IN_ROM. It is available only for certain Device families. The details from the Quartus II online help are: A logic option that allows the Compiler to automatically implement combinational logic in ROM (that is, in an embedded cell within an Embedded System Block (ESB) or Embedded Array Block (EAB) that is set to use ROM mode), to improve speed or area usage. Using ROM in this way can free up logic cells that would otherwise be needed to implement the combinational logic. This option is ignored if it is assigned to anything other than a design entity. The Auto Implement in ROM option is also ignored if you select Product Term as the setting for the Technology Mapper option. This option can be set in the Assignment Editor (Assignments menu) or the Analysis & Synthesis Settings page or the Fitter Settings page of the Settings dialog box (Assignments menu). This option is available for ACEX® 1K, APEXT 20K, APEX 20KC, APEX 20KE, APEX II, ARM®-based ExcaliburT, FLEX 10K®, FLEX 10KA, FLEX 10KE, and MercuryT devices. Hope this helps. - Subroto Datta Altera Corp.Article: 71830
Jesse,
The performance counter is very usefull. I used it already in Nios1, with a
custom peripheral just counting clock cycles. The point in my design was
that I use a 64 bit counter. So it is expected to never roll over. The
counter part of this is that you have to do two read actions to it to get
the time.
If you then add some classes, you can define a kind of PseudoTimer class.
Each instance keeps track of when it is started and stopped.
Finde code below.
Hope this can be of any use for someone
Stefaan.
Verilog code for counter :
module never_ending_timer(Clk, Reset, Out, A, nRD, CS);
input Clk, Reset;
input A, nRD, CS;
output [31:0] Out;
parameter bits = 64;
reg [bits-1:0] cnt;
reg [bits - 32 - 1 : 0] temp;
always @(posedge Clk or posedge Reset)
if (Reset)
begin
cnt <= 0;
temp <= 0;
end
else
begin
cnt <= cnt + 1;
if (CS && !nRD && !A) // read action on lowest DWORD
temp <= cnt[bits-1:32]; // = store highest part
end
assign Out = A ? temp : cnt[31:0];
endmodule
C++ code : (paste in some editor to see colors!)
//standard types
typedef unsigned char BYTE;
typedef unsigned short WORD;
typedef unsigned long DWORD;
typedef unsigned long long QWORD;
class STick
{
private:
volatile struct never_ending_counter
{
DWORD counter_lo;
DWORD counter_hi;
} * hw;
DWORD Lo() {return hw->counter_lo;};
DWORD Hi() {return hw->counter_hi;}; // ! first read the lower part for
latching the value!!
public:
STick(void* hw_address) { hw = (never_ending_counter*) hw_address |
(1<<31);};
~STick() { };
QWORD Ticks() {
// DISABLE_USED_HERE
// DISABLE_INTERRUPTS
DWORD lo = Lo();
DWORD hi = Hi();
// ENABLE_INTERRUPTS
return lo + (((QWORD) hi) << 32);
};
};
extern STick Tick;
class PseudoTimer
{
private :
STick* hw;
DWORD Running;
QWORD start;
QWORD delta;
public :
PseudoTimer() { hw = (STick*) &Tick; Running = 0; start = hw->Ticks(); };
PseudoTimer(void* hw_address) {hw = (STick*) hw_address; Running = 0;
start = hw->Ticks();};
~PseudoTimer() {};
//start timing measurement at zero
void Start() { start = hw->Ticks(); Running = 1;};
//restart time measurement (adds time to previous interval)
void Restart() { start = hw->Ticks() - delta; Running = 1;};
DWORD StopDWORD() { //you can use stop as a brand new starting point
QWORD t = hw->Ticks();
delta = t - start;
start = t;
if (delta > 0xFFFFFFFFFFFFFFFFL)
return 0xFFFFFFFF;
Running = 0;
return (DWORD) delta;
};
DWORD PeekDWORD() { //peak doesn't affect timer operation
if (Running)
{
QWORD t = hw->Ticks();
delta = t - start;
}
if (delta > 0xFFFFFFFFFFFFFFFFL)
return 0xFFFFFFFF;
return (DWORD) delta;
};
QWORD Peek() { //peak doesn't affect timer operation
if (Running)
{
QWORD t = hw->Ticks();
delta = t - start;
}
return delta;
};
QWORD Stop()
{ //you can use stop as a brand new starting point
QWORD t = hw->Ticks();
delta = t - start;
start = t;
Running = 0;
return delta;
};
};
"Jesse Kempa" <kempaj@yahoo.com> wrote in message
news:95776079.0407131023.1266b496@posting.google.com...
> steven derrien <steven_derrien@yahoo.fr> wrote in message
news:<ccu7n3$acg$1@python.ifsic.univ-rennes1.fr>...
> > Hi,
> >
> > Has anybody been trying to use gprof within the NIOS II IDE ?
> > We have some problems regarding the profiling data that is
> > send through the jtag interface directly to the IDE console window.
> >
> > We had a look to the documentation but there is little information
> > regarding the use of the profiler with the NIOS II.
> >
> > It seems that, to the difference of NIOS I, the profiling data
> > is sent as binary data, resulting in the following stdout trace :
> >
> > < Here the program standard output >
> > **gmon.out data follows**
> > < non readable binary data >
> > nios2-terminal: exiting due to ^D on remote
> >
> > Does anybody knows how to solve this issue ?
> >
> > Thank you in advance,
> >
> > Steven
>
> Hi Steven,
>
> Here are the basic steps to using GPROF in Nios II:
>
> (In the IDE):
> 1. Add a compiler switch, "-pg", for your src code project (in the
> C/C++ build area of the project properties). This is standard fare for
> using GPROF regardless of processor.
> 2. Add the same "-pg" switch for the compiler in your system library
> project.
> 3. Check the "use profiling library" checkbox in syslib properties.
>
> (From the SDK Shell):
> 4. Run your program: Use nios2-terminal's "--gmon" switch which will
> automatically capture the profiling data into a 'gmon.out' file after
> your program finishes execution. This has to be done from the command
> line, not the IDE.
>
> Note: nios2-terminal must be started with the processor in a paused
> state. You can do this by opening two SDK shell windows, downloading
> your program using "nios2-download <elf file>" (which downloads your
> code and leaves the processor paused), then running "nios2-terminal
> --gmon" in the second window, and finally running "nios2-download -g"
> in the first to start execution.
>
> More notes: Your application must return from main() because the
> profiling library's data dump is triggered by reaching atexit().
>
> Also, the above notes assume that you're using the JTAG UART for
> STDIO; for the conventional UART we cannot support GPROF with the
> above flow just yet (this is scheduled for the next release)
>
> 5. Place the "gmon.out" file (generated in step 4) into the same dir
> as your .elf file
> 6. Run nios2-elf-gprof <elf file name> gmon.out > <output file name>
> 7. Examine the output file for results.
>
> The above flow was actually easier than I had expected given my GPROF
> experience with other processors :) However, I am sending an
> enhancement request to our engineering team to make the above flow all
> happen from within the IDE so that the SDK shell business isn't
> necessary.
>
> Also, I'll see to it that this is looked at for a relevant app note
> when the time comes; in addition to GPROF there is a performance
> counter peripheral (which is documented in the Nios II kit) which is
> useful for profiling sections of code -- such an app note will likely
> describe the use of both tools.
>
> Jesse Kempa
> Altera Corp.
> jkempa at altera dot com
Article: 71831Where can I find a good overview of RAM technology as of today (static and dynamic) with some specs of current state-of-the-art memories available ? thanks,Article: 71832
Duane Clark wrote: > Lots of useful information Cheers Duane, appreciate it :-) Simon.Article: 71833
"M.Randelzhofer" <techseller@gmx.de> wrote in message news:<2n4qrgFt0iucU1@uni-berlin.de>... > Hi ng, > > i try to understand the Xilinx Spartan2 pinout data sheet. > Some VCCO's at different banks have the same pin number. > > See: > http://direct.xilinx.com/bvdocs/publications/ds001_4.pdf > > E.g. XC2S100-TQ144 pin16 or pin53 and many others. > > The mistakes are so regularly, that i wonder if i miss anything here... > > Thanks for any eye openings. > > MIKE Mike, They are not mistakes - they just mean that those pins supply power to both banks. On the larger packages there are enough pins to have more pins and give better flexibility. They could do with describing it better but they do mention it in the document http://www.xilinx.com/bvdocs/publications/ds001_2.pdf on page 36. kevinArticle: 71834
vadim wrote: > Where can I find a good overview of > RAM technology as of today (static and dynamic) > with some specs of current state-of-the-art memories available ? > > thanks, Look at Cypress, Micron, IDT, SSI, Renasas etc web sites ? RAM is fragmenting into target niche optimised solutions, which is not always good for design life :( -jgArticle: 71835
> > For 100 Mhz this should be rather trivial. Biggest concern > is how many memory chips you decide to drive. e.g. what will > be your configuration for the 32 bits. Will you use a single > chip (not sure if they make them that wide), two 16 bit chips > or 4 8 bit chips. > > If you go for 4 or more, it will be tough to do the layout > without proper tools and previous knowledge how to do it. > > If you stick to two chips and follow all the regular > recommendations (short, balanced traces, etc) you shouldn't > have any problems. Thanks for your answer. I was indeed planning 2 x 16 bits chips as I don't know any 32 bits ones. I've also seen some reference to a micro app note about terminations, I'll have a look. IIRC, the best way to connect two chips would be Sylvain MunautArticle: 71836
There is a fairly well written article on crossing clock domains that has been published this week. The online version is at: http://www.chipdesignmag.com/display.php?articleId=32&issueId=5 There is a minor problem with the figure numbers in the text (off by one) but it is pretty obvious. Philip =================== Philip Freidin philip.freidin@fpga-faq.com Host for WWW.FPGA-FAQ.COMArticle: 71837
Rudolf Usselmann wrote: > Just wondering if anybody has a uLinux port for the Memec-Insight > Virtex 2 pro 20 board ? Hi Rudi, There's an existing board port for the Insight/Memec 2VP7 board. It would be an excellent starting point to get it going on the board you mention. The microblaze-uclinux mailing list archives would be a good place to start: http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux/Mailing_List/ Cheers, JohnArticle: 71838
"Subroto Datta" <sdatta@altera.com> wrote in message news:<D87Pc.3805$tF3.2388@newssvr32.news.prodigy.com>... > Before downloading the srec, make sure that you have programmed the FPGA > device on the board using the programming file generated by Quartus. > > Hope this helps. > > - Subroto Datta > Altera Corp. Dear Subroto, Do u mean the .sof file? if you meant the .sof file, yes I did download it to the stratix chip before running the .srec! Thank you, johnArticle: 71839
Gerd wrote: > Thomas Reinemann <thomas.reinemann@masch-bau.uni-magdeburg.de> wrote: > >>against the background of partial reconfiguration, I would like to >>determine the difference between two initial configurations (NCDs). Does >>any Xilinx tool support this? > > You are probably looking for > $ bitgen version1.ncd version1.bit > $ bitgen -r version1.bit version2.ncd diff1to2.bit Or if you are really brave, maybe $ xdl -ncd2xdl file1.ncd $ xdl -ncd2xdl file2.ncd $ diff -u file1.xdl file2.xdl Note I've never tried this, it could well produce garbage, depending on how "repeatable" is the output of ncd2xdl. Cheers, JohnArticle: 71840
We have discovered that we have some voltage problems, and probably thats why we have so much problems... Thanks for all your help! // JonasArticle: 71841
Simon wrote: > Sylvain Munaut wrote: > >> >>> >>> For 100 Mhz this should be rather trivial. Biggest concern >>> is how many memory chips you decide to drive. e.g. what will >>> be your configuration for the 32 bits. Will you use a single >>> chip (not sure if they make them that wide), two 16 bit chips >>> or 4 8 bit chips. >>> >>> If you go for 4 or more, it will be tough to do the layout >>> without proper tools and previous knowledge how to do it. >>> >>> If you stick to two chips and follow all the regular >>> recommendations (short, balanced traces, etc) you shouldn't >>> have any problems. >> >> >> >> Thanks for your answer. >> >> I was indeed planning 2 x 16 bits chips as I don't know any 32 bits ones. >> >> I've also seen some reference to a micro app note about terminations, >> I'll have a look. >> >> IIRC, the best way to connect two chips would be > > > (perhaps something missing ?) Yes ;) I meant that I should avoid T in the lines but instead put the chips inline. iow, the tracks go from fpga to first chip then from there to the second one. And avoid going from the fpga then split in two branch, one to chip1 the other to chip2. > I'm thinking of the same sort of thing - it depends on how much RAM you > want, but there's a Micron 1Mx32x4 chip I found (Farnell order #5088793) > that's a TSOP package that might be of interest... That chip would be more that enough in fact I was planning for 8Mbytes. But with 32 bit width, I'll have 16Mb, that's ok. But these are SDRam, not DDR. Well I'll see what I take because DDR seem harder to drive than SDR and I also'd like to spare space in the FPGA, else I won't have any space to put stuff that could use the extra bandwidth. Sylvain MunautArticle: 71842
Peter Alfke <peter@xilinx.com> wrote: > I suggest a synchronous design running at 250 MHz (synchronous counter, > transfer to BlockRAM etc) augmented with a small "prescaling" front-end. > The input line gets clocked into four flip-flops in parallel, each clocked > on a different quadrant of the 250 MHz clock. Using the flip-flop clock > polarity option, this requires only two global lines driven by one DCM. I've been thinking about this again, because the OP's question was physics related, so from their PoV: does using mixed settings in the posedge/negedge option of the FFs introduce a systematic error because the inverter on half of the FFs causes additional delay? Or is there no additional delay (because of how the FFs are built in silicon or some other reason)? regards, -gArticle: 71843
Sylvain Munaut wrote: > >> >> For 100 Mhz this should be rather trivial. Biggest concern >> is how many memory chips you decide to drive. e.g. what will >> be your configuration for the 32 bits. Will you use a single >> chip (not sure if they make them that wide), two 16 bit chips >> or 4 8 bit chips. >> >> If you go for 4 or more, it will be tough to do the layout >> without proper tools and previous knowledge how to do it. >> >> If you stick to two chips and follow all the regular >> recommendations (short, balanced traces, etc) you shouldn't >> have any problems. > > > Thanks for your answer. > > I was indeed planning 2 x 16 bits chips as I don't know any 32 bits ones. > > I've also seen some reference to a micro app note about terminations, > I'll have a look. > > IIRC, the best way to connect two chips would be (perhaps something missing ?) I'm thinking of the same sort of thing - it depends on how much RAM you want, but there's a Micron 1Mx32x4 chip I found (Farnell order #5088793) that's a TSOP package that might be of interest... Simon.Article: 71844
Gerd wrote: > Peter Alfke <peter@xilinx.com> wrote: > >>I suggest a synchronous design running at 250 MHz (synchronous counter, >>transfer to BlockRAM etc) augmented with a small "prescaling" front-end. >>The input line gets clocked into four flip-flops in parallel, each clocked >>on a different quadrant of the 250 MHz clock. Using the flip-flop clock >>polarity option, this requires only two global lines driven by one DCM. > > > I've been thinking about this again, because the OP's question was > physics related, so from their PoV: does using mixed settings in the > posedge/negedge option of the FFs introduce a systematic error because > the inverter on half of the FFs causes additional delay? Or is there > no additional delay (because of how the FFs are built in silicon or > some other reason)? If you simply invert, then you have both the delay miss-match issue, and also any duty cycle variation from 50.00% becomes a time skew. If you use 4 possible phases from the DCM, presumably that removes the duty cycle issue, but you will still have LSB step errors in precise timing. My understanding of the DCM is these are << 1ns, (but they are not zero). -jgArticle: 71845
.Article: 71846
Sylvain Munaut wrote: > Hi > > I'd like to know the price for > X3S200 - PQ208 > X3S200 - FT256 > X3S400 - PQ208 > X3S400 - FT256 > X3S400 - FG456 > > > I have the price I'll pay for the X3S200 - PQ208, so if you give > relative price, ( eg twice the price ) > It doesn't have to be precise, just to know if there is a big change or > not. > > My usual account manager is in vacation and It's just a quick info. > > > Thanks > > Sylvain goto www.nuhorizons.com Laurent Gauch www.amontec.comArticle: 71847
Before downloading type in: nr -t Enter a view times to see if NIOS dumps memory. If nothing happens check you port/cable. Make sure the pins are correctly connected to the Rx and TX via your FPGA. Did you successfully downloaded a program before? Looking at your 1st post it seems that if was actually downloading. If it downloads and then stops/terminates then your program is crashing. Are you compiling standard examples on the dev. board or have you modified your hello_nios.c or running on your own board? One of the main problems I have found was a dry joint/ missing pin on one of the addr/data lines. The program downloads , but the memory is only receiving garbage. After completion the Go command sends it to the execution point where it basically runs random code. To verify this make sure you can do the 'nr -t' thing. If you can then check your target memory e.g. 0x1000000 with "m1000000". If it dumps memory then try and change it e.g. "m1000000:1234". Recheck the memory with "m1000000" to verify that the memory is writeable and that the correct data is stored. Also make sure that the next memory word is not altered (very common). Good luck Victor "John" <johngalil@hotmail.com> wrote in message news:46532e21.0408011924.5693e366@posting.google.com... > "Subroto Datta" <sdatta@altera.com> wrote in message news:<D87Pc.3805$tF3.2388@newssvr32.news.prodigy.com>... > > Before downloading the srec, make sure that you have programmed the FPGA > > device on the board using the programming file generated by Quartus. > > > > Hope this helps. > > > > - Subroto Datta > > Altera Corp. > > Dear Subroto, > > Do u mean the .sof file? > > if you meant the .sof file, yes I did download it to the stratix chip > before running the .srec! > > Thank you, > johnArticle: 71848
I had a question on whether you can use Chipscope pro to load an external SRAM connected to the FPGA. I want to use ChipSCope Pro to load data into an SRAM, is there a way to automate this, any suggestions or comments regarding this? Is this a feasible idea?Article: 71849
Sylvain Munaut wrote: > > Hi > > I'd like to know the price for > X3S200 - PQ208 > X3S200 - FT256 > X3S400 - PQ208 > X3S400 - FT256 > X3S400 - FG456 > > I have the price I'll pay for the X3S200 - PQ208, so if you give relative price, ( eg twice the price ) > It doesn't have to be precise, just to know if there is a big change or not. > > My usual account manager is in vacation and It's just a quick info. FPGA pricing varies widely depending on the amount of business you do with the distiributor. You should be able to get the X3S400-FG456 (what speed?) in the slowest speed grade for under $20 if you buy >1k a year. For lower volumes you can use any of the online distis to get a price estimate. The price will vary a lot on package and speed. So you need the speed number... -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
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