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> The second way is to include the > received CRC in the calculation for the check CRC. If you do this, the > result is the magic number (assuming the checker was initialized with > all 1's). Is this magic number (residual) given by all CRCs? I have experienced that the USB CRC5/CRC16 have residuals which are for all correct calculations the same. But what about other CRCs? RgdsArticle: 71026
Fredrik, I don't want to start a discussion about the chicken and the egg and.. You are right about Stratix, but Lattice has implemented them in a low cost device, and there is the advantage. If you don't want to spend lot's of $$ on features you're not going to use, this ECP-DSP family is a very good alternative, and the performance ... well look for yourselve and try a benchmark. Luc ___ for On 5 Jul 2004 23:11:54 -0700, fredrik_he_lang@hotmail.com (Fredrik) wrote: >Luc Braeckman <luc.braeckman@pandora.be> wrote in message news:<co4ie010ld9h69mmp8i09l86i5l0uhs13a@4ax.com>... >> IMHO, Altera's DSP block is only a multiplier. The MAC block Lattice >> is proposing is much richer: reg, mult, pipeline reg, accu, reg. On >> top of it, the IO cell has more regs than any other comparable >> architecture. >Please have a look at: >http://www.altera.com/products/devices/stratix/features/stx-dsp.html >and then see where Latice got thier ideas from. But you are correct >for the lowcost families Altera (CycloneII) and Xilinx (spartan-3) has >chosen Multipliers rather then DSP blocks. Put if you call Alteras DSP >block a mulitiplyer you have to say the same about Latice since there >are at least on the marketing slides I have seen identical. >YMHO >FredrikArticle: 71027
I'm very happy w/ Verilogger. I've tried a lot of other stuff. ModelSim sucks dongle. Too many menus and submenus and too many things you just have to know about it. And even then it won't give meaningful debug messages at times. And since you're an ASIC engineer, you won't have to do any searching for the free license file, so you can keep those trojans and adwares off your system. It has all the bugs worked out, and has all the features you need, and none of the ones you don't. BB "license_rant_master" <none@nowhere.net> wrote in message news:SGMEc.2916$486.1576@newssvr25.news.prodigy.com... > I am an ASIC engineer who frequently 'takes work home' with me. > Recently, I began using ssh to remotely login to our company's > servers to run some Verilog/VHDL simulations. Launching > sims (from the UNIX command line) is fairly easy and painless, > but any kind of interactive (GUI) operations are pitifully > slow over an WAN/internet connection. In the past, I > haven't needed to do much more than check on running jobs, > restart them, then logout. Now, I find the need to do some > interactive debugging work (waveform viewing, code editing, > etc.) > > So I thought, ok, I'll just install Linux at home and check > out a license remotely from the company. The system > administrator told me "NO!" this is forbidden, due to the license > agreements of just about every EDA-tool vendor. According to the > language/legalese of the license-agreement, a license 'seat' > is tied to a physical location called 'site.' > > There are minor differences among the 'site-radius', but the > end-result is the same ... no executing the tool on hardware outside > of the radius: > > Cadence : 1 mile radius within licensed machine-node > (Sysadmin told me this...didn't double-check myself.) > > Synopsys: 5 mile radius within licensed machine-node > (couldn't find the agreement, but found this on Solvnet.) > > Model/Mentor: 800 meter (0.5mi) radius within licensed machine-node > (Download the user's manual for any Modelsim product.) > > ... > > At this point, I think, well alright, most of these EDA tools > are $100,000 USD and up, so it's reasonable for the vendor to impose > these terms. EDA companies don't want 1 company buying a huge site-wide > (100+) licenses, then randomly 'renting' them out over the internet. > > I mentally used this analogy to convince myself this is ok: > I buy broadband internet service for my household. > It's "unlimited" for my household -- not my neightborhood or someone > driving by on a WiFi laptop. Fair enough... > > Since I can't use the company's tools on *my* home machine, I > started investigating various low-cost Verilog simulators to run > under Windows. (I can't use Icarus because it fails to compile a > lot of our company's Verilog RTL.) > > /RANT ON > > 1) Modelsim/PE "Personal Edition" -- *exact* same license agreement > as their premiere Modelsim/SE. > > "Mentor Graphics > grants to you, subject to payment of appropriate license fees, a > nontransferable, nonexclusive license to use > Software solely: (a) in machine-readable, object-code form; (b) for your > internal business purposes; and (c) on > the computer hardware or at the site for which an applicable license fee > is paid, or as authorized by Mentor > Graphics. A site is restricted to a one-half mile (800 meter) radius." > > *RIDICULOUS* If I were a design-consultant, and my laptop were > my primary compute platform, how am I supposed to comply with a > 'site' radius? By their language, I can't run Modelsim > if I drive more than 0.5mi from my home-residence/business?!? > > 2) ok, so next I move on to Cadence's "Verilog Desktop" > > Wow, same story -- the language of their license agreement brings > me to the same conclusion. Install on laptop -- automatic > non-compliance with their agreement (unless you 'lock down' the > laptop with a 1-mile chain.) Funny how their salesman now use > x86-laptops for nearly *all* customer-site product demos?!? > > 3) I may investigate Verilogger Pro or Simucad, but I figure why bother. > I'll probably just end up getting angrier... > > ... > > /RANT OFF > > Any comments? > What pisses me off the most, is those Cadence/Synopsys/Mentor > "travelling salesman." They come to our company-site, armed with > laptops and LCD-projectors -- then show off how a small x86-laptop > now runs jobs faster than a low-end Sun/IBM RISC workstation. > These EDAs need to be sued for false advertising. At a minimum, > someone needs to challenge their ridiculous license agreement > for products aimed at 'personal' use. > > For now, I've simply told my supervisor 'project schedule slip.' > And I've given up on doing real work at home (now mostly just > catching on documentation and inline RTL-comments.) >Article: 71028
You may try to do some manual floor planning then let the router do the rest... Don't expect the machine to understand everything you know... Kelvin "Heliboy" <heliboy2003@yahoo.com.tw> wrote in message news:a91f428b.0407052243.69385c03@posting.google.com... > Folks, > > I have this question for a long time, just could not get an answer. > > Assume we have a design consisting of several blocks and some of those > blocks are hinhly regular (for example, a datapath). When we do P&R, > does the tool take the advantage of this regularity and place those > datapath element in series? Or it just does P&R globally without > looking at the local regularity? > > The reason I am asking this is that we have a design with blocks which > are regular inside. But after P&R, the LUT utilization increases > dramatically, it seems it uses lots LUT for routing which isn't > expected just by looking at the regularity of the blocks. > > Thanks.Article: 71029
After compiling few FPGAs, I have found this phenomenon. When the design occupies a small fraction of the FPGA, par throws the stuff loosely spread all over the FPGA...like ugly zigzags... When the design occupies 80% of the FPGA, par kompresses my design densely into the bottom 60% of the FPGA, leaving top 40% loosely occupied...then it tell me it failed route...:( Weird! What may I do besides manual floorplanning? KelvinArticle: 71030
Ok, this is how I eventually solved it
bootloop.asm:
loop:
b loop
powerpc-eabi-as bootloop.asm -o boot.o
powerpc-eabi-ld -e 0xFFFFFFFC -Ttext 0xFFFFFFFC -l
<path to EDK-project>/ppc405_0/lib -o bootloop.elf
data2bram -bm <path to EDK-project>/implementation/system.bmm
-bd bootloop.elf -bt <path to EDK-project>/implementation/system.bit
-o b download.bit -p <Virtex target>
And then the JTAG connection worked!
Tnx for the help!
// Jonas
Article: 71031Hi all, I am having some problems when reconfiguring a Virtex FPGA using JBits. BRAMs have a registered output and, after a partial reconfiguration, this register is reset and the behaviour of the design for one cycle is not the expected. The output from the BRAM was supposed to be 0 1 2 3 4 5 6 7 8 9 And I get 0 1 2 3 4 (reconfiguration) 0 6 7 8 9 Do you know how can solve this problem? Of course, I can change the BRAm for a distributed RAM, but this is not a valid solution for my case. Best regards, David de AndrésArticle: 71032
Thanks Phil,
Your English translates brilliantly to Spanish :O)
I have built successfully your 'diffddr' module with Leonardo and Precision,
still a problem though...
The 'diffddr' module double-data-rates a single bit (std_logic) and I need
to DDR an 8 bit bus, I've tried a data_width of 4 but it behaves the same as
with a data_width = 1, follows the code (with data_width = 1 you basically
have an std_logic although for the tools is considered a bus):
-------------Code starts here--------------------
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity idiffddr_g is
generic
(
data_width : integer:=1
);
port (
mainclk_p : in std_logic;
mainclk_n : in std_logic;
rst : in std_logic;
diff_p : in std_logic_vector(data_width-1 downto 0);
diff_n : in std_logic_vector(data_width-1 downto 0);
diffout : out std_logic_vector(data_width-1 downto 0);
diffout_n : out std_logic_vector(data_width-1 downto 0)
);
end entity;
architecture rtl of idiffddr_g is
signal mainclk : std_logic;
signal clk0 : std_logic;
signal clk : std_logic;
signal clk_n : std_logic;
signal diff : std_logic_vector(data_width-1 downto 0);
begin
i_ibufgds: IBUFGDS_LVDS_25
port map (
I => mainclk_p,
IB => mainclk_n,
O => mainclk
);
-- put in a DCM
i_dcm : DCM
port map (
CLKIN => mainclk,
CLKFB => clk,
DSSEN => '0',
PSINCDEC => '0',
PSEN => '0',
PSCLK => '0',
RST => rst,
CLK0 => clk0,
LOCKED => open
);
-- and a bufg
i_bufg: bufg port map (
i => clk0,
o => clk
);
clk_n <= not clk;
-- Now the test code
g_ibufds: for i in diff'range generate
diff0: IBUFDS_LVDS_25 port map (
I => diff_p(i),
IB => diff_n(i),
O => diff(i)
);
end generate;
process (clk) begin
if rising_edge(clk) then
diffout <= diff;
end if;
if falling_edge(clk) then
diffout_n <= diff;
end if;
end process;
end;
-------------Code ends here--------------------
As soon as I add the generic width (even if is not a generic), nahh, it
doesn't work!
The synthesizer output is 'the same' for module 'idiffddr' and 'idiffddr_g'
but ISE seems to push only the 'rising_edge' FF and then the falling edge
into the output IOB...is not using the DDR.
It's like if the mapper considers the IOB as a bit-wide structure and when
it sees a bus, even if the bus is 1-bit wide :) it breaks.
Have you tried your module with x-bit wide input data...?
Thanks in advance,
I.U. Hernandez
"Phil Hays" <Spampostmaster@comcast.net> wrote in message
news:b58je01vq60g3a8aql4h8ck7il2ta83eoj@4ax.com...
> "I.U. Hernandez" <ulises@aliathon.com> wrote:
>
> >Hi guys,
> >
> >It's been ages since I haven't posted anything here...
> >
> >Well, I have a problem trying to build a design:
> >
> >- 311 MHz LVDS clock to IBUFGDS
> >- to DCM
> >- generates CLK0 to BUFG (rxclk0_311a_ig)
> >- generates CLK180 to BUFG (rxclk180_311a_ig)
> >
> >easy so far...
> >
> >Data comes in as an LVDS differential nibble (or nybble :O) apologies
from
> >my Spanish-English), I am supposed to Double Data Rate the data...
> >
> >I have tried instantiating the whole thing:
>
> I hope my English translates well to Spanish.
>
> Did you try just writing behavioral code and seeing what it did?
>
> XST at least (I don't have Synplify or Precision at home) handles the
> following code correctly. The final output from PAR is an input
> buffer with DDR flip flops.
>
>
> --
> Phil Hays
> Phil-hays at posting domain should work for email
> ______________________ Cut Here ______________________________
>
> library ieee;
> use ieee.numeric_std.all;
> use ieee.std_logic_1164.all;
> library unisim;
> use unisim.vcomponents.all;
> entity diffddr is
> port (
> mainclk : in std_logic;
> rst : in std_logic;
> diffa : in std_logic;
> diffb : in std_logic;
> diffout : out std_logic;
> diffout_n : out std_logic
> );
> end entity;
> --
> architecture insts of diffddr is
> signal clkin : std_logic;
> signal clkdv : std_logic;
> signal clk2x : std_logic;
> signal clk0 : std_logic;
> signal clk90 : std_logic;
> signal clk180 : std_logic;
> signal clk270 : std_logic;
> signal clkfx : std_logic;
> signal locked : std_logic;
> signal clk : std_logic;
> signal clk_n : std_logic;
> signal diff : std_logic;
> begin
> -- put in a DCM
> dcm_inst: dcm port map (
> clkin => clkin,
> clkfb => clk,
> clk0 => clk0,
> clkdv => clkdv,
> clk2x => clk2x,
> clkfx => clkfx,
> clk90 => clk90,
> clk180 => clk180,
> clk270 => clk270,
> rst => rst,
> locked => locked
> );
> --And a clock pad buffer
> clkbuf: IBUF port map (
> o => clkin,
> i => mainclk
> );
> -- and a bufg
> clktree: bufg port map (
> i => clk0,
> o => clk
> );
> clk_n <= not clk;
> -- Now the test code
> diff0: IBUFDS_LVDS_25 port map (
> I => diffa,
> IB => diffb,
> O => diff
> );
> process (clk) begin
> if rising_edge(clk) then
> diffout <= diff;
> end if;
> end process;
> process(clk) begin
> if falling_edge(clk) then
> diffout_n <= diff;
> end if;
> end process;
> end;
>
Article: 71033Dear Sirs, We are manufacturer of universal device programmers. We are looking for distributor in different countries. http://www.rk-system.com.pl/uprog2.shtml#ogolnie Currently, we have the following models: 1) UprogHS 84 - Dual package with boundled 48DIP and universal 84PLCC or SOIC/TSOP44 support. UprogHS 84 high speed programmer can be also used as a eight socket gang programmer. This model has some additional options: tester, emulator, logic analyzer. Device list about 7700 chips. More details: http://www.rk-system.com.pl/uprog2.shtml#uproghs84 2) UprogHS 48 portable - High speed USB 48DIP portable programmer with additional options: tester, emulator, logic analyzer. More details: http://www.rk-system.com.pl/uprog2.shtml#uproghs48p 3) UprogHS 48 - High speed 48DIP programmer with additional options: tester, emulator, logic analyzer. Device list about 7500 chips. More details: http://www.rk-system.com.pl/uprog2.shtml#uproghs48 4) Uprog 48 - Universal programmer with 48DIP socket supporting about 7000 chips. More details: http://www.rk-system.com.pl/uprog2.shtml#uprog48 5) Uprog40 - Universal programmer with 40DIP socket supporting about 6300 chips. More details: http://www.rk-system.com.pl/uprog2.shtml#uprog40 All offered models are good quality and quite easy to sell. The device lists of all programmers are strongly and quickly developed and all software updates are free of charge! We can offer very good reselling conditions ! RK-SYSTEM ul. Che³moñskiego 30 05-825 Grodzisk Mazowiecki POLAND tel. +48 22 724 30 39 tel. +48 22 755 69 83 fax +48 22 724 30 37 fax +48 22 755 58 78 email:rk-system@rk-system.com.pl http://www.rk-system.com.plArticle: 71034
You can try using the PACE to define area constraints for your design block(s), that way PAR will have a predefined location to work with, --- jakab "Kelvin" <student@nowhere.com> wrote in message news:40ea7188@news.starhub.net.sg... > After compiling few FPGAs, I have found this phenomenon. > When the design occupies a small fraction of the FPGA, par throws the stuff > loosely spread > all over the FPGA...like ugly zigzags... > When the design occupies 80% of the FPGA, par kompresses my design densely > into the bottom > 60% of the FPGA, leaving top 40% loosely occupied...then it tell me it > failed route...:( > Weird! > > What may I do besides manual floorplanning? > > Kelvin > > > >Article: 71035
Yeah, when I did partial reconfigurable design, I apply area_group on two sides of my FPGA. However, the phenomenon remain for each of the partial designs. Thanks for your reply. Kelvin "jakab tanko" <jtanko@ics-ltd.com> wrote in message news:cce64d$cbf$1@news.storm.ca... > You can try using the PACE to define area constraints for your design > block(s), that way > PAR will have a predefined location to work with, > --- > jakab > "Kelvin" <student@nowhere.com> wrote in message > news:40ea7188@news.starhub.net.sg... > > After compiling few FPGAs, I have found this phenomenon. > > When the design occupies a small fraction of the FPGA, par throws the > stuff > > loosely spread > > all over the FPGA...like ugly zigzags... > > When the design occupies 80% of the FPGA, par kompresses my design densely > > into the bottom > > 60% of the FPGA, leaving top 40% loosely occupied...then it tell me it > > failed route...:( > > Weird! > > > > What may I do besides manual floorplanning? > > > > Kelvin > > > > > > > > > >Article: 71036
You may want to look at Emulation Technologies' website. They have a line of prototyping adapters that convert most SMT packages including 54-pin TSOP (SDRAM x4 x8 and x16 available in this package) to through hole on 0.1" centres. http://www.emulation.com/catalog/off-the-shelf_solutions/prototyping_adapters/tsop/ "John Adair" <newsreply@loseinspace.co.uk> wrote in message news:<LowFc.42$5_.8@newsr2.u-net.net>... > It is possible that our University Access Program(UAP) may be able to help > depending on your timescales. We have only just announced this for UK and > Europe and North America is a few months away it's official launch and > support. But if you are interested have a look here > http://www.enterpoint.co.uk/news.html . > > John Adair > Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development > Board. > http://www.enterpoint.co.uk > > This message is the personal opinion of the sender and not that necessarily > that of Enterpoint Ltd.. Readers should make their own evaluation of the > facts. No responsibility for error or inaccuracy is accepted. > > "Edmond Cote" <edmond_cote@yahoo.ca> wrote in message > news:40e60e46$1_2@aeinews.... > > > > Hi, > > > > I currently have access to a large number of FPGA prototyping boards > through > > my University. Unfortunately these boards are quite simple, wire-wrapping > > would need to be used to prototype memory or other peripherals. While > > ordinarily this wouldn't pose too much of a problem for me, I require a > > rather large amount of RAM (of the order of ~4Mbytes) for this project I > > will be working on. > > > > Looking through electronic catalogues, I quickly realized that for one it > is > > nearly impossible to find DRAM IC's in DIP packages (and that even if I > > could find them I would need a hella-lot of those 64Kb chips). The DRAM I > > could find is obviously only availible in surface mount type packaging. > > Ideally I'd love to get a custom PCB developped and get someone who could > > solder to work, but in my case I don't think it is an option as I don't > have > > the time/money/experience/talent? to do so. > > > > So basically does anyone have any suggestions?, do any vendors have a > SDRAM > > protoboard (something like a couple MB of SDRAM on a board with > prototyping > > headers)? how about using DIMMs instead of individual ICs?. > > > > As a last resort, I might need to purchase an FPGA board from Memec, Xess, > > but personally I'd much rather work with a 1M+ Virtex devices availible > from > > school then to have a fund such a board myself, which would be of much > > lesser quality. Does anyone have any other vendors to suggest, my > > requirements are having at least 2Mb of RAM and under 300$, and well at > > least 100k gates. > > > > Thanks in advance for your help and suggestions! > > > > Ed. > > > > > >Article: 71037
ALuPin@web.de (ALuPin) wrote in message news:<b8a9a7b0.0407052258.6f1be41f@posting.google.com>... > > The second way is to include the > > received CRC in the calculation for the check CRC. If you do this, the > > result is the magic number (assuming the checker was initialized with > > all 1's). > > Is this magic number (residual) given by all CRCs? > I have experienced that the USB CRC5/CRC16 have residuals which are > for all correct calculations the same. But what about other CRCs? Yes, all CRC's produce a residual - it is a function of the following items: * The CRC polynomial being used (CRC-16 vs. CRC-CCITT vs. CRC-32, etc) * The initial value (sometimes all 1's, but not always) * Bit and byte ordering (application dependant) * Bit inversion (application dependant: sometimes XOR with all 1's) Have fun, MarcArticle: 71038
Hi, there: I have found that Xilinx synthesis directive "mult_style =lut" can only be applied to either a reg/wire directly under a module, or applied to the module itself. A complicated design or module may contain multipliers wrapped in a task or function, in which situation I may or may not define a wire/reg. I have discovered that mult_style didn't work in either a function or a task. The use of mult_style on the module itself applies to ALL the multiplers in the module irregardless of whether a multiplier is wrapped in a function/ task or not. so, how do I constrain "mult_style =lut" on my multiplier in a function/task statement while leave my bare multipliers to BLOCK alone? Thanks. KelvinArticle: 71039
Hi Jimmy, We've run into similar difficulties. The Xilinx tools will assume, by default, that anything connected to a clock input is connected to a global clock input. The workaround is to explicitly connect the input pin to an IBUF primitive, and connect the IBUF output to everything that uses the input signal. For more information, get the Xilinx Libraries Guide. Here's a link for the PDF version for V6.1 ISE. http://toolbox.xilinx.com/docsan/xilinx6/books/docs/lib/lib.pdf Here's a link for the online HTML version for V6.1 ISE http://toolbox.xilinx.com/docsan/xilinx6/books/data/docs/lib/lib0001_1.html Other versions are available, but you'll need to search for what you require. Best regards, Dwayne Surdu-MillerArticle: 71040
P.S. I dunno off-hand why BufferReady is deigned to be a global clock. One way to find out would be to synthesize the module then view the RTL schematic of the synthesized design and search for anything that connects BufferReady to a clock input. If XST found implications that BufferReady is a clock, the RTL schematic should help you find where the implications took place. Dwayne Surdu-MillerArticle: 71041
P.P.S. It looks like BufferReady should be an output, not an input (my apologies). It shouldn't be on a global clock pin at all, as they are input-only! Something weird is happening.Article: 71042
rrr@ieee.org (Rajeev) wrote in message > So here's my questions... > > (1) Is it a bad idea to use 'X' in a simulation ? > > (2) Is there something I'm missing that explains this behavior ? > > (3) I tried other logic functions and all possible 2-input > combinations with > 9-valued inputs. The mux is the only thing that I find puzzling. Is > there > a preferred way to write the mux ? Hi Rajeev, The Quartus simulator is not a behavioral simulator. It simulates a synthesized circuit which is functionally equivalent to the users specification. The synthesizer is free to assign an 'X' signal to either 1 or 0 to reduce the logic. Hope this helps. - SubrotoArticle: 71043
Hi guys, I am mostly a newb at fpga design, although I did a teeny bit of work on a Spartan II design a few years ago in verilog. Anyway, I would like to learn vhdl, and get a development board because I like to supplement endless reading of textbooks with some hands-on experiments. I will probably purchase Ashenden's book soon. So, I have found two starter boards which look interesting...the $99 Spartan 3 starter kit from Xilinx, and the $164 Spartan 3 starter kit from Nu Horizons. Before I saw the Nu Horizons board, I was ready to get the Xilinx starter kit. Now, I am torn between the two. I know nothing about the Microblaze core...does the Nu Horizons board come with all the IP you need to do endless experiments with this core, or do you need to pay the $495 edk to Xilinx to get usefull IP? If you get everything you need with the $164 Nu Horizons board, then I am sold on that, because I have several projects in mind that would greatly benefit from the larger Sparten 3 part, the 64MB of sdram and the 32MB of flash. The D/A is very nice too...I have an application for that as well. Opinions? Thanks! HankArticle: 71044
I agree with Luc. The DSP blocks are just great for a low cost FPGA. Stratix have the same or similar but you need to pay for them. Another point that Luc mentioned is the DDR capabilities. There is a dedicated hardware (DLL and input registers) to facilitate the DDR interface without needing to waste LUT on it. I like that as well. Clocking scheme looks good. Great range of freq from analog PLLs. Normal 4 quadrants. It seems the market for the low cost FPGA is getting hot with one good new member. .. paul Luc Braeckman <luc.braeckman@pandora.be> wrote in message news:<jflke0156m53oldb1laiu7cjuf2ljujgtf@4ax.com>... > Fredrik, > > I don't want to start a discussion about the chicken and the egg and.. > You are right about Stratix, but Lattice has implemented them in a low > cost device, and there is the advantage. If you don't want to spend > lot's of $$ on features you're not going to use, this ECP-DSP family > is a very good alternative, and the performance ... well look for > yourselve and try a benchmark. > Luc > ___ > for On 5 Jul 2004 23:11:54 -0700, fredrik_he_lang@hotmail.com > (Fredrik) wrote: > > >Luc Braeckman <luc.braeckman@pandora.be> wrote in message news:<co4ie010ld9h69mmp8i09l86i5l0uhs13a@4ax.com>... > >> IMHO, Altera's DSP block is only a multiplier. The MAC block Lattice > >> is proposing is much richer: reg, mult, pipeline reg, accu, reg. On > >> top of it, the IO cell has more regs than any other comparable > >> architecture. > >Please have a look at: > >http://www.altera.com/products/devices/stratix/features/stx-dsp.html > >and then see where Latice got thier ideas from. But you are correct > >for the lowcost families Altera (CycloneII) and Xilinx (spartan-3) has > >chosen Multipliers rather then DSP blocks. Put if you call Alteras DSP > >block a mulitiplyer you have to say the same about Latice since there > >are at least on the marketing slides I have seen identical. > >YMHO > >FredrikArticle: 71045
Makesh Soundarajan <makesh_s_e@hotmail.com> wrote: Dear Makesh, > Hi > > Has anybody used the D/A converter (Linear Tech's LTC1654) ? I am > having few issues . I tried to initialize using both the 24 and 32 bit > format but the output of D/A remains at 0. > I have had some small problems with the LTC1654 as well. Have you also started with the DAC A output? There is a small problem with the output gain configuration of the LTC1654. There is one pin per DAC which should be either connected to GND or to the DAC output - if I remember correctly. On the board the DAC A config pin is hardwired to VCC and the DAC B config pin is connected to VCC by a resistor but can be shorted to GND by a 2-pin jumper close to the DAC. If you close the jumper at least DAC B should work. To make DAC A running you have to lift the corresponding pin of the LTC1654 and connect it to GND with a short wire. There is one capacitor connected to GND close to that pin. This is a suitable point to get the GND signal from. > Any help will be greatly appreciated > I hope it helps. I guess you have the datasheet of the LTC1654, please look for the gain setting for detailed infos. > > Thanks > Makesh I like the compact board, also because of its on board peripherals. Best regards, ChristophArticle: 71046
"I. Ulises Hernandez" <delete@e-vhdl.com> wrote:
>Your English translates brilliantly to Spanish :O)
Good, as my Spanish is beyond awful ;-)
>I have built successfully your 'diffddr' module with Leonardo and Precision,
>still a problem though...
Please try the following code. I increased the generic width to 8, as
that is what you are targeting. I added another layer of FFs to make
sure there was no ambiguity as to where to force the FF into, and
verified the map was forcing FFs into IOBs (map report file will have
"-pr b" on the command line). I also split the clocked process into
rising and falling edge sections as I have seen problems with this in
the past. XST handles the following code correctly.
--
Phil Hays
Phil-hays at posting domain should work for email
---------------------------- Cut Here -----------------------------
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity idiffddr_g is
generic
(
data_width : integer:=8
);
port (
mainclk_p : in std_logic;
mainclk_n : in std_logic;
rst : in std_logic;
diff_p : in std_logic_vector(data_width-1 downto 0);
diff_n : in std_logic_vector(data_width-1 downto 0);
diffout : out std_logic_vector(data_width-1 downto 0);
diffout_n : out std_logic_vector(data_width-1 downto 0)
);
end entity;
architecture rtl of idiffddr_g is
signal mainclk : std_logic;
signal clk0 : std_logic;
signal clk : std_logic;
signal clk_n : std_logic;
signal diff : std_logic_vector(data_width-1 downto 0);
signal difft : std_logic_vector(data_width-1 downto 0);
signal difft_n : std_logic_vector(data_width-1 downto 0);
begin
i_ibufgds: IBUFGDS_LVDS_25
port map (
I => mainclk_p,
IB => mainclk_n,
O => mainclk
);
-- put in a DCM
i_dcm : DCM
port map (
CLKIN => mainclk,
CLKFB => clk,
DSSEN => '0',
PSINCDEC => '0',
PSEN => '0',
PSCLK => '0',
RST => rst,
CLK0 => clk0,
LOCKED => open
);
-- and a bufg
i_bufg: bufg port map (
i => clk0,
o => clk
);
clk_n <= not clk;
-- Now the test code
g_ibufds: for i in diff'range generate
diff0: IBUFDS_LVDS_25 port map (
I => diff_p(i),
IB => diff_n(i),
O => diff(i)
);
end generate;
process (clk) begin
if rising_edge(clk) then
difft <= diff;
diffout <= difft;
end if;
end process;
-- Falling edge clock is in a seperate process to avoid
-- problems with some synthesis tools.
process (clk) begin
if falling_edge(clk) then
difft_n <= diff;
diffout_n <= difft_n;
end if;
end process;
end;
Article: 71047amy-rehner@usa.com (Amy) wrote in message news:<5ca5153c.0406241143.44a21b5b@posting.google.com>... > Hi all, > I am looking for some fax software packages (V.34, V.17, V.29, > V.27ter, V.21 Channel 2, T.30) in C5000 platform. Any suggestion? > Thanks > > Amy Hi, I used to work for this Gao Research Inc. I think their color fax packages are perfect for you. you can visit to their website at http://www.gaoresearch.com/ for more infomation.Article: 71048
Have any of you tried Lattice's software for their new -EC parts? How close
is it to Xilinx (they share a common heritage)? I'm trying to get a feel
for its quality and stability.
Things should be getting interesting when their 90nm -SC parts come out (vs.
Stratix-II and Virtex-4), especially with their cool DDR I/O interface.
Perhaps Lattice will make a come-back?
--
/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 71049Actually 18 bits makes sense for parity, which is why the block RAMs are 18 or 36 bits wide rather than 16 or 32. The multiplier would normally only work on data, not parity. My guess is that Xilinx picked 18 bits to use the common routing resources available at the block RAM site (each multiplier shares routing with an adjacent 18 Kbit block RAM). In an FPGA data width is arbitrary unless you're using an embedded processor. 18 bits is as reasonable a size as any other, and 2 bits better than 16 (you don't have to use all the bits). Routing resource sharing shows up when you try to use the block RAM at 36-bit width and realize the multiplier is no longer usable. General Schvantzkoph <schvantzkoph@yahoo.com> wrote in message news:<pan.2004.07.05.12.53.56.811963@yahoo.com>... > On Mon, 05 Jul 2004 04:57:43 -0700, debo wrote: > > > Most of the commercial DSP processors today have 16X16 or 32X32 bit > > signed multilpiers. Why do Altera and Xilinx provide 18X18 > > multilpiers? > > > > Also, what is the use of a single parity bit with each byte? As far as > > i can understand it will only allow for error detection for a single > > bit flip (which is the simplest form of error detection). Are there > > any other uses of this parity bit? > > Single bit error detection is sufficient for most applications. If you are > using 64 bit data paths then 1 bit per byte adds up to eight extra bits > which is sufficient for a single bit correction, double bit detection ECC > code.
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