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Did you use the correct reset value for the CRC (usaly 0xFFFFFFFF)? I thing that the checksum that is included in the Ethernet packet is the complement of thr CRC result, i.e. checksum = not CRC. /Patrik st wrote: > moti@terasync.net (Moti Cohen) wrote in message news:<c04bfe33.0407040651.2199a09f@posting.google.com>... > >>Hy all, >>I'm currently implementing a receiver (vhdl) part of the ethernet mac >>which is responsible for the MII interafce. I'm need an crc32 >>calculator (RTL) to check the FCS field. I've tried using the easics >>crctoll in order to create the mechanism (for a 4 bit data input) but >>it does not seems to work. does anyone have a working (rtl) vhdl >>implementation for this block? or at least a detailed expalnation on >>how to create it..? >>Thanks in advance, Moti. > > > Hi, > > I've developped, for my personnal needs, a crc software. I've took for > inputs : g(x)=x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 > + x5 + x4 + x2 + x + 1 > and 4 bits bus. > The results are : > -- x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 > + x^5 + x^4 + x^2 + x^1 + 1 > function fcrc(DIN : std_logic_vector(3 downto 0); CRC : > std_logic_vector(31 downto 0)) > return std_logic_vector is > variable RESUL : std_logic_vector(31 downto 0); > begin > RESUL( 0):=CRC(28) xor DIN(0); > RESUL( 1):=CRC(28) xor CRC(29) xor DIN(0) xor DIN(1); > RESUL( 2):=CRC(28) xor CRC(29) xor CRC(30) xor DIN(0) xor DIN(1) > xor DIN(2); > RESUL( 3):=CRC(29) xor CRC(30) xor CRC(31) xor DIN(1) xor DIN(2) > xor DIN(3); > RESUL( 4):=CRC(0) xor CRC(28) xor CRC(30) xor CRC(31) xor DIN(0) > xor DIN(2) xor DIN(3); > RESUL( 5):=CRC(1) xor CRC(28) xor CRC(29) xor CRC(31) xor DIN(0) > xor DIN(1) xor DIN(3); > RESUL( 6):=CRC(2) xor CRC(29) xor CRC(30) xor DIN(1) xor DIN(2); > RESUL( 7):=CRC(3) xor CRC(28) xor CRC(30) xor CRC(31) xor DIN(0) > xor DIN(2) xor DIN(3); > RESUL( 8):=CRC(4) xor CRC(28) xor CRC(29) xor CRC(31) xor DIN(0) > xor DIN(1) xor DIN(3); > RESUL( 9):=CRC(5) xor CRC(29) xor CRC(30) xor DIN(1) xor DIN(2); > RESUL(10):=CRC(6) xor CRC(28) xor CRC(30) xor CRC(31) xor DIN(0) > xor DIN(2) xor DIN(3); > RESUL(11):=CRC(7) xor CRC(28) xor CRC(29) xor CRC(31) xor DIN(0) > xor DIN(1) xor DIN(3); > RESUL(12):=CRC(8) xor CRC(28) xor CRC(29) xor CRC(30) xor DIN(0) > xor DIN(1) xor DIN(2); > RESUL(13):=CRC(9) xor CRC(29) xor CRC(30) xor CRC(31) xor DIN(1) > xor DIN(2) xor DIN(3); > RESUL(14):=CRC(10) xor CRC(30) xor CRC(31) xor DIN(2) xor DIN(3); > RESUL(15):=CRC(11) xor CRC(31) xor DIN(3); > RESUL(16):=CRC(12) xor CRC(28) xor DIN(0); > RESUL(17):=CRC(13) xor CRC(29) xor DIN(1); > RESUL(18):=CRC(14) xor CRC(30) xor DIN(2); > RESUL(19):=CRC(15) xor CRC(31) xor DIN(3); > RESUL(20):=CRC(16); > RESUL(21):=CRC(17); > RESUL(22):=CRC(18) xor CRC(28) xor DIN(0); > RESUL(23):=CRC(19) xor CRC(28) xor CRC(29) xor DIN(0) xor DIN(1); > RESUL(24):=CRC(20) xor CRC(29) xor CRC(30) xor DIN(1) xor DIN(2); > RESUL(25):=CRC(21) xor CRC(30) xor CRC(31) xor DIN(2) xor DIN(3); > RESUL(26):=CRC(22) xor CRC(28) xor CRC(31) xor DIN(0) xor DIN(3); > RESUL(27):=CRC(23) xor CRC(29) xor DIN(1); > RESUL(28):=CRC(24) xor CRC(30) xor DIN(2); > RESUL(29):=CRC(25) xor CRC(31) xor DIN(3); > RESUL(30):=CRC(26); > RESUL(31):=CRC(27); > return RESUL; > end fcrc; > Tell me (in the news group) if it's ok. -- ------ Patrik ErikssonArticle: 71001
Most of the commercial DSP processors today have 16X16 or 32X32 bit signed multilpiers. Why do Altera and Xilinx provide 18X18 multilpiers? Also, what is the use of a single parity bit with each byte? As far as i can understand it will only allow for error detection for a single bit flip (which is the simplest form of error detection). Are there any other uses of this parity bit?Article: 71002
On Mon, 05 Jul 2004 04:57:43 -0700, debo wrote: > Most of the commercial DSP processors today have 16X16 or 32X32 bit > signed multilpiers. Why do Altera and Xilinx provide 18X18 > multilpiers? > > Also, what is the use of a single parity bit with each byte? As far as > i can understand it will only allow for error detection for a single > bit flip (which is the simplest form of error detection). Are there > any other uses of this parity bit? Single bit error detection is sufficient for most applications. If you are using 64 bit data paths then 1 bit per byte adds up to eight extra bits which is sufficient for a single bit correction, double bit detection ECC code.Article: 71003
I think NIOS and SOPC builder are great products. However, there are a
couple things I find annoying regarding the generated Verilog code
when it comes to compatibility with third party synthesis tools and
simulators. They are:
* Support of specific synthesis tool only. The generated code have
statements like:
//exemplar translate_off
Rather than:
//synthesis translate_off
* Mix of design and testbench code in the same file
The generated top level NIOS file contains the following structure:
module nios32 ...etc...
endmodule
//exemplar translate_off
`include "/eda/sim_lib/220model.v"
`include "cpu.v"
...
module test_bench ;
...
endmodule
//exemplar translate_on
I would prefer if the testbench was generated in a separate file
(testbench.v or similar). This would ease simulation of the NIOS in
my own environment. In this case I would simply not include
testbench.v.
Sanity checks and assertions included in //synthesis
translate_off/on pairs are of course ok.
* Use of `ifdef MODEL_TECH
Not a big issue I as I can do a +define+MODEL_TECH (even though it
took me a while to figure this out) in my favorite simulator.
However, I think more descriptive preprocessor variable names would
be better, e.g.
//synthesis translate_off
`ifdef NIOS_SIM_GEN_OPCODE
assign opcode = ((((~instruction[15] && ~instruction[14] ...
//synthesis translate_on
In some cases the simulation wont work if you don't define
MODEL_TECH, e.g. like in:
`ifdef MODEL_TECH
//////////////// SIMULATION-ONLY CONTENTS
altsyncram the_altsyncram
(
...
I don't know the reason behind this structure since the synthesis
tool wont touch this code. The `ifdef MODEL_TECH could have been
left out.
* Use of include. The generated code will look like:
`include "/eda/sim_lib/altera_mf.v"
`include "/eda/sim_lib/220model.v"
`include "cpu.v"
The first two will cause problems for third party tools since they
have no clue where to look. Further the path is absolute so I can't
fix this in DC-FPGA by setting the search_path variable.
There is no need for include statements in this case. The filenames
can be included on the command line or file input list in a
synthesis tool or simulator.
It appears that my synthesis tool is processing the include
statements even inside // synthesis translate_off (I guess the could
be a synthesis translate_on in the include file), which results in
an error when it hits the absolute path.
Are these issues present in NIOS-II?
Petter
--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?
Article: 71004hello! i want to compile a design for a altera acex or cyclon and i want to put additionally a table into it (f.e. a .mif file) without compiling it completely when changing the mif file (each delivered device has its own mif file or sth similar) what is the best way. does quartus have a possibility while burning to integrate the mif file into the pof file while burning? or should i use a enhanced configuration device and i must write a complete engine to read and write eth out of this device? or is it the best way to put simply an flahs onto the pcb? best regards, roland -- reply me to madcapATsbox.tugrazDOTatArticle: 71005
I have a similar application. We perform PCI-X DMA with 4Kbyte bursts
from our add-in
card into the host's memory (Menory Write = command x"07"). This works
well in a dual
Xeon system with Intel E7501 chipset @ 133 MHz, we have a datarate of
about 420 MB/s. We
have been working for a while before the handshake between driver and
hardware worked
properly. We do it like following:
--> add-in card performs an interrupt and sets an interrupt bit
--> the device driver writes a valid address for the DMA into a BAR
register
--> the device driver clears the interrupt bit!
--> the user application in the FPGA starts the DMA and attempts to
write the desired
burst length to this address. The user
application keeps track of the address. In case of a DMA abort
it makes a new
transaction request till the 4Kbyte are
finished.
--> add-in card performs an interrupt
and so on ....
Within 4Kbyte bursts we have about 10 aborts, depending on bus traffic
and system. I
have also measured aborts right from the start of the DMA without any
data being written
to the host's memory! If you don't consider aborts, this can also be
your problem!
Matthias
Mark Schellhorn schrieb:
> If anyone can offer help with this (or a pointer to a more suitable
forum) it
> would be greatly appreciated. I am posting here because I know there
is some
> some folks with expertise who frequent this group (and we're using a
Xilinx core
> :)).
>
> We are attempting to perform 64B burst PCI-X DMA write transfers from
our add-in
> card into host memory on a dual Xeon system.
>
> Our linux device driver (kernel 2.24.x/2.26.x) is notified via an
interrupt &
> single dword "doorbell" write that the larger 64B entry is available
for processing.
>
> The order of operation on the PCI-X bus is as follows:
>
> 64B data write --> 4B doorbell write --> interrupt.
>
> Upon receiving the interrupt, the device driver polls the location in
memory
> where the 4B doorbell write is expected to show up. Once he sees the
doorbell
> location written, he reads the 64B data location. PCI ordering should
guarantee
> that the 64B data location is written to system memory before the 4B
doorbell
> write is.
>
> The above writes are performed as Memory Write Block transactions (we
have also
> tried Memory Write transactions), the No Snoop bit is cleared, and the
Relaxed
> Ordering bit is cleared.
>
> We consistently encounter a situation where the device driver
correctly receives
> the interrupt & single dword doorbell write, but the 64B write fails
to appear
> in memory. Instead, the device driver reads a stale 64B block of data
(data from
> the last successful DMA write).
>
> As a debug measure, we had the FPGA on our add-in card perform a
readback
> (Memory Read Block) of the 64B entry immediately after writing it. We
obeserved
> that the data read back was stale and matched the stale data that the
device
> driver saw. Eg:
>
> 1) Location 0xABCDEF00 is known to contain stale 64B data
0xAAAA....AAAA.
> 1) FPGA does Memory Write Block 64B 0xBBBB....BBBB at address
0xABCDEF00.
> 2) FPGA does Memory Read Block 64B at address 0xABCDEF00 (Split
esponse).
> 3) Split Completion is returned by bridge with data
0xAAAA....AAAA.
>
> This appears to be a violation of PCI ordering rules. Again, the No
Snoop and
> Relaxed Order bits are cleared for all of these transactions.
>
> The device driver *never* writes to the 64B location, so there should
be no
> possibility of a collision occurring where he writes/flushes stale
data that
> overwrites the incoming DMA write.
>
> This tells me that the location is NOT getting written because,
according to PCI
> ordering rules, the FPGA read *must* push the Memory Write Block into
system
> memory before reading back the location.
>
> We observe this behaviour in dual Xeon systems with both the Intel
E7501 chipset
> and the Broadcom Serverworks GC-LE chipset.
>
> We observe this in SMP and single processor configurations.
>
> When bus traffic is light at 133MHz, or whenever the bus is running at
66MHz, we
> do *not* observe this problem. We occasionally observe the problem
when the bus
> is running at 100MHz with heavy traffic. This suggests that we are
hitting a
> narrow timing window at higher bus speeds.
>
> We are suspicious that we might be encountering a cache errata in the
Xeon, and
> are wondering if anyone can confirm this and possibly provide a
workaround?
>
> We've been banging our heads on this for a couple of weeks now.
>
> Mark
--
Matthias Müller
Fraunhofer Institut Integrierte Schaltungen IIS
-Bildsensorik-
Am Wolfsmantel 33
D-91058 Erlangen
Tel: +49 (0)9131-776-554
Fax: +49 (0)9131-776-598
mailto:mur@iis.fhg.de http://www.iis.fhg.de
Article: 71006On Sat, 3 Jul 2004, tns1 wrote: > In both cases it sounds like you are missing carriage returns or line > feeds. The staircase pattern is an classic example. You may need to set > minicom to append carriage returns to incoming line feeds, to echo typed > characters, or to send carriage returns with line feeds. Once you are > sure both CR & LF is part of every line, it should be clear when you > need them and when you don't. > > > Nigel Gunton CEMS STAFF wrote: > > Hi, > > I'm having problems getting nios-run -t to function correctly. The > > development platform is Quartus 3 sp2, SOPC 3.02 on Linux, Apex board. > > > > I'm using the standard_32 example provided with the Nios kit 3.2. This > > builds (SDK and the hardware) without apparent problem, synthesises and > > can be downloaded via the jtag interface. > > > > executing nios-run -t results in the peripherals test menu being displayed > > but no response to keyboard input occurs, except ^C which occasionally > > requires repeating to get the program to quit. Running strace shows > > repeated calls to query the keyboard via select(), but only the ^c is > > picked up on. > > > > Running minicom permits access to germs: and to the peripheral tests, > > albeit with a 'staircase' problem on the output from the peripherals test, > > but at least I have 2 way communication which implies that the problem > > lies with nios-run. > > > > Running nios-run -p with a download file results in it waiting > > indefinitely for the board to respond, both with the factory default and > > the jtag downloaded file. > > > > Has anybody had similar problems? A search through the archives didn't > > find anything, hence the post. > > > > AFAIUS, I need to use nios-run to reprogram the onboard flash or is there > > an alternative. > > thanks but ... I'm not too bothered by the missing CR with minicom, I was just ensuring that the GERMS: monitor was running. The issue that I am trying to resolve is that nios-run -t accepts the initial output from GERMS: and the peripheral test program, displays the menu on the terminal and then ignores all keyboard input from the host, regardless of trying various settings for lf/cr on the tty output. This led me to suspect that there was a problem with nios-run communicating. thanks anyway, nigelg -- Nigel Gunton School of Electrical & Computer Engineering CEMS, UWE, Bristol, BS16 1QY, UK.Article: 71007
Hi guys,
It's been ages since I haven't posted anything here...
Well, I have a problem trying to build a design:
- 311 MHz LVDS clock to IBUFGDS
- to DCM
- generates CLK0 to BUFG (rxclk0_311a_ig)
- generates CLK180 to BUFG (rxclk180_311a_ig)
easy so far...
Data comes in as an LVDS differential nibble (or nybble :O) apologies from
my Spanish-English), I am supposed to Double Data Rate the data...
I have tried instantiating the whole thing:
i_rxdata_a0: IBUFDS_LVDS_25
port map (
I => rxdata_a(0),
IB => rxdata_a(1),
O => rxdata_a_diff(0)
);
i_rxdata_a1: IBUFDS_LVDS_25
port map (
I => rxdata_a(2),
IB => rxdata_a(3),
O => rxdata_a_diff(1)
);
i_rxdata_a2: IBUFDS_LVDS_25
port map (
I => rxdata_a(4),
IB => rxdata_a(5),
O => rxdata_a_diff(2)
);
i_rxdata_a3: IBUFDS_LVDS_25
port map (
I => rxdata_a(6),
IB => rxdata_a(7),
O => rxdata_a_diff(3)
);
G_1: for i in rxdata_a_diff'range generate
i_rxdata_a: IFDDRRSE
port map (
Q0 => rxdata_a0(i),
Q1 => rxdata_a1(i),
C0 => rxclk0_311a_ig,
C1 => rxclk180_311a_ig,
CE => '1',
D => rxdata_a_diff(i),
R => areset,
S => '0'
);
end generate G_1;
Fair enough! I synthesize it with Precision and looks all right...
Then I use ISE to build it and during the translate process I get:
ERROR:NgdBuild:455 - logical net 'rxdata_a_diff(0)' has multiple drivers.
The
possible drivers causing this are pin O on block i_rxdata_a0 with type
IBUFDS, pin PAD on block rxdata_a_diff(0) with type PAD
and the same for the 3 remaining bits...
It seems to thing that the 'rx_data_a_diff' is a block with PADs (?), I have
try to remove PAD insertion in the whole design and still fails...
Any ideas in how to use DDR with differntial inputs?
Regards,
--
I.U. Hernandez
Article: 71008
Moti Cohen wrote:
> Marc Randolph <mrand@my-deja.com> wrote in message news:<u4ednTCBZ4B5q3XdRVn-vA@comcast.com>...
>
>>Moti Cohen wrote:
>>
>>>Hy all,
>>>I'm currently implementing a receiver (vhdl) part of the ethernet mac
>>>which is responsible for the MII interafce. I'm need an crc32
>>>calculator (RTL) to check the FCS field. I've tried using the easics
>>>crctoll in order to create the mechanism (for a 4 bit data input) but
>>>it does not seems to work. does anyone have a working (rtl) vhdl
>>>implementation for this block? or at least a detailed expalnation on
>>>how to create it..?
>>
>>
>> I'd be willing to bet that your problem is bit ordering (hint: take
>>an 8 bit chunk and reverse the order of the bits before throwing it into
>>the easics checker). Although I'm sure there is probably a way, I don't
>>quickly see how you'd do it four bits at a time.
>>
>
> Hi Marc,
> Thanks for your answer so first of all I have already tried revesring
> the bits order without any success - I read something about a "magic
> number" but I'm not sure what to do with it. regarding the 4 bit data
> path - the easics "crctoll" can generate a vhdl file for 1,2,4,8...64
> bits so its not the problem..
Howdy Moti,
I probably could have been clearer on my previous post. I may be
wrong, but it is my understanding that the BYTE must be bit-reversed.
i.e., bit(0) <= bit(7), bit(4) <= bit(3), etc. If you only have four
bits, you can't very well bit reverse 0 to 7.
We have used the 8 bit, 16 bit, and 32 bit easics code and they all work
fine (after you figure out the right bit order and such).
There are two ways to verify a CRC. One is to compute the check CRC on
everything up to, but not including, the received CRC. Then do a
compare between the two CRC's. The second way is to include the
received CRC in the calculation for the check CRC. If you do this, the
result is the magic number (assuming the checker was initialized with
all 1's).
Good luck,
Marc
Article: 71009OK, so are you sure the baud rates and COM port assignments are correct? The USB/RS232 cables have an annoying habit of shutting off, or getting different port assignments each time. If you are sure all is in order, then strip down you app to isolate the problem behavior. I have not used that specific example, but I have seen some pretty strange terminal related problems whenever I forgot to Generate the new SW support files before compiling. Are you sure Nios 3.2 will work with the older Quartus? The lastest Nios tools are Nios3.2, QII4SP1, and SOPC4. Better yet, the NiosII IDE is available. Nigel Gunton CEMS STAFF wrote: > On Sat, 3 Jul 2004, tns1 wrote: > > >>In both cases it sounds like you are missing carriage returns or line >>feeds. The staircase pattern is an classic example. You may need to set >>minicom to append carriage returns to incoming line feeds, to echo typed >>characters, or to send carriage returns with line feeds. Once you are >>sure both CR & LF is part of every line, it should be clear when you >>need them and when you don't. >> >> >>Nigel Gunton CEMS STAFF wrote: >> >>>Hi, >>> I'm having problems getting nios-run -t to function correctly. The >>>development platform is Quartus 3 sp2, SOPC 3.02 on Linux, Apex board. >>> >>>I'm using the standard_32 example provided with the Nios kit 3.2. This >>>builds (SDK and the hardware) without apparent problem, synthesises and >>>can be downloaded via the jtag interface. >>> >>>executing nios-run -t results in the peripherals test menu being displayed >>>but no response to keyboard input occurs, except ^C which occasionally >>>requires repeating to get the program to quit. Running strace shows >>>repeated calls to query the keyboard via select(), but only the ^c is >>>picked up on. >>> >>>Running minicom permits access to germs: and to the peripheral tests, >>>albeit with a 'staircase' problem on the output from the peripherals test, >>>but at least I have 2 way communication which implies that the problem >>>lies with nios-run. >>> >>>Running nios-run -p with a download file results in it waiting >>>indefinitely for the board to respond, both with the factory default and >>>the jtag downloaded file. >>> >>>Has anybody had similar problems? A search through the archives didn't >>>find anything, hence the post. >>> >>>AFAIUS, I need to use nios-run to reprogram the onboard flash or is there >>>an alternative. >> >> > thanks but ... > > I'm not too bothered by the missing CR with minicom, I was just ensuring > that the GERMS: monitor was running. The issue that I am trying to resolve > is that nios-run -t accepts the initial output from GERMS: and the > peripheral test program, displays the menu on the terminal and then > ignores all keyboard input from the host, regardless of trying various > settings for lf/cr on the tty output. > > This led me to suspect that there was a problem with nios-run > communicating. > > thanks anyway, > > nigelg > -- > Nigel Gunton > School of Electrical & Computer Engineering > CEMS, UWE, Bristol, BS16 1QY, UK. >Article: 71010
"I.U. Hernandez" <ulises@aliathon.com> wrote:
>Hi guys,
>
>It's been ages since I haven't posted anything here...
>
>Well, I have a problem trying to build a design:
>
>- 311 MHz LVDS clock to IBUFGDS
>- to DCM
>- generates CLK0 to BUFG (rxclk0_311a_ig)
>- generates CLK180 to BUFG (rxclk180_311a_ig)
>
>easy so far...
>
>Data comes in as an LVDS differential nibble (or nybble :O) apologies from
>my Spanish-English), I am supposed to Double Data Rate the data...
>
>I have tried instantiating the whole thing:
I hope my English translates well to Spanish.
Did you try just writing behavioral code and seeing what it did?
XST at least (I don't have Synplify or Precision at home) handles the
following code correctly. The final output from PAR is an input
buffer with DDR flip flops.
--
Phil Hays
Phil-hays at posting domain should work for email
______________________ Cut Here ______________________________
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity diffddr is
port (
mainclk : in std_logic;
rst : in std_logic;
diffa : in std_logic;
diffb : in std_logic;
diffout : out std_logic;
diffout_n : out std_logic
);
end entity;
--
architecture insts of diffddr is
signal clkin : std_logic;
signal clkdv : std_logic;
signal clk2x : std_logic;
signal clk0 : std_logic;
signal clk90 : std_logic;
signal clk180 : std_logic;
signal clk270 : std_logic;
signal clkfx : std_logic;
signal locked : std_logic;
signal clk : std_logic;
signal clk_n : std_logic;
signal diff : std_logic;
begin
-- put in a DCM
dcm_inst: dcm port map (
clkin => clkin,
clkfb => clk,
clk0 => clk0,
clkdv => clkdv,
clk2x => clk2x,
clkfx => clkfx,
clk90 => clk90,
clk180 => clk180,
clk270 => clk270,
rst => rst,
locked => locked
);
--And a clock pad buffer
clkbuf: IBUF port map (
o => clkin,
i => mainclk
);
-- and a bufg
clktree: bufg port map (
i => clk0,
o => clk
);
clk_n <= not clk;
-- Now the test code
diff0: IBUFDS_LVDS_25 port map (
I => diffa,
IB => diffb,
O => diff
);
process (clk) begin
if rising_edge(clk) then
diffout <= diff;
end if;
end process;
process(clk) begin
if falling_edge(clk) then
diffout_n <= diff;
end if;
end process;
end;
Article: 71011Hi Larry, I've used a considerable amount of your Linux build work on the Bright Star Engineering nanoEngine... sad to say it's now gone end of life.... anway... care to elaborate on which versions of of the Xilinx WebPACK work with WINE? Thanks man! Best Regards, Edwin Bland "Larry Doolittle" <ldoolitt@recycle.lbl.gov> wrote in message news:slrncdggem.c0p.ldoolitt@recycle.lbl.gov... > In article <40d6db9f_1@127.0.0.1>, andrew<AT>rogerstech<DOT>co<DOT>uk wrote: > > Xilinx and Altera have free downloadable design software available for > > their range of FPGAs, the problem is that it requires Windows. > > At least some versions of Xilinx WebPACK work with at least some > versions of WINE on Linux x86. Doesn't support all devices, but > enough to be interesting. > > - LarryArticle: 71012
Edwin Bland <edwinb@socal.rr.com> wrote: : Hi Larry, : I've used a considerable amount of your Linux build work on the Bright Star : Engineering nanoEngine... sad to say it's now gone end of life.... : anway... care to elaborate on which versions of of the Xilinx WebPACK work Try Webpack 6.2 with a recent CVS Wine (www.winehq.com), latest tagged build (040615) has some problems. It works more reliable with a native msvcrt, however Xilinx still doesn't manage to distribute MSVCRT with it's Webpack setup, although msvcrt is redistributable and a Webcase for that problem was opened some time ago. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 71013
Hi, I'd like to aske an important, for me, question : I have to compare the improvement of my design (the new version and the old one) with the same design that was implemented using ASIC. I am using Xilinx Virtex II for my implementations. The comparaison is about the area efficiency ratio : area(new_design)/area(old_design) and speed(new_design)/speed(old_design) and this comparaison is made for FPGA and ASIC implementations. The probleme is : do i have to take in consideration the number of 4 input LUT's used as a route-thru. I think that the correcte totale number of used LUT's will be : totale number of used LUT's "-" number of LUT's used as a route thru. Is that correcte or i have to take them in account too??? Thank for any helpArticle: 71014
hi,
I want to know what is meant by clock compensation and which
clock in the design should be compensated or used as compensated clock
and advantages
of doing so in an enhanced pll.
Article: 71015On Mon, 5 Jul 2004 23:09:27 -0700, "Antti Lukats" <antti@case2000.com> wrote: > >"Bob Perlman" <bobsrefusebin@hotmail.com> wrote in message >news:3vpde0p9u98hlop2aucsd27b11b919h8i8@4ax.com... >> On Sat, 3 Jul 2004 18:54:16 -0700, "Antti Lukats" <antti@case2000.com> >> wrote: >> >> <stuff snipped> >> >its not funny to simulate Full 1M Gate with MicroBlaze ! >> >> Does this mean it wasn't simulated? > >yes it means that the 1M gate desing with 32K application code for >Microblaze has not bein simulated. All the custome IP cores connected to >Microblaze of course have been simulated. > >> > and you can not simulate badly configured FPGA anyway, can you? >> >> No, but it remains to be seen whether that's the problem. If you >> haven't simulated, start there. > >Dear Bob, > >I have a bitstream that starts always OK when loaded from configuration >memory, and start with erratic behaviour 1 from 100 JTAG configuration >attempts (even when JTAG configuration did not show any error during >download). I don't know what this means. Are you getting erratic behavior in 1 out of 100 JTAG downloads? Or 100% of JTAG downloads? > When the bitstream starts badly it behavies badly after reset >also, only full new reconfiguration makes the system to working again. So I >do assume it is possible that the CRC check is not sufficent in Virtex2 >devices and that they actually do start also in case of bad download >sometimes. Resets do not reset everything. They do not, for example, re-initialize block RAM. If you are depending on the initial contents of a block RAM for proper operation, and your circuit occasionally stomps on block RAM shortly after start-up, your circuit may not work until you reconfigure. >You suggested this erratic behaviour of bad starting when loading from JTAG >could be found running simulations ?! Well I really cant understand that any >simulation models could take into account the errors that happend during >download. ?? Or what was it what I could possible find in simulation? As I said in my previous post, you haven't proved that configuration is the problem. And I'm not, repeat, NOT, suggesting that you somehow simulate the configuration process. But it would be interesting to know if there's a way resources like block RAMs could be corrupted shortly after you come out of reset, perhaps due to problems with interfaces between mutually asynchronous clock domains. I can't rule out the possibility that you are occasionally loading a corrupted bitstream, but it seems very unlikely. Doctors have a saying: when you hear hoofbeats, think horses, not zebras. If I had a design that I didn't simulate, and configuration seemed to complete successfully, I'd start looking somewhere other than configuration for my problem. Good luck, Bob Perlman Cambrian Design WorksArticle: 71016
Antti Lukats wrote: <snip> > Dear Bob, > > I have a bitstream that starts always OK when loaded from configuration > memory, and start with erratic behaviour 1 from 100 JTAG configuration > attempts (even when JTAG configuration did not show any error during > download). When the bitstream starts badly it behavies badly after reset > also, only full new reconfiguration makes the system to working again. So I > do assume it is possible that the CRC check is not sufficent in Virtex2 > devices and that they actually do start also in case of bad download > sometimes. Have you tried read-back of the FPGA in these cases ? Could be a candidate for an overnight run of continual download/readback's - is this single device specific, or common to multiple FPGAs ? -jgArticle: 71017
Hi, When i use Synplify to synthesis my VHDL design and then i enter the EDIF result file to ISE 6.1 softare and then i can creat area constraint without any troubles. Now if i enter directly my VHDL design to ISE and then synthesis it, when i open "creat area constraint" window, in the design broser window it doesnt shows the logic of my design that i need to place manualy (the folder existe but is empty) it shows only I/o Pins and Global logic (these folders are note empty). How to fixe this ? any idea?. Thanks for any help.Article: 71018
George Smith wrote: > hi > Has anyone used the uClinux port on the Xilinx MicroBlaze? > thanks, > gesmith > Hi George, Yes, I have :) Seriously though, it's out there, and growing rapidly. There's at least two commercial projects I know of (probably more, judging by the mailing list) - it's being used in our research group here at the uni and I know of several others that are starting to get it into their labs as well. The mailing list has about 150 subscribers, and there were about 70,000 hits on the website in the last 12 months, whatever that might mean. The Microblaze port is integrated into the main uClinux tree, and has been that way pretty much since the beginning. So, I guess the answer to you question must be a resounding yes! :) You can subscribe to, or browse/search the mailing list archives from this page: http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux/Mailing_List/index.htm Cheers, JohnArticle: 71019
I was simulating with some inputs set to 'X'=unknown on the inputs and
observing
defined outputs where I thought the output should be indeterminate.
Playing around some, I've reduced things to the following example.
The outputs are as determined by QuartusII v4.0SP1. No optimizations
turned on. The logic is not inside a process, but that doesn't make a
difference. Quartus II v3.0 sp2 behaves exactly the same.
A,B,Sel : in std_logic;
Y,Z : out std_logic;
-- Straight Combinatorial Logic:
Y <= A when Sel='1' else B;
Z <= (A and Sel) or (B and (not Sel));
Simulation Results:
Inputs -> Outputs
Sel A B -> Y Z
0 0 0 0 0
0 0 1 1 1
0 1 0 0 0
0 1 1 1 1
1 0 0 0 0
1 0 1 0 0
1 1 0 1 1
1 1 1 1 1 so far so good !
X 0 0 0 0
X 0 1 0 U :-( why is Y==A when Sel='X' ??
X 1 0 1 U
X 1 1 1 U ! simulator is able to figure out Z=0 when A=B=0
but
isn't able to figure out the case A=B=1
X X 0 X U
X X 1 X U ok no surprises here...
X 0 X 0 U
X 1 X 1 U well its consistent...
X X X 0 U @#$% Zero ???
So here's my questions...
(1) Is it a bad idea to use 'X' in a simulation ?
(2) Is there something I'm missing that explains this behavior ?
(3) I tried other logic functions and all possible 2-input
combinations with
9-valued inputs. The mux is the only thing that I find puzzling. Is
there
a preferred way to write the mux ?
P.S.:
1.As one might expect, the following behaves the same as the above
expr for Y
process (A,B,Sel) begin
if Sel='1' then Y<=A; else Y<=B;end if;
end process;
2.I looked at the synthesis equations but was not illuminated.
QIIv4.0sp1 does
simulation with a separate Functional Simulation Netlist, but I don't
know where
to find this in a readable form.
Thanks for any insights,
-rajeev-
Article: 71020
Hi
Has anybody used the D/A converter (Linear Tech's LTC1654) ? I am
having few issues . I tried to initialize using both the 24 and 32 bit
format but the output of D/A remains at 0.
Any help will be greatly appreciated
Thanks
Makesh
Article: 71021
Hi Roland,
You can do this easily with Quartus II 4.0 and later. The steps are
listed below.
1. Open a command line / DOS prompt. Make sure that quartus_cdb is in your
path. Then:
2. cd to the project directory
3. Type
quartus_cdb <project> --update_mif
4. Then type
quartus_asm <project>
In both cases replace <project> with the project name. The command in Step 3
will take the changed mif's and update the compiler database, without
recompiling the rest of the design. The commmand in Step 4 will regenerate
the pof/sof with the new mif.
Hope this helps.
Subroto Datta
Altera Corp.
"roland voraberger" <me@privacy.net> wrote in message
news:2kt63iF66k01U1@uni-berlin.de...
> hello!
>
> i want to compile a design for a altera acex or cyclon and i want to
> put additionally a table into it (f.e. a .mif file) without compiling
> it completely when changing the mif file (each delivered device has its
> own mif file or sth similar)
> what is the best way. does quartus have a possibility while burning to
> integrate the mif file into the pof file while burning?
> or should i use a enhanced configuration device and i must write a
> complete engine to read and write eth out of this device?
> or is it the best way to put simply an flahs onto the pcb?
> best regards, roland
>
> --
> reply me to madcapATsbox.tugrazDOTat
Article: 71022"Bob Perlman" <bobsrefusebin@hotmail.com> wrote in message news:3vpde0p9u98hlop2aucsd27b11b919h8i8@4ax.com... > On Sat, 3 Jul 2004 18:54:16 -0700, "Antti Lukats" <antti@case2000.com> > wrote: > > <stuff snipped> > >its not funny to simulate Full 1M Gate with MicroBlaze ! > > Does this mean it wasn't simulated? yes it means that the 1M gate desing with 32K application code for Microblaze has not bein simulated. All the custome IP cores connected to Microblaze of course have been simulated. > > and you can not simulate badly configured FPGA anyway, can you? > > No, but it remains to be seen whether that's the problem. If you > haven't simulated, start there. Dear Bob, I have a bitstream that starts always OK when loaded from configuration memory, and start with erratic behaviour 1 from 100 JTAG configuration attempts (even when JTAG configuration did not show any error during download). When the bitstream starts badly it behavies badly after reset also, only full new reconfiguration makes the system to working again. So I do assume it is possible that the CRC check is not sufficent in Virtex2 devices and that they actually do start also in case of bad download sometimes. You suggested this erratic behaviour of bad starting when loading from JTAG could be found running simulations ?! Well I really cant understand that any simulation models could take into account the errors that happend during download. ?? Or what was it what I could possible find in simulation? AnttiArticle: 71023
Luc Braeckman <luc.braeckman@pandora.be> wrote in message news:<co4ie010ld9h69mmp8i09l86i5l0uhs13a@4ax.com>... > IMHO, Altera's DSP block is only a multiplier. The MAC block Lattice > is proposing is much richer: reg, mult, pipeline reg, accu, reg. On > top of it, the IO cell has more regs than any other comparable > architecture. Please have a look at: http://www.altera.com/products/devices/stratix/features/stx-dsp.html and then see where Latice got thier ideas from. But you are correct for the lowcost families Altera (CycloneII) and Xilinx (spartan-3) has chosen Multipliers rather then DSP blocks. Put if you call Alteras DSP block a mulitiplyer you have to say the same about Latice since there are at least on the marketing slides I have seen identical. YMHO FredrikArticle: 71024
Folks, I have this question for a long time, just could not get an answer. Assume we have a design consisting of several blocks and some of those blocks are hinhly regular (for example, a datapath). When we do P&R, does the tool take the advantage of this regularity and place those datapath element in series? Or it just does P&R globally without looking at the local regularity? The reason I am asking this is that we have a design with blocks which are regular inside. But after P&R, the LUT utilization increases dramatically, it seems it uses lots LUT for routing which isn't expected just by looking at the regularity of the blocks. Thanks.
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