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On Sat, 19 Jun 2004 17:51:15 GMT, nico@puntnl.niks (Nico Coesel) wrote: > >Did you ever try to compress these files? I totally agree with you >that these files _look_ easy to compress, but they aren't. I tried >RLE, but that will only save 5% to 10%. ZIP does a little better. I >just tried to compress a .bit file for a 400k gate Xilinx device and >it reduces the size by 26% but you'll need to have room for the ZIP >decompression code... I tried my simple run-encoder. On various designs I have around, it achieved compression ratios of (best) 0.56 and worst 1.04 (ie, compressed was bigger than uncompresssed!) The worst was on a fairly dense XC2S400 bga part, whose rbt file had hardly any long runs of anything. Even pkzip only managed to crunch the binary config image to 0.74 on this one. It looks to me that the newer Xilinx chip files tend to be less compressible... seem to have fewer runs. So maybe there's no very-simple-to-unpack thing that's generally useful. Needs more thought someday, I guess. JohnArticle: 70551
On Sun, 20 Jun 2004 17:45:27 +0000, Gregg C Levine wrote: > Hello from Gregg C Levine > I have here an XC3020, and matching configuration storage EEPROM, an > XC1736DPC, the were originally purchased for another project. We ended up not > doing that project. Now we'd like to use both for something completely different. > Are these parts still supported by Xilinix? Has anyone heard differently? We'd also > prefer to do the programming under Linux. > Gregg C Levine drwho8 atsign att dot net The 3000 series hasn't been supported for years. As for programing it in Linux, Linus was in grade school when the 3000s were current so you aren't going to find any Linux native tools that support them. However you should be able to run the old DOS based XACT tools under wine.Article: 70552
Hi Miika, Youu need a license file that contains a mainwin_lnx entry or something to that effect in addition to the quartus line. You can ask your Altera FAE or sales person to get it for you. Typically yo have got this line generated if you had specified that you were using the Linux platform at the time of purchasing the Quartus subscription. Hope this helps. - Subroto Datta Altera Corp. "Miika Pekkarinen" <miika.nospam1@ihme.org> wrote in message news:0tjBc.2055$Fc3.1666@reader1.news.jippii.net... > Hello, > > I have Altera Quartus II 4.0 software and I managed to successfully install > it on a Debian Linux machine (with Intel Pentium 4 processor). However, > always when I try to start the software, I will get the following messages: > > "Choose the preferred look and feel for the Quartus II software..." > > I select Quartus II and click OK. After that I will get: > > "MainWin license not available -- to run the Quartus II software, you > must specify a valid license file that contains a MainWin license." > > I have searched Altera web sites and newsgroups but was unable to find out > what is this MainWin license. So does anybody know what it is, where could > I get one and how to specify the license file for Quartus? > > Thanks for your advice. It would be nice if I could do finally all FPGA > development on Linux. > -- > Miika Pekkarinen <miipekk@it.jyu.fi>, > Department of Math. Information Technology, > University of Jyvaskyla, P.O. Box 35, FIN-40014 Jyvaskyla, FINLAND > > >Article: 70553
Hi all,
Maybe this question has been asked before, but I couldn't find a
suitable answer on this group until now. Having followed the coding
styles recommended by Xilinx, I ended up with the following code:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity dual_port_ram is
generic (
WIDTH : integer := 32;
DEPTH : integer := 10
);
port (
w_clk : in std_logic;
w_en_in : in std_logic;
w_addr_in : in std_logic_vector(DEPTH-1 downto 0);
w_data_in : in std_logic_vector(WIDTH-1 downto 0);
r_clk : in std_logic;
r_addr_in : in std_logic_vector(DEPTH-1 downto 0);
r_data_out : out std_logic_vector(WIDTH-1 downto 0)
);
end entity;
architecture xilinx of dual_port_ram is
type memory_type is array (natural range <>) of
std_logic_vector(WIDTH-1 downto 0);
signal memory : memory_type(2**DEPTH-1 downto 0);
begin
write : process(w_clk)
begin
if w_clk'event and w_clk = '1' then
if w_en_in = '1' then
memory(to_integer(unsigned(w_addr_in))) <= w_data_in;
end if;
end if;
end process;
read : process(r_clk)
begin
if r_clk'event and r_clk = '1' then
r_data_out <= memory(to_integer(unsigned(r_addr_in)));
end if;
end process;
end architecture;
Yet, instead of BlockRAM, XST implements this as distributed RAM (with
combinational output) plus registers at the output, issuing the
following:
INFO:Xst:1435 - HDL ADVISOR - Unable to extract a block RAM for signal
<memory>. The read/write synchronization appears to be READ_FIRST and
is not available for the selected family. A distributed RAM will
usually be created instead. To take advantage of block RAM resources,
you may want to revisit your RAM synchronization or check available
device families.
Found 1024x32-bit dual-port distributed RAM for signal <memory>.
What is this read/write RAM synchronization after all? Maybe the
Xilinx folks (Peter Alfke & Co.) could help ;)
Thanks
Article: 70554I'm using Synplify 7.2 Pro to synthesize a rather simple design for an AT40K10AL component. My problem is thet Synplify likes to add a few macros that Atmel doens't support directly in their IDS place and route tool. These are, more spefically, the ldrasa and fdrasa cells. I found that for Xilinx parts, Synplify ships with macros that can be used by the Xilinx p/r tool, however I have found no such substitute for Atmel devices. Is anyone aware of a solution to this problem? Are there macros available to solve the problem? or better yet, is there a way to tell Synplify not to use certain types of cells when synthesizing? Thank you. --Greg --Article: 70555
In article <pan.2004.06.20.17.57.34.653961@yahoo.com>, schvantzkoph@yahoo.com says... > >On Sun, 20 Jun 2004 17:45:27 +0000, Gregg C Levine wrote: > >> Hello from Gregg C Levine >> I have here an XC3020, and matching configuration storage EEPROM, an >> XC1736DPC, the were originally purchased for another project. We ended up not >> doing that project. Now we'd like to use both for something completely different. >> Are these parts still supported by Xilinix? Has anyone heard differently? We'd also >> prefer to do the programming under Linux. >> Gregg C Levine drwho8 atsign att dot net > >The 3000 series hasn't been supported for years. As for programing it in >Linux, Linus was in grade school when the 3000s were current so you aren't >going to find any Linux native tools that support them. However you should >be able to run the old DOS based XACT tools under wine. Hello (again) from Gregg C Levine Now where'd I go about obtaining the older XACT series of tools from? I don't suppose the company still has them....... Gregg C Levine drwho8 atsign att dot netArticle: 70556
Hello, I'm new to the world of CPLDs or FPGAs so please be easy on me. We have a requirement for an 8 channel (12 channel would be better) countdown timer at 12 to 14 bit resolution with a 20MHz clock input. All we need is to be able to load the channel's timer value via the processor's data bus and start the timers after the last channel is loaded. We need 8 (or 12) outputs that go high during the countdown and turns off when the timer times out and stays off until the next time they are loaded. Is this possible in a relatively cheap CPLD and which "family" would be a good starting point? If this is a complicated design we would certainly entertain the possibility of farming this out. Thanks, RichardArticle: 70557
Zak <jute@zak.invalid> wrote: >Nico Coesel wrote: > >> Did you ever try to compress these files? I totally agree with you >> that these files _look_ easy to compress, but they aren't. I tried >> RLE, but that will only save 5% to 10%. > >Probably because the looks for repeating bytes, while here we have only >repeating stretches of 0's. What might work is to re-code the file into >numbers giving the number of 0 bits between 1's as a first step: > >00100000101000000000010000011000000000001 would turn into >2 - 5 - 1 - 10 - 5 - 0 - 11. > > Stretches of 0 more than 254 long could be encoded as 255, meaning 255 >zeroes and no 1, whith the next number to give more 0's. 1-[255 0s]-1 >would code to 255 0 in that case. > >The resulting bytes are probably easier to huffman compress. Or it may >pay to do this for 0 runs up to 16 long, and coding these as bytes with >values 0-15 (not as nibble pairs, subsequent nibbles probably do not >have any relationship). This makes sense. Haven't tried is though. I presume(d) ZIP looks at the bits instead of the bytes. Still, don't feel lucky because you seen a lot of contiguous '1's and '0's. Here is a wild idea: Another way of compressing the file may be by stripping the frame headers (which are repeated at the start of each frame, these can easely be added during decompression) and sorting the resulting data. Next step is compressing it, but not by going from left to right, but going from top to bottom and compress column after column. Because of the sorting, least changes from 0 to 1 are to be expected in a column. Decompressing however would require a fair amount of memory, so the data also has to be divided in blocks so only a block at a time needs to be decompressed. IIRC it doesn't matter in which order the data frames are loaded as long as the command frames are at the right place. Xilinx has some thorough information on their programming datastream on their website. -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 70558
Hi Richard - [1] Suppose 12 channel x 14 bits = 164 FF. For counters. Decode logic sizing is processor dependant, but assuming "simple" synchronous IO strobe with decoded address bits for port decoding, this consumes combinational decode as opposed to FF. I would be looking at a device with maybe 200 FF. [2] 14 bit counters should clock at close 100Mhz + in a CPLD. [3] Try Xilinx 9500 series CPLD. Example, XC95288 offers 288 FF. They have families for different voltage ranges, power consumptions, but this ought to guide you to one solution. Xilinx may not be the only candidate. Lots of vendors offer free compilation tools for their smaller devices .... Xilinx is such vendor. [4] Definitely not challenging. 30 minutes to 2 hours experienced designer. Core design is simple ... but all designs have their curve balls that were not obvious up front. Try a local university ... lots of good students anxious to demonstrate their HDL skills. -- Regards, John Retta - Colorado Based Xilinx Consultant Owner and Designer Retta Technical Consulting Inc. email : jretta@rtc-inc.com web : www.rtc-inc.com "Richard Cooke" <rcooke@redmtnengr.com> wrote in message news:MKoBc.2634$3E1.1401@newssvr25.news.prodigy.com... > Hello, > > I'm new to the world of CPLDs or FPGAs so please be easy on me. We have > a requirement for an 8 channel (12 channel would be better) countdown > timer at 12 to 14 bit resolution with a 20MHz clock input. > > All we need is to be able to load the channel's timer value via the > processor's data bus and start the timers after the last channel is > loaded. We need 8 (or 12) outputs that go high during the countdown and > turns off when the timer times out and stays off until the next time > they are loaded. > > Is this possible in a relatively cheap CPLD and which "family" would be > a good starting point? If this is a complicated design we would > certainly entertain the possibility of farming this out. > > Thanks, > > RichardArticle: 70559
Hi, I try to send bits to my xc4010XL FPGA through a parallel cable but I encounter problems... I've got LED conected to the right pin (they are working fine because I have already tested them with an other program). Well, i use a program to change the parallel cable pin value (work fine too because i controlled each pin with a multimeter). When i use the special pin MD0 and MD2 it work fine (i can display the value on the led) but whenever i try use acquire the data through the data pin (P45 to P49) it does not work... Did I forget a special component, configuration? I tryed with IBUF.. thank you for helping meArticle: 70560
On 20 Jun 2004 14:55:20 -0700, pmihail@gmx.net (Acciduzzu) wrote: >The read/write synchronization appears to be READ_FIRST and >is not available for the selected family What logic family? If I recall correctly, Virtex, VirtexE, Spartan-2 and Spartan-2E all do not support Read_First, they only support Read-After-Write. You might try targeting Virtex-2, Virtex-2 pro or Spartan-3. --Å_Œil Hays Phil_hays at posting domain should work for emailArticle: 70561
On 18 Jun 2004 14:33:28 -0700, henk@mediatronix.com (Henk van Kampen) wrote: >Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> wrote in message news:<f8f5d09c1bhectj9dm3qtv1e771tnug1j7@4ax.com>... >> This doesn't help the OP though, as the core itself is written in >> VHDL. Steve, would there be any problem if a third party (e.g. me) >> were to publish a behavioural Verilog description of picoblaze[123]? > >Allan: >The Picoblaze cores are, although VHDL, just instantiations of LUTS >and FF's. So a straight translation should be possible. Possible, yes, but would it be frowned upon by Xilinx? Regards, Allan.Article: 70562
Hi, all,
From the incoming data flow, I will collect a fixed number of data (say 88
samples, each with 8-bit width). I want to use RAM to buffer the incoming
data, and after the RAM is filled up with 88 samples, I will output all
these 88 samples simultaneously to
another buffer to perform further operation. If I don't use RAM, it will be
synthesized as D Flip-flop for the incoming data buffer, which is quite
resource cosuming. So I want to instantiate as or refer to distributed RAM
or Block RAM (using xilinx virtex 2).
But the available RAM seems working this way, one data in and one data out.
port(
RB_CLK8x : in STD_LOGIC;
RB_WREn : in STD_LOGIC;
RB_RDEn : in STD_LOGIC;
RB_WRAddr : in STD_LOGIC_VECTOR(7 downto 0);
RB_RDAddr : in STD_LOGIC_VECTOR(6 downto 0);
RB_DataIn : in STD_LOGIC_VECTOR(7 downto 0);
RB_Dout: out STD_LOGIC_VECTOR(7 downto 0)
);
so how can I input data one by one, and output them in parallel way?
Any comments or suggestion will be heartly appreciated.
regards,
freedragon
Article: 70563The solution i suggest to you here is to use a FIFO , which in fact consists in a blockram surrounded by a little manager design. There are plenty of fifo designs available, the best is to go at xilinx.com The use of a fifo is extremly simple , just handle a read signal to pop data and a write signal to push data, just a little trick : in the design where you use teh FIFO, doing things (pop or push data) at CLOCK falling edge simplify even more the things The data flow in your app is not sufficiently described to allow to choose between a synchronous (data producer & consumer share the same CLK) or asynchrounous (each having his own CLK). "Jimmy" <mljiang@eee.hku.hk> a écrit dans le message de news:cb5mre$t63$1@hkueee5.eee.hku.hk... > Hi, all, > > From the incoming data flow, I will collect a fixed number of data (say 88 > samples, each with 8-bit width). I want to use RAM to buffer the incoming > data, and after the RAM is filled up with 88 samples, I will output all > these 88 samples simultaneously to > another buffer to perform further operation. If I don't use RAM, it will be > synthesized as D Flip-flop for the incoming data buffer, which is quite > resource cosuming. So I want to instantiate as or refer to distributed RAM > or Block RAM (using xilinx virtex 2). > > But the available RAM seems working this way, one data in and one data out. > port( > RB_CLK8x : in STD_LOGIC; > RB_WREn : in STD_LOGIC; > RB_RDEn : in STD_LOGIC; > RB_WRAddr : in STD_LOGIC_VECTOR(7 downto 0); > RB_RDAddr : in STD_LOGIC_VECTOR(6 downto 0); > RB_DataIn : in STD_LOGIC_VECTOR(7 downto 0); > RB_Dout: out STD_LOGIC_VECTOR(7 downto 0) > ); > > so how can I input data one by one, and output them in parallel way? > Any comments or suggestion will be heartly appreciated. > > regards, > freedragon > >Article: 70564
> I want to use RAM to buffer the incoming data, and after the RAM is > filled up with 88 samples, I will output all these 88 samples > simultaneously to another buffer to perform further operation. That would make 704 data-signals between your buffers ... why would you want to do that!? for a fast buffer-to-buffer transfer?? - you could transfer to the next buffer at a faster clock and higher width ... lets say 100MHz and 32Bits would make 220 ns ... still too long?! - you could switch between input-buffers ... your data-processing works on one of your input-buffers while the second one is filled from your input ... switching between them could be done fast ... bye, MichaelArticle: 70565
"Hendra Gunawan" <u1000393@email.sjsu.edu> wrote: > How about digital logic design engineer? What kind of math required other > than basic arithmetic? And don't they need a lot less math than say an RF > engineer? Depending on the level of abstraction. Nowadays your tools doing all the nasty stuff, so you don't even need to know boolean arithmetic. However it's still good to know the basics, of what your tools doing to get good results. I think you need less skills in "applied higher mathematic" than an RF engineer but at least the same amount in more abstract mathematics like coding theory, formal algorithms, complexity theory, automation therory and so on. If you like to implement eg a booth multiplier you end up with more mathematic than you ever wanted to learn. The actual needed mathematics may be strongly dependent on the kind of circuits your doing. When working on digital ASICs for RF you need other mathematical skills then needed in CPU development or similar ASICS for number crunching. Image processing has other needs than lowpower design. bye ThomasArticle: 70566
Hi Phil, I am targeting a Spartan-IIe btw. What I do not know is what that read/write synchronization is. Maybe you know also how I can infer a dual-ram for Spartan-IIe? CheersArticle: 70567
Now I am doing Xilinx Virtex2 (xc2v1000) readback to capture register states. I have some question about it, I hope somebady can help me! Thanks a lot. 1. when I only want to read back one frame, for instance, xc2v1000 device,after I specify the frame address in the FAR register, How many frame size (number of word to readback) should I load to FDRO register(only type I )? xc2v1000 has the frame length in bits 3392. If does the readback stream contain one pad frame(3392 bit) prior to the desired readback frame (3392 bit) specified by FAR register? The question is number of frame size ,106 or 212? 2.are there pad words between the readback frames? 3. flush the command pipe with 32 bits of zeros. How many times should I do? Because I have read the Virtex2 platform user guide(ug002.pdf), all configuration has 2 times to flush pipe. This is what I send to the cfg_in to initiate the transfer one frame, 0xaa995566; synchronization Word 0x30016001; FLR Write packet header 0x00000069; FLR write packet data 0x30008001; CMD write packet header 0x00000007; CMD write packet data(RcRc) 0x30008001; CMD write packet header 0x00000004; CMD write packet data(RCFG) 0x30002001; FAR write packet header frameaddr from .ll file; FAR write packet data (frame address) 0x280060d4; FDRO write packet head (type 1), d4(hex) = 212(dec) 0x00000000; Flush the command pipe. then, Load the CFG_OUT instruction into the JTAG IR, then go to the SDR. is that right? Thank you for reading. Any information about it is welcome. Thanks in advance.Article: 70568
I need to use spartan series FPGA for a design.( As design have only 5 V supply available). when I start a new project in XILINX ISE 6.1 I dont get option of Spartan in Device selection list. can anyone help me out. which software do I need. Thanks for any helpArticle: 70569
======
URGENT
======
I have a small query and if possible do help me on this issue.
|
|FPGA |=========
| -->| Din
Processor<->|<----> | This is my dual port memory
data line | <--| Dout
(bidir) | |=========
|
|
I have my main module dataline to be bidirectional so that there is no
separate datalinein and separate datalineout. So Iam making it to be
configured as input and output using the read enable and write enable.
as shown below… I need to know whether its correct or not.
I have no doubts with the memory code below, its working fine when I
make it a read only memory,so that in in the top level indicated below
Ive made the ebmdat as out and directly connected it to the memory out
port.So on reset I hardcode some data and when attempted to read,it
worked fine. But when Bidirectional pin is used as shown below I got
problems.
This is My Top Level accesing my Memory
---------------------------------------
Library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ebmem_top is
port ( ebmclk : in std_logic;
ebmnwt : in std_logic;
ebmnrd : in std_logic;
ebmadd : in std_logic_vector(5 downto 0);
ebmncs : in std_logic;
ebmdat : inout std_logic_vector(7 downto 0));
--It has only a single Port and it should Connect both
input
and output of memory according to ebmwt and ebmrd, which is
achieved with two temporary signals datain and dataout
end ebmem_top;
architecture arc of ebmem_top is
component ebmem ----- MEMORY and its defn in nxt page
------
port (ebmclk : in std_logic;
ebmnwt : in std_logic;
ebmadd : in std_logic_vector(5 downto 0);
ebmncs : in std_logic;
ebmdati : in std_logic_vector(7 downto 0);
ebmdato : out std_logic_vector(7 downto 0));
end component;
signal datain, dataout : std_logic_vector(7 downto 0);
begin
ebmemory : ebmem port map(ebmclk,ebmnwt,ebmadd,ebmncs,datain,dataout);
process(ebmclk)
begin
if(ebmclk='1' and ebmclk'event)then -- THIS IS WHERE THE SWAPPING
HAPPENS
if(ebmnwt = '0')then -- ebmnwt is active low signal
datain <= ebmdat;
ebmdat <= (others =>'Z');
else
ebmdat <= dataout;
end if;
end if;
end process;
end arc;
=================================================================
Assume that its my Memory Core
------------------------------
Library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ebmem is
port ( ebmclk : in std_logic;
ebmnwt : in std_logic;
ebmadd : in std_logic_vector(5 downto 0);
ebmncs : in std_logic;
ebmdati : in std_logic_vector(7 downto 0);
ebmdato : out std_logic_vector(7 downto 0));
end ebmem;
architecture ebm_arch of ebmem is
type memarray is array(63 downto 0) of std_logic_vector(7 downto 0);
signal memloc : memarray;
signal read_a : std_logic_vector(5 downto 0);
begin
process(ebmclk)
begin
if (ebmclk = '1' and ebmclk'event) then
if (ebmnwt = '0' and ebmncs = '0' ) then
memloc(conv_integer(ebmadd)) <= ebmdati;
end if;
read_a <= ebmadd;
end if;
end process;
ebmdato <= memloc(conv_integer(read_a));
end ebm_arch;
==================================================================
Article: 70570"Michael Rhotert" <mrhotert@yahoo.com> wrote in message news:<cau9qq$vpq$05$1@news.t-online.com>... > <sanpab@eis.uva.es> wrote > > Hi all, > > > > I have installed ISE Foundation (6.2.03) and tried to generate an > > EDIF file from a Verilog file. > > Hi, > synthesize your design with xst and then use ngc2edif.exe from command line > to translate the *.ngc netlist to EDIF format. > > Another option is to run the 'translate' (ngdbuild) step after synthesis and > then use ngd2edif.exe from command line. > > /Michael Thanks Michael, it works fine. The generated file was a NDF, so I renamed it to EDF and use it as a black box in other designs. Any advices about parameters? May I use the black box with parameters or I must generate an EDF for each combination of them? Regards, Santiago.Article: 70571
I need to use spartan series FPGA for a design.( As design have only 5 V supply available). when I start a new project in XILINX ISE 6.1 I dont get option of Spartan in Device selection list. can anyone help me out. which software do I need. Thanks for any helpArticle: 70572
more info on such circuits: http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=&iLanguageID=1&multPartNum=1&sTechX_ID=kc_srl16e "Symon" <symon_brewer@hotmail.com> wrote in message news:2j9b41Fvcao4U1@uni-berlin.de... > Hey Goran, > How about posting the code direct. Not all of us have news hosts that can > pass on attachments! > Ta, Syms. > >Article: 70573
Many thanks for the tips, both direct and via the news group.
Not much of a progress understanding what is going on.
Replying to some of the comments I've received I can tell:
- "octnr" was added in the sensitivity list but no effect.
- a full MUX was done on the input (save resources but
that part was working ok already)
- The fitter produces a quite a different thing in the two situations
it seems that to bring this signal out of the CPLD changes a lot of things.
- Used Quartus II instead and it doesn't work with or without testpoint.
it behaves the same as MAX+II without testpoint.
- doesn't seem to be an electrical as all other bus operations work
and most important of all, The SIMULATION produces the same
strange behavior, so it is something I'm doing or the compiler/fitter
doesn't like it ... but what ?!
Would somebody please let me know what would be your
usual way of writing the VHDL to make an output port out of an 8bit bus?
with ("address"(=something) and "data" bus and "write" signals only).
Maybe I'm doing it all wrong.
Many Thanks.
Luis Cupido.
Article: 70574> >OK, bear with me on this. Here's a piece of a .rbt for a Spartan XL... > > > >00111111110001000000000000000000 > > > >Which has long runs of zeroes! > > > >Just eyeballing these files, it looks like something very simple could > >get at least a 2:1 squash factor. > > Did you ever try to compress these files? I totally agree with you > that these files _look_ easy to compress, but they aren't. I tried > RLE, but that will only save 5% to 10%. ZIP does a little better. I > just tried to compress a .bit file for a 400k gate Xilinx device and > it reduces the size by 26% but you'll need to have room for the ZIP > decompression code... As noted before, Ralph Kuhnert, a student of mine, did. http://www.sulimma.de/prak/ws0001/projekte/ralph/Projekt/index.htm http://www.sulimma.de/prak/ws0001/projekte/ralph/Projekt/Projekt.PPT He achieved 30% to 70% compression just using RLE on XC4K data. You probably applied the RLE on bytes as a previous poster suggested. That does not help because the Xilinx data is not byte aligned. (In the histogramms you can see for example that for all designs runs of 19 consecutive 1s are quite common. This probably represents some CLB data, an unsued LUT or something like that.) You need to encoded the individual bits. What worked very well for XC4K is to use 4 Bits per codeword to encode either a zero followed by 0 to 13 ones or 14 ones. Kolja Sulimma
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