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I 've generated 18x18 block based multipliers using Synplify_pro tool. Now I want to generate logic based multipliers( which dont use blocks ). I 've no knowledge on the contsraint files used to generate multipliers using synplify_pro. Can any one let me know on how I can generate logic based multipliers. The following is the .prj file used to generate 10x33 block based multiplier. #-- Synplicity, Inc. #-- Version 7.3.4 #-- Project file ./Mult10x33/Mult_mult10x33.prj #-- Written on Wed Feb 25 16:47:33 2004 #add_file options add_file -vhdl mult10x33.vhd #implementation: "rev_1" impl -add rev_1 #device options set_option -technology VIRTEX2 set_option -part XC2V40 set_option -package CS144 set_option -speed_grade -6 #compilation/mapping options set_option -default_enum_encoding default set_option -symbolic_fsm_compiler 1 set_option -resource_sharing 1 set_option -use_fsm_explorer 0 #map options set_option -frequency 1.000 set_option -fanout_limit 10000 set_option -disable_io_insertion 1 set_option -pipe 0 set_option -update_models_cp 0 set_option -verification_mode 1 set_option -fixgatedclocks 0 set_option -modular 0 set_option -retiming 0 #simulation options set_option -write_verilog 1 set_option -write_vhdl 1 #automatic place and route (vendor) options set_option -write_apr_constraint 1 #set result format/file last project -result_file "rev_1/mult10x33.edf" #implementation attributes set_option -vlog_std v2001 impl -active "rev_1"Article: 70451
Hi, I had the same problem. I think that the clk0 line is routed through a dedicated clock routing line(global) and cannot be brought out. The reason for this I am not sure of yet. But, there isa work around. U could instantiate the FDDRE ( IOB Double data rate registers) primitive and set the inputs to the 2 ff(s) in such a way that the output mimic the clock exactly. -- Joji John ( nansung444@yahoo.com) "Cogito; ergo sum" " plain text reduces headaches" http://www.angelfire.com/ma3/joji http://geocities.com/nansung444 "charles" <czheng@ieee.org> wrote in message news:d2fa3f25.0406071851.5a94c50b@posting.google.com... > I am doing a small experiment with DCM. I used the coregen to > configure it to use a 100Mhz input clock, and output CLK0 and LOCKED. > RST is also tied to a pushbutton RESET. Feedback 1x internal is > configured, and so does the duty cycle correction. Then I instantiate > the module in schematic, and tie all the port to inport and outport > apprepriately without any IBUF,OBUF or BUFG primitives. I noticed a > extra pin coming out of the DCM: CLKIN_IBUFG_OUT. I implemented the > design and downloaded to a xc2vp4 FPGA prototype board. But somehow I > can not get CLK0 to come out. CLKIN_IBUFG_OUT is coming out fine. > LOCKED is still low. So it is not locking, and that is why CLKO is > not coming out. But why? Such a simple design. Someone help. > > CharlesArticle: 70452
tom this link might help you http://www.fpga-faq.com/FPGA_Boards.shtml tomgoogle2000@yahoo.com (tom) wrote in message news:<f185e49c.0406161450.e80a813@posting.google.com>... > Hi, guys, I try to find a company which can provide a FPGA based PCI > board with ethernet port, thanks in advance. > the system requirement: > 1. since my algorithm is computation intensive, it should be run on > FPGA, I try to find a FPGA based PCI board, the desirable FPGA would > be xilinx virtex II or virtex pro > 2. the FPGA based PCI board has a ethernet port, and there is windows > 2k or XP driver for this port > 3. it is better the company can also provide A/D and D/A board > thanks, > TomArticle: 70453
>Another general suggestion: when designing a peripheral as you are, >consider (at least for bring-up purposes), include registers that >allow you to read back the data... Good suggestion. Often you can do it with almost no additional hardware. Sometimes a CSR type register has enough bits for this purpose. You just have to readback the C bits while reading the S bits. If there are any unused bits, you can make them R/W but not connected to anything (else). Sometimes you can make a write only data register read/write with the read path being used only for this purpose. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 70454
There is a possibility we may be able to support your needs. Contact us through one the email addresses on our website I will discuss more detail offline. Meanwhile details of the base board Broaddown2 are here http://www.enterpoint.co.uk/moelbryn/broaddown2.html . John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk This message is the personal opinion of the sender and not that necessarily that of Enterpoint Ltd.. Readers should make their own evaluation of the facts. No responsibility for error or inaccuracy is accepted. "tom" <tomgoogle2000@yahoo.com> wrote in message news:f185e49c.0406161450.e80a813@posting.google.com... > Hi, guys, I try to find a company which can provide a FPGA based PCI > board with ethernet port, thanks in advance. > the system requirement: > 1. since my algorithm is computation intensive, it should be run on > FPGA, I try to find a FPGA based PCI board, the desirable FPGA would > be xilinx virtex II or virtex pro > 2. the FPGA based PCI board has a ethernet port, and there is windows > 2k or XP driver for this port > 3. it is better the company can also provide A/D and D/A board > thanks, > TomArticle: 70455
Thanks for all replies about this problem... I find the answer to create a bitstream file and using command line to configure the FPGA. The result is in the iMPACT documentation, I missed it in the first time when seeing the document. Thanks. Neil Glenn Jacobson <n.e.i.l.j.a.c.o.b.s.o.n.a.t.x.i.l.i.n.x.c.o.m.> wrote in message news:<cakn21$pe62@cliff.xsj.xilinx.com>... > iMPACT can convert a bitstream file to an SVF file automatically using > the File Generation mode (Create SVF/XSVF Files Operation) > > Please check the on-line help for details. > > > Yang-Tzu wrote: > > Hi, > > Is anyone has the experience of converting bitstream file format to > > svf file format? > > > > It seems that iMPACT can't create svf file but bitstream file. > > (Any document about this? The help of iMPACT have no solution. :( > > ) > > > > Is anyone has the answer? > > > > thanks. > > Yang-TzuArticle: 70456
"Thierry Gschwind" <thierryg@ee.ethz.ch> wrote in message news:40ce11d3$1@pfaff2.ethz.ch... > The guys who designed the hardware hardwired M2 and M1 to ground, it's > nearly not possible to change them. Thierry, If you're using a QFP (which I presume you are if you've soldered this down yourself) it's not impossible to lift a pin, even with pin pitches of 0.5mm. You'll need a stereo microscope or other good maginifer, and a scalpel with a new blade. Prepare the area with pleanty of flux. Position the scalpel tip between the pin in question and one of its neighbours. Put pleanty of solder on the iron and heat the pin in question, gently levering against the neighbour. You should be able to prise it up, but be careful with it, don't bend it up and down too many times or it'll snap off. Clean up the adjacent pins with solder-wick and re-do and than need tidied up. You can then get a flying wire on the pin you've lifted, but be careful with it, as I said above it's not mechanically strong and you don't want to overheat it. Not that I've ever had to do this of course ;-) Nial. ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design Cyclone Based 'Easy PCI' proto board www.nialstewartdevelopments.co.ukArticle: 70457
Hi all, I have downloaded a VHDL version of PicoBlaze. I can synthesize it with other VHDL modules, my I prefer the use of Verilog, so the only way I can use it with them is through EDIF black-box. Anyway, life could be better if I can use a verilog version of PicoBlaze directly. Does anyone know if it exists? Thanks in advance, Santiago.Article: 70458
On 17 Jun 2004 02:39:09 -0700, sanpab@eis.uva.es wrote: >Hi all, > > I have downloaded a VHDL version of PicoBlaze. I can synthesize it >with other VHDL modules, my I prefer the use of Verilog, so the only >way I can use it with them is through EDIF black-box. > > Anyway, life could be better if I can use a verilog version of >PicoBlaze directly. Does anyone know if it exists? 1. No, a Verilog version doesn't exist. (If you write one, let me know!) This is a PITA. 2. The latest version of picoblaze uses an NGC file rather than EDIF. You should probably upgrade. Also, you should use picoblaze2 if you can; the extra code space helps. 3. There shouldn't be any problems synthesising with a black box. (I'm doing something similar in my current design.) 4. There *is* a problem with simulation though: you will need to find a simulator that can do both languages simultaneously. These tend to cost a lot. 5. Ken Chapman's kcpsm/kcpsm2 assembler uses template files (e.g. ROM_form.vhd) when it writes the RAMB4 or RAMB16 INIT values. The assembler performs a simple textual substitution, so you can change the template so that it writes Verilog instead of VHDL. The filename can't be changed from ROM_form.vhd though. 6. The assembler doesn't correctly handle source files if they have names longer than 8 characters, or if they are in a directory other than the directory containing the assembler, or if they are not in the current directory. I contacted Xilinx about this and they said that it wouldn't be fixed. :( Regards, Allan.Article: 70459
Hi, is it possible to simulate under Modelsim (OEM Altera 5.7e) a testbench (without any timing information) which includes a module with an SDF file? (The SDF file is attached under ---> Simulate --> SDF ----> Add SDF file FILENAME_vhd.sdo + Apply to region u1 (instantiation name of the module in the testbench) I would appreciate your help because Altera seems not to be able to respond to that question. Thank you.Article: 70460
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On a sunny day (Thu, 17 Jun 2004 12:29:34 +0700) it happened Rudolf Usselmann
<russelmann@hotmail.com> wrote in <car9vf$tp5$1@nobel.pacific.net.sg>:
>Stephen Williams wrote:
>
>>
>> Does anybody know if the Xilinx Paralel cable IV cable can
>> be made to work under Linux w/ ISE 6.1i.03? And to make it
>> even more interesting, my Linux is AMD64, will the driver work
>> at all on this system?
>>
>>
>> .... and while we're on the subject, the Linux driver source is
>> itself is pretty basic. Is there programming informatino for the
>> cable that one can use to write custom software to drive the
>> device.
>
>
>Stephen,
>
>not sure if this will help:
>
>I have faced the same problem - not being able to program
>Xilinx Devices using Xilinx Software and Xilinx hardware
>under linux. So I wrote a small dumb program that can take
>a bit stream and directly upload it to an FPGA.
>
>You can find it here: http://www.asics.ws/tools/ljp.c.gz
>
>This works with both Parallel Cable 3 and 4.
>
>Regards,
>rudi
I get:
claim parport: Invalid argument
I am using kernel 2.4.25.
Any ideas? This comes from:
if (ioctl(d, PPCLAIM)) err(-1, "claim parport");
Nevertheless interesting code.
Regards
JP
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Article: 70461Does anybody know how can I disable the automatic optimizer in Quartus II to prevent it from eliminating redundant gates ? (I am trying to implement a delay line using a cascade of inverters, which Quartus removes during compilation since they are logically redundant.) thanks,Article: 70462
Check the latest version KCPSM3, I don't use Verilog but the assembler have a Verilog rom form. Walter. "Allan Herriman" <allan.herriman.hates.spam@ctam.com.au.invalid> a écrit dans le message de news:hgq2d0p1jumlijq9jumml5fks5739g5122@4ax.com... > On 17 Jun 2004 02:39:09 -0700, sanpab@eis.uva.es wrote: > > >Hi all, > > > > I have downloaded a VHDL version of PicoBlaze. I can synthesize it > >with other VHDL modules, my I prefer the use of Verilog, so the only > >way I can use it with them is through EDIF black-box. > > > > Anyway, life could be better if I can use a verilog version of > >PicoBlaze directly. Does anyone know if it exists? > > 1. No, a Verilog version doesn't exist. (If you write one, let me > know!) This is a PITA. > > 2. The latest version of picoblaze uses an NGC file rather than EDIF. > You should probably upgrade. Also, you should use picoblaze2 if you > can; the extra code space helps. > > 3. There shouldn't be any problems synthesising with a black box. > (I'm doing something similar in my current design.) > > 4. There *is* a problem with simulation though: you will need to find > a simulator that can do both languages simultaneously. These tend to > cost a lot. > > 5. Ken Chapman's kcpsm/kcpsm2 assembler uses template files (e.g. > ROM_form.vhd) when it writes the RAMB4 or RAMB16 INIT values. The > assembler performs a simple textual substitution, so you can change > the template so that it writes Verilog instead of VHDL. The filename > can't be changed from ROM_form.vhd though. > > 6. The assembler doesn't correctly handle source files if they have > names longer than 8 characters, or if they are in a directory other > than the directory containing the assembler, or if they are not in the > current directory. > I contacted Xilinx about this and they said that it wouldn't be fixed. > :( > > Regards, > Allan.Article: 70463
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On a sunny day (Thu, 17 Jun 2004 05:39:28 GMT) it happened Philip Freidin
<philip@fliptronics.com> wrote in
<rhb2d0p905uo73cmostsda9j6nf16ogu2v@4ax.com>:
>On Fri, 11 Jun 2004 11:31:18 -0700, Stephen Williams <spamtrap@icarus.com> wrote:
>>
>>Does anybody know if the Xilinx Paralel cable IV cable can
>>be made to work under Linux w/ ISE 6.1i.03? And to make it
>>even more interesting, my Linux is AMD64, will the driver work
>>at all on this system?
>>
>>
>>.... and while we're on the subject, the Linux driver source is
>>itself is pretty basic. Is there programming informatino for the
>>cable that one can use to write custom software to drive the
>>device.
>
>I am not sure how relevant this is, but there is some source code
>and other notes in the FAQ: "Downloading a Bitstream under Linux"
>Here's the URL
>
> http://www.fpga-faq.com/FAQ_Pages/0028_Downloading_a_Bitstream_under_Linux.htm
I have taken that source, added a makefile, and added a way to add the
bit filename in the command line, also added some error checking.
http://ip51cf87c4.direct-adsl.nl/panteltje/download/impact-fl-0.1.tgz
Untar with tar -zxvf impact-fl-0.1.tgz
JP
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Article: 70464The new PicoBlaze User Guide has a short section on using the VHLD PicoBlaze design in a Verilog environment. The Xilinx ISE software includes mixed VHDL/Verilog support. The other option is to instantiate the PicoBlaze design as a black box. Either way, check out page 69 in the following document. PicoBlaze 8-bit Embedded Microcontroller User Guide for Spartan-3, Virtex-II, and Virtex-II Pro http://www.xilinx.com/bvdocs/userguides/ug129.pdf Also, as described on page 72, the KCPSM3 assembler generates a Verilog file describing the instruction ROM, which is useful for simulation. The latest PicoBlaze design is available from the following site. http://www.xilinx.com/picoblaze --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/II/IIE FPGAs http://www.xilinx.com/spartan3 --------------------------------- Spartan-3: Make it Your ASIC <sanpab@eis.uva.es> wrote in message news:d79abcea.0406170139.4845d531@posting.google.com... > Hi all, > > I have downloaded a VHDL version of PicoBlaze. I can synthesize it > with other VHDL modules, my I prefer the use of Verilog, so the only > way I can use it with them is through EDIF black-box. > > Anyway, life could be better if I can use a verilog version of > PicoBlaze directly. Does anyone know if it exists? > > Thanks in advance, Santiago.Article: 70465
On Thu, 17 Jun 2004 10:18:38 -0300, "INS122595" <walter@chasque.apc.org> wrote: >Check the latest version KCPSM3, I don't use Verilog but the assembler have >a Verilog rom form. Hi Walter, do you know where I can download KCPSM3? The Xilinx site requires a user name and password, but I can't find a page that will allow me to register (again). Regards, Allan.Article: 70466
Allan, To register and download Picoblaze3: - Goto http://www.xilinx.com/picoblaze - Click on 'PicoBlaze for Spartan-3, Virtex-II, and Virtex-II Pro FPGAs' - Click on the 'Download' button - Click on 'Create an Account' button Cheers, Shalin- Allan Herriman wrote: > On Thu, 17 Jun 2004 10:18:38 -0300, "INS122595" > <walter@chasque.apc.org> wrote: > > >>Check the latest version KCPSM3, I don't use Verilog but the assembler have >>a Verilog rom form. > > > Hi Walter, do you know where I can download KCPSM3? The Xilinx site > requires a user name and password, but I can't find a page that will > allow me to register (again). > > Regards, > Allan.Article: 70467
On Thu, 17 Jun 2004 07:29:26 -0700, Shalin Sheth <Shalin.Sheth@xilinx.com> wrote: >Allan, > >To register and download Picoblaze3: >- Goto http://www.xilinx.com/picoblaze >- Click on 'PicoBlaze for Spartan-3, Virtex-II, and Virtex-II Pro FPGAs' >- Click on the 'Download' button >- Click on 'Create an Account' button got it, thanks. First impressions: Picoblaze3 has 16 registers vs 32 for Picoblaze2. Some bugs in kcpsm2.exe are also present in kcpsm3.exe (see webcases #533179 and #533195). Kcpsm3.exe can't compile code that compiles with kcpsm2.exe. (This violates one of the cardinal rules of EDA - don't break existing designs.) The problem seems to be that kcpsm3 doesn't accept register names of the form 's00', which is the only form that kcpsm2 accepts. Regards, Allan.Article: 70468
Use the syn_multstyle attribute. From the Synplify reference manual:
-------------
VHDL Syntax and Example
attribute syn_multstyle of object : object_type is "block_mult | logic |
lpm_mult" ;
library ieee;
use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
entity onereg is port (
r : out std_logic_vector(15 downto 0);
en: in std_logic;
a : in std_logic_vector(7 downto 0);
b : in std_logic_vector(7 downto 0);
c : in std_logic_vector(15 downto 0)
);
end onereg;
architecture beh of onereg is
signal temp : std_logic_vector(15 downto 0);
attribute syn_multstyle : string;
attribute syn_multstyle of temp : signal is "logic";
begin
temp <= a * b;
r <= temp when en='1' else c;
end beh;
"Ravi Sankar K." <sankarkonidena@rediffmail.com> wrote in message
news:eb4c4b53.0406162308.18f5e5f@posting.google.com...
> I 've generated 18x18 block based multipliers using Synplify_pro tool.
> Now I want to generate logic based multipliers( which dont use blocks
> ). I 've no
> knowledge on the contsraint files used to generate multipliers using
> synplify_pro. Can any one let me know on how I can generate logic
> based multipliers.
>
> The following is the .prj file used to generate 10x33 block based
> multiplier.
[ remainder omitted ]
Article: 70469Just to clarify Rickman's "Two-clock-cycle thing": Xilinx BlockRAMs need ONE clock to perform any operation, be it a read or a write. As a bonus, the write operation also performs a read operation on the same location, showing either the old or the new data (user option). And this is all on one port. You can obviously use the other port independently from the first. The one thing you cannot do is an asynchronous read without a clock edge. If anybody has any questions about Xilinx BlockRAMs, I am more than happy to explain. Peter Alfke, Xilinx Applications > From: rickman <spamgoeshere4@yahoo.com> > Reply-To: john@bluepal.net > Newsgroups: comp.arch.fpga > Date: Thu, 17 Jun 2004 02:14:36 -0400 > Subject: Re: RAM in Altera EABs and Xilinx Block Rams > > John_H wrote: >> >> Quoting Peter's text from below, "When one port performs a write operation, >> the other port must not write into the same location, unless both ports >> write identical data." >> >> For a one-port dedicated read and one-port dedicated write configuration >> that I *believe* rickman is pursuing, a little trick could be used: feed >> the data to *both* write ports and enable the write to the nomally read-only >> port when a RdAddr==WrAddr compare is valid. This increases the effective >> address setup time but gives the desired WRITE_FIRST functionality without >> increasing the Clk-to-out time. > > To implement a stack you don't normally need separate read and write > ports since you only do one thing at a time. The Xilinx block RAMs > can't do a read in less than two clock cycles which gets in the way of a > stack. So I would need to use a separate register to hold the top of > stack and refresh that on POPs from the RAM using a separate read port > with a separate address. In that case there is never the problem of > simulaneous reads and writes to the same address because you only ever > do one thing at a time. > > I have not thought about my program or data memory. I may really be > hosed there and have to abandon the one clock cycle instruction idea. I > guess I could use a two up clock or something similar. I belive the > Spartan 3 block rams are fast enough that I likely won't have a speed > issue even with a 2x clock. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 70470
Jan Panteltje <pNaonStpealmtje@yahoo.com> wrote: : >rudi : I get: : claim parport: Invalid argument : I am using kernel 2.4.25. : Any ideas? This comes from: : if (ioctl(d, PPCLAIM)) err(-1, "claim parport"); : Nevertheless interesting code. : Regards Do you have the ppdev kernel module loaded? If no, do it. If yes, do you have any other device claiming the papalle port loaded (e.g. a parallel port CDROM or such). If yes, unload. Try again. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 70471
I have a microscop. I had to resolder the whole side where there are M1, M2 and it's look quite ugly now, but I will retry. Nial Stewart wrote: > "Thierry Gschwind" <thierryg@ee.ethz.ch> wrote in message > news:40ce11d3$1@pfaff2.ethz.ch... > > >>The guys who designed the hardware hardwired M2 and M1 to ground, it's >>nearly not possible to change them. > > > > Thierry, > > If you're using a QFP (which I presume you are if you've soldered > this down yourself) it's not impossible to lift a pin, even with > pin pitches of 0.5mm. > > You'll need a stereo microscope or other good maginifer, and a > scalpel with a new blade. > > Prepare the area with pleanty of flux. Position the scalpel tip > between the pin in question and one of its neighbours. Put > pleanty of solder on the iron and heat the pin in question, > gently levering against the neighbour. You should be able to > prise it up, but be careful with it, don't bend it up and down > too many times or it'll snap off. > > Clean up the adjacent pins with solder-wick and re-do and than > need tidied up. > > You can then get a flying wire on the pin you've lifted, but be > careful with it, as I said above it's not mechanically strong > and you don't want to overheat it. > > > Not that I've ever had to do this of course ;-) > > > Nial. > > ------------------------------------------------ > Nial Stewart Developments Ltd > FPGA and High Speed Digital Design > Cyclone Based 'Easy PCI' proto board > www.nialstewartdevelopments.co.uk > >Article: 70472
Hello Looking for vhdl code that can get data from the computer's parallel port. Can't find one that helps so far. I have the digilent D2 board with the xc2s200/pq208. It has a EPP. Is that different from a standard parallel port ? Thanks RayArticle: 70473
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On a sunny day (Thu, 17 Jun 2004 16:44:17 +0000 (UTC)) it happened Uwe Bonnes
<bon@elektron.ikp.physik.tu-darmstadt.de> wrote in
<cashp1$6vi$1@news.tu-darmstadt.de>:
>Do you have the ppdev kernel module loaded? If no, do it. If yes, do you
>have any other device claiming the papalle port loaded (e.g. a parallel
>port CDROM or such). If yes, unload. Try again.
>
>Bye
Did some testing, there is no module named ppdev.
panteltje:~# lsmod | grep p
parport_pc 14192 1 (autoclean)
lp 6592 0 (autoclean)
parport 24992 1 (autoclean) [parport_pc lp]
Removing and insmodding any of these does make no difference, except now I get:
open parport: No such device
Of cause I have /dev/parport0 etc...
Maybe I should not be using /dev/parport?
JP
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Article: 70474Hi all, I have installed ISE Foundation (6.2.03) and tried to generate an EDIF file from a Verilog file. I remember I could do it a few years ago with 4.x version (not sure). I need to install something special? Anyway, what happens if the design has parameters? The EDIF file allow it? Thanks in advance, Santiago.
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