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I've got a NIOS system running but have questions about memory usage (RAM). I've got 2 files that contain the issues. The 1st is the memory map (.mn) generated by the compiler and the 2nd is a memory dump captured using hyperterm. Before starting the CPU and capturing the memory dump, I filled RAM with AAAAs. The two mysteries (1) The map indicates we have a total ram of 8192 (I am using all decimal now) of which 5232 (about 63%) is allocated. That leaves about 2960 available. Included in the 5232 is a block of 1052 associated with malloc. We suspect this is used for local variable storage that exceeds the stack BUT what determines this block size? Looking at our code, we cannot see where we need anywhere near this amount of RAM for local variable storage. How we make it smaller? --- ouput of copmiler map file 00040000 A na_ext_ram 00040000 A nasys_usersocket_1 00040000 A nasys_vector_table 00040100 A _nasys_data_destination 00040100 A nasys_data_mem 00040100 A nasys_vector_table_end 00040100 D _data 00040100 D nS 00040104 D x 00040124 D y ... Deleted variable listing for clarity 00040abc D testStr 00040ad8 D RAMLimit 00040adc d inited.0 00040ae0 d inited.1 00040ae4 d impure_data 00040dd0 D _impure_ptr 00040dd4 D __mb_cur_max 00040dd8 d lc_ctype.0 00040de0 d last_lc_ctype.1 00040de8 D __malloc_av_ 000411f0 D __malloc_trim_threshold 000411f4 D __malloc_top_pad 000411f8 D __malloc_sbrk_base 000411fc D __malloc_max_sbrked_mem 00041200 D __malloc_max_total_mem 00041204 D __malloc_current_mallinfo 0004122c A __bss_start 0004122c A _nasys_uninitialized_storage 0004122c B _bss 0004122c D _edata 0004122c D _nasys_data_destination_end 0004122c b xAvg.48 00041234 b yAvg.49 0004123c b sAvg.50 00041244 B _nr_userisrtable 00041444 B atexit_func 00041448 B _main_return 0004144c B cwpUnderflowG 0004146c B errno 00041470 A _end 00041470 A _nasys_uninitialized_storage_end 00042000 A na_ext_ram_end 00042000 A nasys_data_mem_end 00042000 A nasys_stack_top ---------------- (2) When I run the program and dump the RAM, you can see that data (non AA values) occur through the first 5232 locations. Then there are some AA's followed by a large section of RAM with non AA's. In fact, it appears something is using another 2004 of RAM out of the available 2960. This wipes out our growth capability. What is using up this RAM and how do we prevent it? Memory Dump------------------- 040000: 3641 000C 392F 000C 398A 000C 3641 000C 040010: 3641 000C 3641 000C 3641 000C 3641 000C 040020: 3641 000C 3641 000C 3641 000C 3641 000C RAM contains mostly 0000s as expected. 040D10: 0000 0000 0000 0000 0000 0000 0AE4 0004 040D20: 0000 0000 0000 0000 0000 0000 0009 0001 040D30: 0000 0000 0000 0000 0000 0000 0D20 0004 040D40: 61FD 000C 621E 000C 624B 000C 6273 000C Looks like this RAM contains the address of itself Probably a Malloc event. 040DF0: 0DE8 0004 0DE8 0004 0DF0 0004 0DF0 0004 040E00: 0DF8 0004 0DF8 0004 0E00 0004 0E00 0004 040E10: 0E08 0004 0E08 0004 0E10 0004 0E10 0004 040E20: 0E18 0004 0E18 0004 0E20 0004 0E20 0004 This pattern continues 0411C0: 11B8 0004 11B8 0004 11C0 0004 11C0 0004 0411D0: 11C8 0004 11C8 0004 11D0 0004 11D0 0004 0411E0: 11D8 0004 11D8 0004 11E0 0004 11E0 0004 Here starts a lot of Zeros.. 0411F0: 0000 0002 0000 0000 FFFF FFFF 0000 0000 041200: 0000 0000 0000 0000 0000 0000 0000 0000 041210: 0000 0000 0000 0000 0000 0000 0000 0000 Continuing till 041440: 0000 0000 0000 0000 20FB 0008 0000 0000 041450: 0000 0000 0000 0000 0000 0000 0000 0000 041460: 0000 0000 0000 0000 0000 0000 0000 0000 An then untouched memory. 041470: AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA 041480: AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA 041490: AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA 0414A0: AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA Till this which looks like stack usage 041780: AAAA AAAA 4141 4141 0041 0000 0003 0000 041790: FFFF FFFF FFFF FFFF 0000 0000 0031 0000 0417A0: 0300 0004 5C75 000C FF20 0000 0000 0000 0417B0: 0000 0000 0000 0000 56EC 000C AAAA AAAA 0417C0: AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA Up to the end of RAM or the Start of Stack. 041F40: 6DB0 3FE1 0000 0000 9800 40EA 5CBC 77C4 041F50: D662 3FEA 0000 0000 79B0 40F4 AAAA AAAA 041F60: AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA 041F70: AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA 041F80: AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA 041F90: AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA 041FA0: AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA 041FB0: AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA 041FC0: AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA 041FD0: AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA 041FE0: AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA 041FF0: AAAA AAAA AAAA AAAA AAAA AAAA AAAA 0862 --------------------------------Article: 70076
Hi Matthew, Do you have the latest service pack? Have a look at answer 19248. Cheers, Syms.Article: 70077
George, The Nios I is a Harvard architecture meaning it has a separate Instruction and Data bus. You need to connect a memory or bus to the instruction bus only if the cpu will get/load instructions from that memory. If not then don't waste the logic. Ken "George" <george.martin@att.net> wrote in message news:e9d879fa.0406011041.29676c1a@posting.google.com... > Do you know how to do that. I added a 2nd TriState Bus and connected > that to the CPU Data Master Bus. The 1st TriSatate bus is connected > to the CPU Instruction Master Bus. > > Is this the best (correct) way?? > > Thanks > GeorgeArticle: 70078
Computer hardware enthusiast Johan De Gelas of aceshardware compared performance of seven top PC MPUs on Quartus-II Web Edition place and route task. Johan is a real professional when it comes to benchmarking computers. His results can be safely relied on. Probably the article would be of interest for participants of comp.arch.fpga http://www.aceshardware.com/read.jsp?id=65000307 Johan recognizes that the test design was uncharacteristically small by modern FPGA's standards. He is willing to improve the benchmark. Please, post you proposals for improvements in the aceshardware message board. http://www.aceshardware.com/forum Just keep in mind that A. Benchmarks have to utilize free or donated tools and free or donated design files. B. Johan is not logic designer. Try to make benchmarks setup easier for him. He has more than enough head ashes with the hardware he is testing, doesn't have to mess with software as well. Regards, Michael P.S. Many thank to Zhao Ming, who supplied radix-4 CFFT core that served as the basis for the benchmark. And of course to Altera Corporation for free Quartus tools.Article: 70079
I've downloaded and attempted to run both the solaris and windows executables of RASP that are downloadable from http://ballade.cs.ucla.edu/software_release/rasp/htdocs/ In both cases, the PLAmap executable continually seg faults. Has anybody else had this problem? My other option for optaining PLAmap is by acquiring SIS from UC Berkeley and then compiling the code for RASP ... but I've also been unable to compile the code for SIS that is provided by Berkeley. Any help/advice would be appreciated. -MarkArticle: 70080
> > You can choose whether the memory banks are connected to the instruction > > master and/or the data master. It sounds like there is a limitation in the > > Nios II regarding the width of instruction addresses (probably so that an > > absolute call or jump can fit within a single instruction), but that should > > not affect the data access (presumably this range is mostly data?). > > Deselect the instruction master connection from the data banks, and see if > > that helps. > > > Do you know how to do that. I added a 2nd TriState Bus and connected > that to the CPU Data Master Bus. The 1st TriSatate bus is connected > to the CPU Instruction Master Bus. > > Is this the best (correct) way?? > > Thanks > George Hi George, A colleague replied to your inquiry over on the Nios forum website. However just to clarify the above: Each tri-state master will generate a new tri-state bus coming out of your SOPC Builder system. Depending on how your board is designed this probably isn't what you want (you probably should keep the bus setup similar, if not identical, to your Nios I system). As alluded to above, the limitation is in fact in place so that a Nios II call instruction will always fall within a 'legal' range (256MBytes of address space). So for your system I would recommend the following: 1. Tie the Nios II CPU instruction master only to those memories that you wish to have code in. 2. Make sure that the address span between all peripherals that you read instructions out of falls into that 256MB range. This will probably mean altering the base address of your memories to group all instruction memories close together. If the above is not an acceptable solution, feel free to send me an email and I can give you some additional ideas. Regards, Jesse Kempa Altera Corp. jkempa at altera dot comArticle: 70081
That is excellent. Funny, I was just reading Toms Hardware's latest test of the 939 pin Athlon64 thinking that none of these benchmarks really relate stuff I care about and how to get benchmarks of P&R. Michael, thank you soo much! Indeed, Quartus II is really the only app I run that takes enough time to be annoying; even my toy designs take more like 5 minutes to complete. (Games aren't even that CPU limited anymore). Ace's result are a bit surprising. Ignoring Intel, more memory bandwidth makes nearly no difference and twice the L2 doesn't make up for 9% frequency loss, so it looks like frequency is the factor to optimize for this application (ie., the 3700+ beats the 3800+). Oh, and no surprise, AMD wins on price/preformance big time. Tommy Michael S wrote: > Computer hardware enthusiast Johan De Gelas of aceshardware compared > performance of seven top PC MPUs on Quartus-II Web Edition place and > route task. > Johan is a real professional when it comes to benchmarking computers. > His results can be safely relied on. > > Probably the article would be of interest for participants of > comp.arch.fpga > > http://www.aceshardware.com/read.jsp?id=65000307 > > Johan recognizes that the test design was uncharacteristically small > by modern FPGA's standards. He is willing to improve the benchmark. > Please, post you proposals for improvements in the aceshardware > message board. > > http://www.aceshardware.com/forum > > Just keep in mind that > A. Benchmarks have to utilize free or donated tools and free or > donated design files. > B. Johan is not logic designer. Try to make benchmarks setup easier > for him. He has more than enough head ashes with the hardware he is > testing, doesn't have to mess with software as well. > > Regards, > Michael > > P.S. > Many thank to Zhao Ming, who supplied radix-4 CFFT core that served as > the basis for the benchmark. > And of course to Altera Corporation for free Quartus tools.Article: 70082
hi, i m still in planning phase of my design. i was just looking at xilinx and altera devices. Xilinx provides tri-state buffers as well as tri-state lines whereas altera doesn't and suggests to use muxs insteed of tri-state buffers. Now assume that i have a bus in my design where lots of drivers are there n driving bus through tri-state buffers. I am just wondering what will happen if i implement this design in altera. I'll have to take all drivers at one place, put a mux and re-route them to all sink. won't it affect timing considerably. considering it xilinx becomes obvious choice because of tri-state buffers n lines. Anyone has any other opinion or observation on the topic??Article: 70083
Hi, mike_treseler@comcast.net (Mike Treseler) wrote > usenet_10@stanka-web.de (Thomas Stanka) wrote > > I had a design with asynchronous inputs. I inspected the rtl code to > > ensure, the asynch inputs would only be used if they are stable with > > respect to the specification. Unfortunately I missed a line, where an > > asynchronous input release an synchron reset. The synthesis generated > > a race condition which lead to disfunction of the design. After > > founding the problem it was very easy to see the failure in the > > netlist. > > You found the source of one race condition. > There are no doubt others that will introduce themselves > over time, temperature, state and input variations. :). Indeed there was a possible second race condition for a very unusual input constellation, but I ensured, that there were no other race conditions by inspection of every path from asynchronous inputs to registers. Even over temperature and voltage. This job was very nasty and seems to me very errorprone when having more than about 10 pathes to inspect. So I wonder whether there exist allready tools helping you doing this job. > > I don't like the idea > > to spend hours and days inspecting netlists for asynchronous inputs I > > use to ensure, that this failure won't happen a second time. > > I don't either. Consider doing whatever is necessary > synchronize all the inputs to the system clock. Impossible for this design due to hard area constraints. > > but I have some designs with hard area constraints and > > other designs with timing constraints that didn't permit the use of > > registers for all inputs. > > That is an engineering problem. > There are always alternatives. Tell me your employer, it seems very good to have a job, where an fpga designer has the possibillity to deny projects with hard constraints *g*. Beside the hard area criteria, when a design had to fit into an given fpga with no possibillity to get an bigger fpga to place the neccessary FF to synchronise every input, there are other designs with timing criteria, that didn't allow to synchronise by inserting two ff between two clock domains. Whenever your designs allows you no clock cycle to respond on requests, you have to deal with asynchronity by using other technics like handshake (if possible). bye ThomasArticle: 70084
>I used to use a tool like this when I was at Agilent. It was written >in-house (Hi Mark!). [Big snip of feature list.] This seems like a great candidate for a FPGA related open-source project. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 70085
On Wed, 02 Jun 2004 02:13:35 -0500, hmurray@suespammers.org (Hal Murray) wrote: >>I used to use a tool like this when I was at Agilent. It was written >>in-house (Hi Mark!). > >[Big snip of feature list.] > >This seems like a great candidate for a FPGA related open-source project. Agreed. Allan.Article: 70086
Hi, I have several FPGAs in my design and I want the first FPGA to feed the other FPGAs with its master clock. The first FPGA use a DCM to reshape an input clock and get its master clock. I want the three FPGAs to have a phase-aligned clock. I just don't know how to do it since the master clock of the first FPGA which is the output clk0 of the DCM has to go through an output buffer to access a pin to be distributed to the others FPGAs but then the clock would have a delay compare to clk0. Is someone can help me with that ? Thanks. Christophe.Article: 70087
Hi Chris, Basically you need a controllable skew on your clock domain distributed over the PCB, right? What is the master clock frequency and where is it derived from? I might have a solution based on this info. Regards, Luc On 2 Jun 2004 04:27:18 -0700, ccoutand@hotmail.com (chris) wrote: >Hi, > >I have several FPGAs in my design and I want the first FPGA to feed >the other FPGAs with its master clock. The first FPGA use a DCM to >reshape an input clock and get its master clock. >I want the three FPGAs to have a phase-aligned clock. >I just don't know how to do it since the master clock of the first >FPGA which is the output clk0 of the DCM has to go through an output >buffer to access a pin to be distributed to the others FPGAs but then >the clock would have a delay compare to clk0. >Is someone can help me with that ? > >Thanks. Christophe.Article: 70088
Hello, Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> wrote: > By the time all the feature creep had ended, the tool we used checked > for: [snip] Thanks for this list. I try to setup a script helping me to check for this list. I will post, if the script is running stable. > The majority of our problems were due to cross-clock domain paths > inside a single FPGA, but the same issues could apply to signals > coming from pins. > Prior to the creation of this tool, I estimated about half the debug > time on some projects was due to improperly handled cross clock domain > signals. Many of the bugs were in "proven" legacy code that had been > "working fine" for years. > There weren't that many bugs, it's just that they took a long time to > find compared with straighforward functional bugs. I agree with you that it is very hard and long lasting to debug errors regarding race conditions :). Especially if you can't find the source of the problems by RTL inspection. bye ThomasArticle: 70089
ccoutand@hotmail.com (chris) wrote in news:33923a80.0406020327.20fde6f3 @posting.google.com: > Hi, > > I have several FPGAs in my design and I want the first FPGA to feed > the other FPGAs with its master clock. The first FPGA use a DCM to > reshape an input clock and get its master clock. > I want the three FPGAs to have a phase-aligned clock. > I just don't know how to do it since the master clock of the first > FPGA which is the output clk0 of the DCM has to go through an output > buffer to access a pin to be distributed to the others FPGAs but then > the clock would have a delay compare to clk0. > Is someone can help me with that ? > > Thanks. Christophe. Can't you just use two DCMs as shown in the FPGA datasheet to remove the skew caused by the buffer and PCB delays? -- ---------------------------------------------------------------- Dr. Dave Van den Bout XESS Corp. PO Box 33091 Raleigh NC 27636 Phn: (919) 363-4695 Fax: (801) 749-6501 devb@xess.com http://www.xess.comArticle: 70090
I am a novoice in FPGAs. My application needs an a/d converter on a FPGA. Is it possible to design an a/d converter on FPGA. I am using Altera Nios FPGA. Any info is appreciated. Thank you, SrikanthArticle: 70091
You could make a sigma delta ADC using just the FPGA and a comparator, and a few
r's and c's. If you use an FPGA with LVDS pin pairs, you might even be able to
use one of the LVDS pairs as the comparator. Depending on your required sample
rate and resolution, this may or may not be an acceptable hack. A better
solution for low rate might be to use either an external sigma-delta modulator
or one of the serial ADCs for a minimal added cost system.
Srikanth Anumalla wrote:
> I am a novoice in FPGAs. My application needs an a/d converter on a FPGA. Is
> it possible to design an a/d converter on FPGA. I am using Altera Nios FPGA.
> Any info is appreciated.
>
> Thank you,
> Srikanth
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 70092digari wrote: > > hi, > i m still in planning phase of my design. i was just looking at xilinx > and altera devices. Xilinx provides tri-state buffers as well as > tri-state lines whereas altera doesn't and suggests to use muxs > insteed of tri-state buffers. > Now assume that i have a bus in my design where lots of drivers are > there n driving bus through tri-state buffers. I am just wondering > what will happen if i implement this design in altera. I'll have to > take all drivers at one place, put a mux and re-route them to all > sink. won't it affect timing considerably. > considering it xilinx becomes obvious choice because of tri-state > buffers n lines. Anyone has any other opinion or observation on the > topic?? The older Xilinx chips have lots of tristate buffers. But they have been phasing them out for the last two generations and have completed that task with the Spartan 3 chips. The internal tristate buffer is dead! BTW, if you think routing signals to a common mux is slow, you should check the timing numbers on the tbufs driving long lines which then run around the chip. If you do a really good job of placement, you can minimize the speed penalty. But tristate buffers will *always* be slow due to the nature of a passive pullup. Altera has a cascade backbone inside their LABs that will AND the outputs of the LUTs at a very high speed. This can implement a very wide AND-OR gate for wide muxes at high speed. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 70093
Yup, Tristate is actually slower. The tristate buffers in Virtex and all subsequent families are in fact separate bidirectional logic structures that simulate the behavior of a tristate bus. http://www.xilinx.com/bvdocs/appnotes/xapp466.pdf see page 11: Spartan 3 is faster and less expensive without any tristate elements at all! Austin rickman wrote: > digari wrote: > >>hi, >>i m still in planning phase of my design. i was just looking at xilinx >>and altera devices. Xilinx provides tri-state buffers as well as >>tri-state lines whereas altera doesn't and suggests to use muxs >>insteed of tri-state buffers. >>Now assume that i have a bus in my design where lots of drivers are >>there n driving bus through tri-state buffers. I am just wondering >>what will happen if i implement this design in altera. I'll have to >>take all drivers at one place, put a mux and re-route them to all >>sink. won't it affect timing considerably. >>considering it xilinx becomes obvious choice because of tri-state >>buffers n lines. Anyone has any other opinion or observation on the >>topic?? > > > The older Xilinx chips have lots of tristate buffers. But they have > been phasing them out for the last two generations and have completed > that task with the Spartan 3 chips. The internal tristate buffer is > dead! > > BTW, if you think routing signals to a common mux is slow, you should > check the timing numbers on the tbufs driving long lines which then run > around the chip. If you do a really good job of placement, you can > minimize the speed penalty. But tristate buffers will *always* be slow > due to the nature of a passive pullup. > > Altera has a cascade backbone inside their LABs that will AND the > outputs of the LUTs at a very high speed. This can implement a very > wide AND-OR gate for wide muxes at high speed. >Article: 70094
usenet_10@stanka-web.de (Thomas Stanka) wrote in message news:<ef424d2c.0406020556.15ead43d@posting.google.com>... > Thanks for this list. I try to setup a script helping me to check for > this list. > I will post, if the script is running stable. Yes, thanks Allan, for the excellent posting. I like the idea of having a way to verify the "known-good" designs that are not well documented. I would note that for *new* designs, all of these defects can be prevented with the right set of design rules. -- Mike TreselerArticle: 70095
You may use a LFSR register. See it at http://www.xilinx.com/bvdocs/appnotes/xapp052.pdf Cheers.Article: 70096
Srikanth Anumalla wrote: > I am a novoice in FPGAs. My application needs an a/d converter on a FPGA. Is > it possible to design an a/d converter on FPGA. I am using Altera Nios FPGA. > Any info is appreciated. It all depends on the resolution/speed you need. Tracking ADCs, which use a DAC and comparitor, are simple. The DAC can be single pin PWM, or Rate Multiplier - for better performance, external Vcc/Vref, and buffer all help. Gnd and Vcc lines on FPGAs are NOT low noise analog nodes ! Sigma-Delta ADCs are also simple, but need an integrator/Vref/Slice for best performance. If it is a closed-loop system, where you are more interested in a balance-point than absolute precision/linearity, then the very simple single slope RC ramp can be used. -jgArticle: 70097
I'm working on a design with a Xilinx XC95XL series CPLD. The inputs would be coming from a system with a 5 V (possibly higher, I don't have the exact number yet) output. I need 3.3 V outputs, so using the separate I/O power supply is not a good solution. As a novice engineer, I have a few ideas, but don't know which is best. Is there a problem with using a simple resistor divider to create lower voltages? Should I have to use a separate level shifter IC instead to change the 5 V signals to 3.3 V? Thanks, Matt CohenArticle: 70098
Matt Cohen wrote: > > I'm working on a design with a Xilinx XC95XL series CPLD. The inputs > would be coming from a system with a 5 V (possibly higher, I don't > have the exact number yet) output. I need 3.3 V outputs, so using the > separate I/O power supply is not a good solution. As a novice > engineer, I have a few ideas, but don't know which is best. Is there > a problem with using a simple resistor divider to create lower > voltages? Should I have to use a separate level shifter IC instead to > change the 5 V signals to 3.3 V? Thanks, > Matt Cohen It depends on the details of the chips you are driving and the CPLD. Most 3.3 volt chips can tolerate 5 volt signals on their inputs. If your 5 volt signals are actually TTL level driven, the thresholds will match well. If they are CMOS level driven then they will likely work as well, but heavy loading can cause the low state to rise above the acceptable 0.4 volt on the input. I doubt that you will have heavy loads on your inputs. The output of 3.3 volt logic is what you say you need. So if you power the IOs from 3.3 volts and use a 5 volt tolerant CPLD, you should be in good shape. If you really want to use a 5 volt supply on the CPLD, then the way you interface to the output loads depends on the loads. If the load devices are not 5 volt tolerant, then you will need to add a series resistor or even a divider as you say. But if they are 5 volt tolerant, then you need do nothing. Check the data sheet on those devices. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 70099
a simple series resistor to limit the input current is sufficient for 5v
signals to 3.3v inputs assuming the 3.3v inputs are NOT already 5v
tolerant (if they are, then you don't even need the resistor).
Matt Cohen wrote:
> I'm working on a design with a Xilinx XC95XL series CPLD. The inputs
> would be coming from a system with a 5 V (possibly higher, I don't
> have the exact number yet) output. I need 3.3 V outputs, so using the
> separate I/O power supply is not a good solution. As a novice
> engineer, I have a few ideas, but don't know which is best. Is there
> a problem with using a simple resistor divider to create lower
> voltages? Should I have to use a separate level shifter IC instead to
> change the 5 V signals to 3.3 V? Thanks,
> Matt Cohen
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
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