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Messages from 70150

Article: 70150
Subject: Re: VHDL test bench in Quartus
From: rickman <spamgoeshere4@yahoo.com>
Date: Sat, 05 Jun 2004 11:11:56 -0400
Links: << >>  << T >>  << A >>
Pratip Mukherjee wrote:
> 
> rickman <spamgoeshere4@yahoo.com> wrote in
> news:40C0DF60.2BF1AA9A@yahoo.com:
> > A test bench is not just a static waveform generator, it can be an
> > interactive environment simulator.  I can write code to model an
> > external memory or MCU bus cycles or any other interface.  As my
> > design progresses it can take a lot less work to keep a testbench up
> > to date than it would to redo waveforms.
> >
> > Maybe it is just a personal preference, but I find a VHDL testbench to
> > be the best way of testing a design I have found.
> >
> 
> If the design has some Altera specific MegaFunction, then don't you have
> to have another version of the same file using generic VHDL construct?
> Can Xilinx/ModelSim be made to understand Altera specific constructs? I
> am talking about the free version of ModelSim which comes with WebPack.
> Thanks.

What MegaFunction are you thinking that I would use?  I have found that
the block rams can be described in generic VHDL.  I expect that any
other feature would be device specific.  One that I will likely end up
using is the cascade chain in the Altera parts, they are useful in wide
input muxes.  I believe I asked about how to get these from generic code
and did not get a good answer from Altera.  So I may have to do as you
are saying and use a conditional depending on the target.  I started to
do that with the memory before I found that both environments worked
well with generic code.  Its not hard to do.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 70151
Subject: Re: IDE/ATA _device_ core availablility
From: "Holger Baxmann" <holger@bitwind.org>
Date: Sat, 5 Jun 2004 19:03:56 +0200
Links: << >>  << T >>  << A >>
> > Reason: connecting a FPGA to an [PC] the standard USB-to-IDE or direct
> > IDE interface way.
>
> I've never seen the VHDL for a device-side IDE interface, but it
> shouldn't be too hard to do at least a PIO-mode interface.  All you need
> to do is respond to reads and writes to two banks of eight registers each
> and generate the appropriate actions (maybe just read and write sector
> commands).  I recommend looking at an early version of the ATA spec
> (before they got to several hundred pages) to see how the interface
> works.  The one I've used is "ATA Interface Reference Manual" published
> by Seagate back in 1993 (stored at
> http://www1.vobis.de/bbs/firmen/seagate/manual/atarevc.pdf)
>

Thank you, Dave

I will do my very best, but I need a harddisk either so the alternative is
to be the real 'man-in-the-middle'.

> Once you get a design roughed out, you could combine it in an FPGA or
> simulator with the IDE interface core we have at www.xess.com.  That
> would show you if your device-side interface is alive before subjecting
> it to a real-world command stream from a PC IDE port.
>

Hopefully my board is arriving soon, there it could be on CD, does it?

bax
PS: And thanks, Vobis ;-)



Article: 70152
Subject: parameter feature of AHDL in Xilinx
From: "Charles Zheng" <czheng@ieee.org>
Date: Sat, 05 Jun 2004 18:56:30 GMT
Links: << >>  << T >>  << A >>
In altera's tool, if a .tdf file uses the parameter for that component, and
if you instantiate the component in the schematic, you can change the
parameter by right clicking on the symbol.  I wonder if there is similar
feature with VHDL file in Xilinx ISE's ECS tool.  That is a convenient
feature because you can instantiate as many time as you want, and just
change the parameter in the schematic to customize each one of them.

Thanks,
Charles



Article: 70153
Subject: Re: USB OTG high speed
From: "Antti Lukats" <antti@case2000.com>
Date: Sat, 5 Jun 2004 15:27:06 -0700
Links: << >>  << T >>  << A >>
"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:40BF9374.B3B5A244@yahoo.com...
> I see where Atmel has announced a USB OTG full speed controller chip.
> It looks interesting.  But I would prefer a high speed device.  Anyone
> know of such a chip?  Or I can use a core if it is not too large.  So
> far I have not found anything that will implement OTG and high speed.
>
> Rick "rickman" Collins

Hi Rick,

the philips HS chips is not available at least for normal mortals. It realy
looks like real nice part but I guess only available in some very small BGS
like package :(

there are a few HS OTG PHY chips available, (at least 3 known to us) and
some companies have also working IP Cores (OTG HS).
www.asics.ws
they have a OTG eval board for demonstration of the OTG IP Core that
supports OTG PHY solutions from 5 different manufacturers.

Antti



Article: 70154
Subject: Quick question
From: "Jason Berringer" <look_at_bottom_of@email.com>
Date: Sat, 5 Jun 2004 18:36:11 -0400
Links: << >>  << T >>  << A >>
Hello all,

I'm curious to know the benefits of using third party synthesis tools. For
example how much better are synthesis tools like Synplicity or Synplify, etc
over just using the vendor tools ISE Webpack. Do you only experience some
significant gains with large designs or does it not really matter. I've been
using the Xilins synthesis tools for quite a while and have never had a
problem. I will be the first to admit that my largest designs have only
taken up about 60% of a XC2S150 so I'm not dealing with mosterous designs.

Anyn commetns are appreciated.

Jason

jberringer@remove.sympatico.remove.ca

remove the removes to reply to me personally.



Article: 70155
Subject: Variable Frequency and Voltage Supply
From: loudgary@yahoo.com.hk (GaRY)
Date: 6 Jun 2004 05:37:54 -0700
Links: << >>  << T >>  << A >>
Hi,

I am very new in using FPGA. I wanna know is there any design of
information in FPGA use variable clock and variable voltage, coz I
want to find ways to reduce power when using FPGA.
Thx for the help.

GaRY

Article: 70156
Subject: Re: Three-phase PWM generator in VHDL
From: "Mike" <her@her.com>
Date: Sun, 06 Jun 2004 23:18:40 GMT
Links: << >>  << T >>  << A >>
I am working with one now. You have to be clear in your requirements, such
as
1) Short circuit detection/shutdown
2) Dead Time
3) Cycle reference (usualy 8 khz)
4) Typically the Phase A, B and C signals have an inverse.
5) Are you using a gate drive (ie IGBT)?
6) Motors produce lotsa noise, any feedback to prevent motor damage (see
item 1) should contain a debounce to validate logic levels.

fabbl



"Giuseppe³" <miaooaim.REMOVETHIS@tiscali.it> wrote in message
news:2i829fFkbfktU1@uni-berlin.de...
> Hello,
> Is there anybody, that know where I can find a free source code to
generate
> a three-phase PWM to drive an AC motor with the SpartanII Fpga?
>
> Or I have to write myself :-) ?
>
> Thank you for your attention
> -- 
> --
> Ciao
> Giuseppe
>
>
>



Article: 70157
Subject: Where is my Digital Up Convertor in Logicore ??!! :)
From: djb@global.net.mt (David Joseph Bonnici)
Date: 6 Jun 2004 19:58:28 -0700
Links: << >>  << T >>  << A >>
I have been on the xilinx website and they say that they have included
the Digital Up Convertor in ISE package. I have opened Coregen but I
CANNOT FIND IT. Perhaps I am getting cross eyed. I tried a file search
on the installation path C:\xilinx and there is not even the duc.pdf
I know that I can build one myself from the other blocks, but I would
like to use it. (to be less error prone, designs use less slices, less
code, less time)
Is there someone that has the same problems that I have?

Apart from that: Can someone explain me what is "Bit convergent
rounding" with a practical example of numbers?

David

Article: 70158
Subject: CFP: Workshop on Application Specific Processors (WASP 2004)
From: "Scott Mahlke" <mahlke@eecs.umich.edu>
Date: Mon, 7 Jun 2004 00:49:08 -0400
Links: << >>  << T >>  << A >>
**************************************************************
Call For Papers
3rd Workshop on Application Specific Processors (WASP 2004)

Held in conjunction with the International Conference on
Hardware/Software Codesign and System Synthesis, (CODES+ISSS),
September 7, 2004, Stockholm, Sweden

Abstract due:  July 1, 2004
Submission due:  July 8, 2004
Acceptance notification:  August 1, 2004
Final version due:  August 15, 2004

Website: http://dna.ucsd.edu/wasp04

************************************************************

The dramatic embedded processor volumes and the associated market
segments force a reevaluation of the best way to satisfy the possibly
conflicting demands placed on processor designs. Domain-specific
embedded processors, such as network, automotive, cellular and others,
present interesting architectural refinements, albeit at the cost of
splintering the embedded processor market. Reprogrammable and/or
reconfigurable embedded processors provide an alternative approach,
capable of delivering single, fixedsilicon architectures, thus
amortizing design and manufacturing costs across large volumes, yet
necessitating an answer to the challenge of effective customization
of embedded processors.

The workshop papers explore (micro)architectural design approaches
and trade-offs and compiler technologies, for both domain-specific
and customizable embedded processors. The workshop aims at generating
a forum wherein the various approaches to address the twin challenges
of cost amortization over large volumes while delivering optimal cost,
performance, and power characteristics for a wide segment of embedded
processor market niches will be explored and compared. WASP explores
emerging trends and novel concepts in application-specific processors.
Major topics include, but are not limited to:

    * Domain-specific processors (Network, multimedia, etc.)
    * Application-specific hardware accelerators
    * Microarchitectural customization techniques
    * (Re)configurable processor architectures
    * Dynamically reconfigurable processors (Microarchitectural,
                     Coarse-grained, FPGA, etc.)
    * Application-specific processors in System-on-a-chip (SOC)
    * Application-specific customizations for low-power
    * Compiler techniques for processor customizations
    * OS and Middleware support for application-specific processors


General Chair: Faraydon Karim, ST Micro
Technical Program Chair: Peter Petrov, UC San Diego
Publicity Chair: Scott Mahlke, U Michigan
E-Media Chair: Ismet Bayraktaroglu, SUN
Publication Chair: Paolo Ienne, EPFL
Special Issue: Alex Veidenbaum, UC Irvine
Special Sessions: Fadi Kurdahi, UC Irvine

Technical Program Committee:
Tarek Abdelrahman, U Toronto
Pradip Bose, IBM
Kiyoung Choi, Seoul National U
Pai Chou, UC Irvine
Ed Deprettere, Leiden U
Nikil Dutt, UC Irvine
Carl Ebeling, U Washington
Eric Flamand, ST Micro
Krisztian Flautner, ARM
Daniel Gajski, UC Irvine
Joerg Henkel, U Karlsruhe
Vojin Oklobdzija, UC Davis
Sri Parameswaran, U New South Wales
JoAnn M. Paul, CMU
Majid Sarrafzadeh, UCLA
Cristina Silvano, Politecnico di Milano
Paco Tirado, U Complutense de Madrid
Stamatis Vassiliadis, Delft U
Hiroto Yasuura, Kyushu U



Article: 70159
Subject: Rocket IO Timing Problem : sometimes miss Half Word
From: "Adarsh Kumar Jain" <adarsh.jain@cern.ch>
Date: Mon, 7 Jun 2004 10:10:29 +0200
Links: << >>  << T >>  << A >>
Hi All,
I am using a Xilinx V2Pro with 8 Rocket IOs all of which are being used.
My problem is that once in a while one or two channels misalign the data.
They mix up one byte of the Idle Word with one byte from Valid data
and then the whole subsequent data stream gets misaligned like that.
And sometimes i completely miss the first Valid Data Word.
Too me it looks like a timing problem, exactly what i can't figure out.
This is because, the problem is not fixed or repeatable. For example
sometimes
i see it happening on say just channel one, but if i power down the board
and restart,
then the problem either disappears or appears in another channel.
I have 8 xilinxs on the board and the problem is the same for all of them.
And within the Xilinx, all the channels are completely identical and so that
does not really "help" me in debugging.
Is there something i need to do to make the design more "robust" ?
Please advise,
Thanks in advance,
adarsh



Article: 70160
Subject: Re: parameter feature of AHDL in Xilinx
From: Anders Hellerup Madsen <anders@hellerup-madsen.dk>
Date: Mon, 07 Jun 2004 11:20:15 +0200
Links: << >>  << T >>  << A >>
Charles Zheng wrote:
> In altera's tool, if a .tdf file uses the parameter for that component, and
> if you instantiate the component in the schematic, you can change the
> parameter by right clicking on the symbol.  I wonder if there is similar
> feature with VHDL file in Xilinx ISE's ECS tool.  That is a convenient
> feature because you can instantiate as many time as you want, and just
> change the parameter in the schematic to customize each one of them.

Yes. For each core you have to supply a .mpd file which defines the 
input and output ports of the core, and in this file you can define 
parameters for the core. The parameters can be assinged values be 
double-clicking on the core in the "Platform Studio" tool. When the 
cores are compiled the parameters turn into generics for VHDL code and 
something similar for Verilog.

-- Anders

Article: 70161
Subject: Rocket IO : Sensitivity to RefClk Phase
From: "Adarsh Kumar Jain" <adarsh.jain@cern.ch>
Date: Mon, 7 Jun 2004 11:32:27 +0200
Links: << >>  << T >>  << A >>
Hi All,
I am simulating the Rocket IOs but it seems the working of the
rocket IOs is extremely sensitive to the phase of the RefClk.
I change the phase a little bit and i get a message in simulation
which says that the Rocket IO lost sync with RefClk.
Is there a way to control this behaviour ?
Adarsh



Article: 70162
Subject: comp.arch.fpga: reset strategy
From: pop <>
Date: Mon, 7 Jun 2004 03:47:55 -0700
Links: << >>  << T >>  << A >>
Hi 

I have inherited a design containing both asyncrous and syncronous FF. 
I started to rewrite the code but started to doubt the strategy. Does 
anybody know which is better. The FPGA is very large.


Article: 70163
Subject: Problem with the "Write RPM to UCF" command (floorplanner 6)
From: yvan.eustache1@etud.univ-ubs.fr (yvan.eustache1@etud.univ-ubs.fr)
Date: 7 Jun 2004 04:46:04 -0700
Links: << >>  << T >>  << A >>
Hi 

I have problems with the "Write RPM to UCF" command in the
floorplanner 6.2i.

I use a VirtexE.

I want to make RPM and when I click on the "Write RPM to UCF" command,
The macro in The *.ucf file starts with a "RLOC="X0Y0"" constraints.
All macro logics have "RLOC="R0C0"" constraints.

I can't reuse the macro because the map fails with the error :
>>>ERROR:Map:6 - Bad format for RLOC constraint "X0Y0" on reg_sortie
symbol
   "Inst_reg_sortie".

Help me please...

Yvan EUSTACHE

Article: 70164
Subject: Re: Quick question
From: johnjakson@yahoo.com (john jakson)
Date: 7 Jun 2004 05:46:52 -0700
Links: << >>  << T >>  << A >>
"Jason Berringer" <look_at_bottom_of@email.com> wrote in message news:<rVrwc.55767$Hn.1478571@news20.bellglobal.com>...
> Hello all,
> 
> I'm curious to know the benefits of using third party synthesis tools. For
> example how much better are synthesis tools like Synplicity or Synplify, etc
> over just using the vendor tools ISE Webpack. Do you only experience some
> significant gains with large designs or does it not really matter. I've been
> using the Xilins synthesis tools for quite a while and have never had a
> problem. I will be the first to admit that my largest designs have only
> taken up about 60% of a XC2S150 so I'm not dealing with mosterous designs.
> 
> Anyn commetns are appreciated.
> 
> Jason
> 
> jberringer@remove.sympatico.remove.ca
> 
> remove the removes to reply to me personally.

search back through previous posts on synplicity, I recall several
posters have said that they were getting better results than webpack
on the larger designs, which I can believe although for now webpack is
fine for me too.

regards

johnjakson_usa_com

Article: 70165
Subject: Good SDRAM Controller
From: petersommerfeld@hotmail.com (Peter Sommerfeld)
Date: 7 Jun 2004 07:34:32 -0700
Links: << >>  << T >>  << A >>
Hi folks,

Can anyone recommend an SDRAM controller, free or otherwise, with the
following features:
  - synthesizable to >100 MHz fmax on Stratix -7 (preferably 133 MHz)
  - allows latent read bursts to maximum throughput
  - burtsts efficiently (keeps bank rows open where possible)

For starters, I am looking at Rudolf Usselmann's controller from
OpenCores but I'm concerned that the Wishbone interface may not
support latent reads. Can anyone confirm this?

I also looked at Altera's SDRAM controller but it won't synthesize
past 100 MHz.

Regards,

-- Pete

Article: 70166
Subject: Re: Good SDRAM Controller
From: Dave Vanden Bout <devb@xess.com>
Date: Mon, 07 Jun 2004 15:02:38 GMT
Links: << >>  << T >>  << A >>
petersommerfeld@hotmail.com (Peter Sommerfeld) wrote in 
news:5c4d983.0406070634.385ec9ff@posting.google.com:

> Hi folks,
> 
> Can anyone recommend an SDRAM controller, free or otherwise, with the
> following features:

You might try the one at http://www.xess.com/projects/sdramtst-1_2.zip.  
The documentation is at 
http://www.xess.com/appnotes/an-030104-sdramcntl.pdf

>   - synthesizable to >100 MHz fmax on Stratix -7 (preferably 133 MHz)
Unknown.  It runs at 100 MHz on an the slowest speed grade of SpartanII.
It does use Xilinx DLLs at the very top-level but these can be stripped 
out without any effect.  The rest is standard VHDL so it should be 
synthesizable for Altera.

>   - allows latent read bursts to maximum throughput
It does have some delay when you first read from a row if the row was not 
already open, but after that you can pipeline the reads so you get a new 
word every cycle.  Writes work the same way.

>   - burtsts efficiently (keeps bank rows open where possible)
Yes, it does that but it doesn't keep rows open in separate banks.  So 
you incur the delay of opening a row each time you read or write to a 
different bank.




> 
> For starters, I am looking at Rudolf Usselmann's controller from
> OpenCores but I'm concerned that the Wishbone interface may not
> support latent reads. Can anyone confirm this?
> 
> I also looked at Altera's SDRAM controller but it won't synthesize
> past 100 MHz.
> 
> Regards,
> 
> -- Pete
> 



-- 
----------------------------------------------------------------
Dr. Dave Van den Bout
XESS Corp.
PO Box 33091
Raleigh NC 27636
Phn: (919) 363-4695
Fax: (801) 749-6501
devb@xess.com
http://www.xess.com


Article: 70167
Subject: Re: Quick question
From: "John_H" <johnhandwork@mail.com>
Date: Mon, 07 Jun 2004 16:02:49 GMT
Links: << >>  << T >>  << A >>
I see you're not pushing density yet.  Are you pushing speed?  If your needs
are for slow clocks, low complexity, and low density, you shouldn't need
anything more than you have.  Other third party tools can provide higher
speed performance through better optimizations that have sensitivity to
which paths are more critical than others.  When it was first coming out,
XST (Xilinx Synthesis Technology) was heralded as a nice, technically
accurate compiler that will always have access to the latest silicon
features.  Its purpose was not to provide spectacular performance results;
for the points where it does outdo third party tool vendors, kudos!

I have a design now where I know where my worst delay will be and my coding
style is attempting to coax the critical signal into the last layer of
logic.  My expectation is that the 3rd party synthesis will deliver good
results to begin with and only need a little tweaking to get the worst
behaving paths under control.  I'd expect much more interaction with XST to
be able to achieve similar results, but this is a guess;  I haven't USED the
tool, only listened to their FAEs.


"Jason Berringer" <look_at_bottom_of@email.com> wrote in message
news:rVrwc.55767$Hn.1478571@news20.bellglobal.com...
> Hello all,
>
> I'm curious to know the benefits of using third party synthesis tools. For
> example how much better are synthesis tools like Synplicity or Synplify,
etc
> over just using the vendor tools ISE Webpack. Do you only experience some
> significant gains with large designs or does it not really matter. I've
been
> using the Xilins synthesis tools for quite a while and have never had a
> problem. I will be the first to admit that my largest designs have only
> taken up about 60% of a XC2S150 so I'm not dealing with mosterous designs.
>
> Anyn commetns are appreciated.
>
> Jason
>
> jberringer@remove.sympatico.remove.ca
>
> remove the removes to reply to me personally.
>
>



Article: 70168
Subject: Re: Variable Frequency and Voltage Supply
From: Peter Alfke <peter@xilinx.com>
Date: Mon, 07 Jun 2004 13:19:01 -0700
Links: << >>  << T >>  << A >>
The supply voltage (except for I/Os) is dictated by the manufacturere,
so you have only a few percent to play with.
Dynamic power consumption is proportional to clock rate, so you have
enormous leeway, but watch out for min frequency limits on PLL and
DLL/DCM-controlled clocks.
Leakage current used to be insignificant, then became a few mA, and can
now be hundreds of mA. But it is inherently proportional to thechip
size, and worst for the newest FPGAs. (CoolRunner CPLDs are still unbeatable)

Peter Alfke
===============
GaRY wrote:
> 
> Hi,
> 
> I am very new in using FPGA. I wanna know is there any design of
> information in FPGA use variable clock and variable voltage, coz I
> want to find ways to reduce power when using FPGA.
> Thx for the help.
> 
> GaRY

Article: 70169
Subject: Re: Good SDRAM Controller
From: Roger Larsson <roger.larsson@skelleftea.mail.telia.com>
Date: Mon, 07 Jun 2004 21:11:06 GMT
Links: << >>  << T >>  << A >>
Peter Sommerfeld wrote:

> Hi folks,
> 
> Can anyone recommend an SDRAM controller, free or otherwise, with the
> following features:
>   - synthesizable to >100 MHz fmax on Stratix -7 (preferably 133 MHz)
>   - allows latent read bursts to maximum throughput
>   - burtsts efficiently (keeps bank rows open where possible)
> 
> For starters, I am looking at Rudolf Usselmann's controller from
> OpenCores but I'm concerned that the Wishbone interface may not
> support latent reads. Can anyone confirm this?

Why not ask the authors?

/RogerL

-- 
Roger Larsson
Skellefteċ
Sweden

Article: 70170
Subject: ISE 4.2i Impact and Windows XP not working
From: "Hendra Gunawan" <u1000393@email.sjsu.edu>
Date: Mon, 7 Jun 2004 19:19:32 -0700
Links: << >>  << T >>  << A >>
Hi folks,
I have Xilinx ISE 4.2i installed in Windows XP system. Everything runs fine
except the Impact program (the one you use to download the bitstream). It
said unable to detect the cable or something like that. What can I do to
make Impact run with Windows XP?
I look at Xilinx website and they recommend to download Impact program that
comes with Webpack 6.2i and use it to download the bitstream. But I would
rather not to do that. I don't feel comfortable to have two different ISE in
the same system.

Thanks in advance!

Hendra



Article: 70171
Subject: DCM in Xilinx
From: czheng@ieee.org (charles)
Date: 7 Jun 2004 19:51:42 -0700
Links: << >>  << T >>  << A >>
I am doing a small experiment with DCM.  I used the coregen to
configure it to use a 100Mhz input clock, and output CLK0 and LOCKED. 
RST is also tied to a pushbutton RESET.  Feedback 1x internal is
configured, and so does the duty cycle correction.  Then I instantiate
the module in schematic, and tie all the port to inport and outport
apprepriately without any IBUF,OBUF or BUFG primitives.  I noticed a
extra pin coming out of the DCM: CLKIN_IBUFG_OUT. I implemented the
design and downloaded to a xc2vp4 FPGA prototype board.  But somehow I
can not get CLK0 to come out. CLKIN_IBUFG_OUT is coming out fine. 
LOCKED is still low.  So it is not locking, and that is why CLKO is
not coming out. But why?  Such a simple design.  Someone help.

Charles

Article: 70172
Subject: Re: comp.arch.fpga: reset strategy
From: "Hendra Gunawan" <u1000393@email.sjsu.edu>
Date: Mon, 7 Jun 2004 20:16:51 -0700
Links: << >>  << T >>  << A >>


http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_Resets_rev1_1.pd=
f
http://www.sunburst-design.com/papers/CummingsSNUG2003Boston_Resets_rev1_=
2.pdf

Hendra



Article: 70173
Subject: Re: comp.arch.fpga: reset strategy
From: "John Retta" <jretta@rtc-inc.com>
Date: Tue, 08 Jun 2004 04:13:33 GMT
Links: << >>  << T >>  << A >>

 The previously mentioned article was an interesting read.  I have always
been a strong
advocate of synchronous design, and this includes the application of resets.
  My rule of thumb is use synchronous resets in all areas, unless
exceptional
conditions arise.  There are at least two good exceptions :
[1] Block of logic may have a clock which after power-up disappears, example
clock derived from a DDS which might be reset operationally.  In order to
restore outputs
to inactive states in absence of clock, asynchronous reset needs to be used.
[2] Sequential logic drives tristate enable control - During powerup or
during
in-circuit test mode, clock may not be present, and multiple drivers causing
contention
can cause device failure.
  My rationale for avoiding asynchronous resets is two-fold.  Once you
develop
synchronous design devotion, then allowing asynchronous resets seems to be
a strong violation.  Second, is kind of the real basis for synchronous
design
practices.  The only timing paths that need to be analyzed are from Q
outputs
of flops to D- Inputs.  I think static timing analyzers are much better at
timing
asynchronous reset paths, but as recently as 2-3 years ago, I don't think
this
was the case.  Problem is that the start of the path is no longer the
originating
D-FF, but rather the reset source which drives the reset to this device.
  Sometimes historical problems which have been later resolved still don't
cause a designer to abandon coding styles that were reinforced by hard to
trace problems.
-- 
Regards,
John Retta - Colorado based Xilinx Design Consultant
Owner and Designer
Retta Technical Consulting Inc.

email : jretta@rtc-inc.com
web :  www.rtc-inc.com


<pop> wrote in message news:ee86f56.-1@webx.sUN8CHnE...
Hi

I have inherited a design containing both asyncrous and syncronous FF. I
started to rewrite the code but started to doubt the strategy. Does anybody
know which is better. The FPGA is very large.



Article: 70174
Subject: Virtex-4 FX transceiver jitter
From: Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid>
Date: Tue, 08 Jun 2004 14:18:51 +1000
Links: << >>  << T >>  << A >>
Hi,
Does anyone know if the (just announced) Virtex-4 FX transceivers will
have jitter characteristics suituable for SONET work at 10Gb/s?

The current (V2PX) transceivers aren't able to meet the jitter specs,
forcing the use of external SERDES devices.

There's not much real information on the web page yet.
http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Virtex-4

TIA,
Allan.



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