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ram <ramntn@yahoo.com> wrote in message 61c2cc9d.0405071751.1dc395c9@posting.google.com... > Hi Group, > I am designing a simple core to add to the opb bus > using opb_ssp0 package. > The core has 2 register, and I am tryin to write a value > and read from them. > But when I do that its giving me an output thats wierd, > whenever I write a even number to the register I read > back an odd number (one greater then the even number) > but for odd numbers its ok. My first design with EDK had exactly the same problem! The LSB of every register seemed to be stuck at 1... We solved the problem by setting a valid address range for the MIR registers (even if MIR was disabled) and by using a fixed 1 for the IPIF Ack signal (this was ok for our cores, but it is not a good idea in general...). Good luck, Antonio Di Stefano P.S. MIR registers have typically an address range 256 byte wide, starting from a 0x------00 address to a 0x------FF one...Article: 69376
Hi Tom,
Yes I was, I think, a very early adopter of Confluence. I find the
language very impressive. Your FFT core on OpenCores is what got me
interested in it.
The biggest problem has been convincing my company to consider the
tool, which I have so far been unsuccessful with. As is typical, a
company adopts certain standards and practices, and the intertia is
difficult to overcome. Hopefully someday ...
Not that I'm unhappy with VHDL, in fact as long as I can work with the
latest FPGAs with whatever language I think I'll be very happy, but
from my tests I can write IP faster in Confluence than VHDL, and the
learning curve is shorter.
-- Pete
> Pete, I'm sure you're aware that Confluence does not have this
> limitation:
>
> component some_comp *gaggle with local_source external_reference is
> gaggle.from_here <- local_source
> gaggle.from_somewhere_else -> external_reference
> end
>
> And in the second thread that Mike referenced, the author mentioned
> partial function applications. As a functional programming language,
> Confluence has a few forms of partial functions:
>
> system = {my_component _ _ _}
>
> This allows you to instantiate a component with the ports unconnected,
> then pass around the resulting system to be wired up later.
>
> -Tom
>
>
> > > >> gaggle.DSPaddr <= DSPaddr;
> > > >> gaggle.DSPdata_in <= DSPdata;
> > > >>-- . . . (rest of INs go here)
> > > >>-- then OUTs:
> > > >> nDHOLD <= gaggle.nDRDY;
> > > >> nDRDY <= gaggle.nDRDY;
> > > >> DSPdata <= gaggle.DSPdata_out when output_enabled
> > > >> else (DSPdata'range => 'Z');
>
> >
> >
> > > Peter,
> > > As a PS to my other post, to date I have found
> > > that if I want to work with a single record,
> > > I have been limited to std_logic family.
> > >
> > > I have tried tinkering with integers and resolution
> > > functions, but have had problems with resolving a value
> > > to drive when the record field is not to be driven.
> > > It seems that the resolution function is called at the
> > > block level and there currently no way I could find to
> > > work around this.
> > >
> > > This is a topic we are kicking around in the VHDL-200X
> > > effort. I had wished for it to be part of the fast track
> > > effort and I made a proposal, but it is not clear even to
> > > me that the proposal is the best long term solution, so I
> > > don't want to push it. My preference is to see what comes
> > > up when we give more time and consideration to the problem.
> > >
> > > For more on the vhdl-200x effort, see:
> > > http://www.eda.org/vhdl-200x
> > >
> > > IEEE standards are open to public participation.
> > >
> > > Best Regards,
> > > Jim
> > >
> > >
> > > > Hi Mike,
> > > >
> > > > Yes I found my problem, and it was unfortunately in a part of my
> > > > record that I didn't post. In my record, I had a field that was of the
> > > > physical type time which I was using inside my procedures for certain
> > > > delays. ie:
> > > >
> > > > type rec is record
> > > > ...
> > > > clock_period : time;
> > > > ...
> > > > end record;
> > > >
> > > > So while I was assuming a signal-driving issue to be the problem, it
> > > > was this field (which is still bizarre, because I set this field only
> > > > once and never write it again, therefore, I would have thought, it
> > > > could not be a problem). Anyways, I replaced this field with a clock
> > > > signal which makes more sense now anyways and everything works great,
> > > > and thanks to yours and Jim's replies, I understand what's going on
> > > > much better too. I had better post the whole thing the next time I
> > > > have a problem like this.
> > > >
> > > > -- Pete
> > > >
> > > >
> > > >>Peter Sommerfeld wrote:
> > > >>
> > > >>
> > > >>>Thanks for the reply. I must be on the right track, because it looks
> > > >>>like I have been doing what you suggested in
> > > >>>http://groups.google.com/groups?q=gaggle.DSPaddr. However, the InitBus
> > > >>>call causes compile errors in my design.
> > > >>
> > > >>You have stumbled onto the procedure scope problem.
> > > >>Re-read that thread and see the lines I added
> > > >>to my example architecture below.
> > > >>
> > > >> -- Mike Treseler
> > > >>
> > > >>
> > > >>------------------------------------------------------------
> > > >>architecture synth of signal_structure is
> > > >> -- note, I changed your type to data in and out signals
> > > >>
> > > >> type DSPIF_type is
> > > >> record
> > > >> DSPaddr : std_logic_vector(23 downto 0);
> > > >> DSPdata_in : std_logic_vector(31 downto 0);
> > > >> DSPdata_out : std_logic_vector(31 downto 0);
> > > >> nDHOLD : std_logic;
> > > >> nDHOLDA : std_logic;
> > > >> nDPAGE : std_logic_vector(3 downto 0);
> > > >> nDSTRB : std_logic;
> > > >> nDBE : std_logic_vector(3 downto 0);
> > > >> nDOE : std_logic;
> > > >> nDWE : std_logic;
> > > >> nDRDY : std_logic;
> > > >> end record;
> > > >>
> > > >> signal gaggle : DSPIF_type;
> > > >> signal output_enabled : boolean;
> > > >>-------------------------------------------------------------------------------
> > > >> -- Added proc example in scope
> > > >> procedure InitBus( signal gaggle: inout DSPIF_type )
> > > >> is begin end InitBus;
> > > >>-------------------------------------------------------------------------------
> > > >>begin
> > > >> -- wire up signal structure to pins
> > > >> gaggle.DSPaddr <= DSPaddr;
> > > >> gaggle.DSPdata_in <= DSPdata;
> > > >>-- . . . (rest of INs go here)
> > > >>-- then OUTs:
> > > >> nDHOLD <= gaggle.nDRDY;
> > > >> nDRDY <= gaggle.nDRDY;
> > > >> DSPdata <= gaggle.DSPdata_out when output_enabled
> > > >> else (DSPdata'range => 'Z');
> > > >>
> > > >>-- processes using the gaggle signals go here
> > > >>
> > > >>end architecture synth;
> > > >>
> > > >>
> > > >> -- Mike Treseler
> > >
> > >
> > > --
> > > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> > > Jim Lewis
> > > Director of Training mailto:Jim@SynthWorks.com
> > > SynthWorks Design Inc. http://www.SynthWorks.com
> > > 1-503-590-4787
> > >
> > > Expert VHDL Training for Hardware Design and Verification
> > > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Article: 69377
Hello,
i have a counter which is 27 bit long.
signal counter : STD_LOGIC_VECTOR(26 downto 0);
Is there a "better" way to reset than counter <= "00000000...00000" ?
Something like counter <= 0 (26 downto 0) or counter <= 0 ?
Regards,
Martin
Article: 69378I'm having trouble using floats with the PPC compiler. Any inclusion of floats produces a pretty indecipherable (to me) linker error. I tried -lm but that doesn't help. Any ideas? Thanks. -DaveArticle: 69379
Hi! anybody knows if it is possible to program an Altera EPM7032LC44 (plcc44) with an hilo-systems ALL-03A programmer and the adapter ADP-EPM7032 /PL The AMAX70.EXE driver fails, asking for the ADP-EPM7032/-Q adaptor. This is a QFP adapter for the EPM7032TQ44. The A70XE.EXE driver fails, asking for the ADP-EPM7128E/-PL adaptor. anybody have hints to know which software to use with ADP-EPM7032/PL adapter. list of adp files for the all03 available here http://matthieu.benoit.free.fr/all03/adp but don't think the righr file is here. any help appreciated, MBArticle: 69380
Martin,
If your signal "counter" is declared as an integer with a valid range you
can then use a reset as shown:
signal counter : integer range 0 to 67108863 := 0;
...
if reset = '0' then
signal counter <= 0;
...
Another method if you are using standard logic vectors is
...
if reset = '0' then
signal counter <= (others => '0');
...
Hope that this helps,
Jason
".Martin Maurer" <capiman@clibb.de> wrote in message
news:c7m4vd$m5d$05$1@news.t-online.com...
> Hello,
>
> i have a counter which is 27 bit long.
>
> signal counter : STD_LOGIC_VECTOR(26 downto 0);
>
> Is there a "better" way to reset than counter <= "00000000...00000" ?
> Something like counter <= 0 (26 downto 0) or counter <= 0 ?
>
> Regards,
>
> Martin
>
>
Article: 69381On Sun, 9 May 2004 22:40:10 +0200, "Martin Maurer" <capiman@clibb.de> wrote: >Hello, > >i have a counter which is 27 bit long. > >signal counter : STD_LOGIC_VECTOR(26 downto 0); > >Is there a "better" way to reset than counter <= "00000000...00000" ? >Something like counter <= 0 (26 downto 0) or counter <= 0 ? counter <= (others => '0'); This is in the comp.lang.vhdl FAQ, http://www.vhdl.org/comp.lang.vhdl/ http://www.vhdl.org/comp.lang.vhdl/FAQ1.html#const_vectors Regards, Allan.Article: 69382
Hi all, I am a novice user of ISE and seeking for help. bitgen program in ISE can generate readback bitstream by command line bitgen -w -l -m -g readback -g persist:X8... from application note XAPP176. So *.rbb and *.msk can be generated. My question is, how to generate readback ASCII file? .rba Thank you in advance. fhleungArticle: 69383
Hi, I have this in my .syr report file from XST: Set property "equivalent_register_removal = no" for signal <foo>. Set property "equivalent_register_removal = no" for signal <bar>. ... Register <bar> equivalent to <foo> has been removed I really don't understand why bar and foo are being merged when the tool knows they are not supposed to be. Can anyone please tell me how I can stop registers from being merged? I think this code used to work properly, and the problem may be due to a bug in XST 6.2.3. BTW, the relevant Verilog source is: // synthesis attribute equivalent_register_removal of foo is no; // synthesis attribute equivalent_register_removal of bar is no; reg foo; reg bar; always @(posedge clk) begin foo <= froboz; bar <= froboz; end TIA, Allan.Article: 69384
It's been 20 plus years since I did any real design work. I currently am starting to learn VHDL in order to create a design that will capture serial data. The serial interface I need to capture data from consists of a 1 Mhz Clock, Data (32 bits) and Enable signals. Any help on where to look for examples or how to get started would be appreciated. If this is the wrong news group, let me know. Thanks, JoelArticle: 69385
> parallax were selling a few boards > also altera was selling some "student" boards > a while back > > Alex Here's a link to the parallax boards: Cyclone 1C3 based, $195: http://www.altera.com/products/devkits/altera/kit-parallax_cyclone_fstpck.html Cyclone 1C20 based, $295: http://www.altera.com/products/devkits/altera/kit-parallax_cyclone_smrtpck.html Also check out the JOP board listed elsewhere in this thread, which is another reasonably-priced Cylone board. All Cyclone devices are supported by Quartus II web edition, which you can download for free from: http://www.altera.com/products/software/pld/products/quartus2/sof-quarwebmain.html Quartus includes HDL synthesis, schematic entry, place and route, static timing analysis, visualization, floorplanning tools, etc. Pretty much all you need to learn about FPGAs. Larger list of Altera-based development boards (most more expensive than you want though): http://www.altera.com/products/devkits/kit-dev_platforms.jsp Regards, Vaughn AlteraArticle: 69386
Hi Jim,
the testbench part is here:
signal lclk : std_logic := '0';
process (lclk) -- Generate 100 Mhz clock (Periodendauer 10 ns)
begin
if lclk='0' then
lclk <= '1' after 15 ns, '0' after 30 ns;
end if;
end process;
The clock works fine. But both outputs of the DCM are always '0'.
Any ideas
Juergen
"Jim Wu" <NOSPAM@NOSPAM.com> wrote in message news:<R8Umc.29892$wY.21792@nwrdny03.gnilink.net>...
> > in order to verify the functionality of XILINX DCM, I have generated a
> > dcm.vhd file with the ISE 6.2 architecture wizard. The dcm module is
> > embedded into a simple top-level file that only connects the testbench
> > signals (in-clock and reset (=0) to the DCM-module. The DCM reset
> > signal is always set to '0'.
> >
>
> It would help if you can post the testbench code as well. Sometimes the
> generation of the inputs to the DCM may affect the behavior simulation
> model. I've seen that DCM model does not work if the input clock starts at 1
> at time 0. e.g
>
> process
> clock_in <= '1';
> wait for 10ns;
> clock_in <= '0';
> wait for 10ns;
> end process;
>
> HTH,
> Jim
> jimwu88NOOOSPAM@yahoo.com
> http://www.geocities.com/jimwu88/chips
Article: 69387apple2ebeige@yahoo.com (Dave) wrote in message news:<d4aa8e8a.0405091311.76c6a81c@posting.google.com>... > I'm having trouble using floats with the PPC compiler. Any inclusion > of floats produces a pretty indecipherable (to me) linker error. I > tried -lm but that doesn't help. Any ideas? Thanks. > > -Dave Posting the error message might help.. Cheers, JonBArticle: 69388
Hi people Well here I am. I have never tried work with bootloaders before so I thought that news groups might would be a good place to start as all the old school experts hang around here :o) One of my problems are that I need to fit alot of SW down in to a 1MB flash. So i'm looking for the possiblity of compressing the binary file and then extracting this into the RAM(2MB). How can this be done???( in detail if possible) I am working with the cyclone(NIOS) FPGA from Altera. Anyone who know any good web based forums for FPGA developers??? Best Regards GreateWhite.DKArticle: 69389
I have modified the testbench, but nothing happens at the DCM output.
from my testbench file:
------------------------
signal lclk : std_logic := '0';
process (lclk) -- Generate 100 Mhz clock (Periodendauer 10 ns)
begin
if lclk='0' then
lclk <= '1' after 15 ns, '0' after 30 ns;
end if;
end process;
------------------------
Any ideas
Jürgen
"Jim Wu" <NOSPAM@NOSPAM.com> wrote in message news:<R8Umc.29892$wY.21792@nwrdny03.gnilink.net>...
> > in order to verify the functionality of XILINX DCM, I have generated a
> > dcm.vhd file with the ISE 6.2 architecture wizard. The dcm module is
> > embedded into a simple top-level file that only connects the testbench
> > signals (in-clock and reset (=0) to the DCM-module. The DCM reset
> > signal is always set to '0'.
> >
>
> It would help if you can post the testbench code as well. Sometimes the
> generation of the inputs to the DCM may affect the behavior simulation
> model. I've seen that DCM model does not work if the input clock starts at 1
> at time 0. e.g
>
> process
> clock_in <= '1';
> wait for 10ns;
> clock_in <= '0';
> wait for 10ns;
> end process;
>
> HTH,
> Jim
> jimwu88NOOOSPAM@yahoo.com
> http://www.geocities.com/jimwu88/chips
Article: 69390Hi newsgroup people, I want to perform a timing simulation of an SRAM controller with Modelsim (version Altera 5.7e) . The background: With address, data and write strobe all changing simultaneously, I am not sure whether the right data will get written to the right location in the SRAM. Right now I am performing a functional simulation. Since I am running with timing check off, data should never be corrupted. Since the SRAM controller is a central module in my design I have to know exactly whether it will run correctly or not so that other modules adapted to the controller will not have to be modified belatedly. It is for that purpose of operating on a boundary condition that I want to add timing to my simulation to get a better idea of what will happen in hardware. I am working with Altera QuartusII software (version 4.0 SP1). For the purpose of a timing simulation under Modelsim I would like to know how to make settings in QuartusII to get the correct output files and how to include them in Modelsim. I would appreciate if you had the time to have a closer look at http://mitglied.lycos.de/vazquez78 Thank you very much for your help.Article: 69391
Weddick wrote:
> It's been 20 plus years since I did any real design work. I currently am
> starting to learn VHDL in order to create a design that will capture serial
> data. The serial interface I need to capture data from consists of a 1 Mhz
> Clock, Data (32 bits) and Enable signals.
>
> Any help on where to look for examples or how to get started would be
> appreciated. If this is the wrong news group, let me know.
Howdy Joel,
The fpga and VHDL news groups seem to support each other sometimes.
This sounds like a purely VHDL question, unless you're trying to do
something fancy or tricky with the FPGA to solve your problem.
You'll probably need to provide a better description of your data stream
to get a good answer on what you need. For example, is the enable like
a sync pulse, where it occurs once per 32 bits, or is it active for each
bit that is valid? If it happens on every bit, how is your circuit
supposed to know which bit on the serial line is to be the MSB of the 32
bit word? Is there a framing sequence in the data?
The fact that the clock is sent along with the data makes this a
relatively straight forward problem. If the enable bit is sent once per
32 bits, it could pre-set a synchronous counter which counts down to 0.
The counter could be used to index into a std_logic_vector(31 downto
0), and when it hit zero, you will have a 32 bit word ready to work
with (latch into a second set of flip flops).
Marc
Article: 69392
Hi all
The source clock pin of the DLL is from the external PLL, which
generates 2 different frequencies. As mentioned in the Application
note of Spartan II, if there is a change in the input frequency, usage
of the Reset pin is mandatory. I tried to generate an internal signal
as the reset signal and connected that internal signal to the reset
pin of the DLL. When the above mentioned logic was implemented, I got
errors stating that the internal signal has multiple drivers and the
input pad net has illegal connections.
1. Is that possible to use an internal signal as the reset signal?
----------------------------
START |------------|-------> START
| |
GENERATE FREQ I | | GENERATE FREQ II
| |
IF DONE | | IF DONE
| |
RESET_DLL = 0 | | RESET_DLL = 0
| |
WAIT FOR APP: 3ms | | WAIT FOR APP. 3ms
| |
STOP GEN. FREQ I | | STOP GEN. FREQ II
AND --- ------ AND
PULL RESET_DLL =1 PULL RESET_DLL = 1
RESET_DLL ---> is the internal signal which is used as the reset
signal and this internal signal is stimulated as mentioned above.
THE ERROR MESSAGE:
ERROR:NgdBuild:455 - logical net 'pll_serial_rst_modclk' has multiple
drivers.
The possible drivers causing this are pin q on block
pll_serial_rst_modclk
with type FDE, pin PAD on block pll_serial_rst_modclk.PAD with type
PAD
ERROR:NgdBuild:466 - input pad net 'pll_serial_rst_modclk' has illegal
connection. Possible pins causing this are pin i1 on block
pll_serial__n00171
with type LUT4, pin q on block pll_serial_rst_modclk with type FDE
Or is there any other possibility to implement the reset signal?
Eagerly waiting for your suggestions..
Thanks in advance..
Regards
Rajesh
Article: 69393hi! try to reset the dcm after 3 or more clk cycles of clkin. hold the reset for about 3 or more clk cycles best regards wolfgang "Jim Wu" <NOSPAM@NOSPAM.com> schrieb im Newsbeitrag news:R8Umc.29892$wY.21792@nwrdny03.gnilink.net... > > in order to verify the functionality of XILINX DCM, I have generated a > > dcm.vhd file with the ISE 6.2 architecture wizard. The dcm module is > > embedded into a simple top-level file that only connects the testbench > > signals (in-clock and reset (=0) to the DCM-module. The DCM reset > > signal is always set to '0'. > > > > It would help if you can post the testbench code as well. Sometimes the > generation of the inputs to the DCM may affect the behavior simulation > model. I've seen that DCM model does not work if the input clock starts at 1 > at time 0. e.g > > process > clock_in <= '1'; > wait for 10ns; > clock_in <= '0'; > wait for 10ns; > end process; > > HTH, > Jim > jimwu88NOOOSPAM@yahoo.com > http://www.geocities.com/jimwu88/chips > > >Article: 69394
Symon wrote: > Very true, for example you need this with Synplify > > attribute syn_black_box : boolean; > attribute syn_black_box of icon : component is TRUE; > attribute syn_noprune : boolean; > attribute syn_noprune of icon : component is TRUE; > For Precision one needs: attribute preserve_driver : boolean; attribute preserve_driver of control0 : signal is true; The Chipscope Core Generator generates attributes for the predecessor of Precision, Leonardo and I assumed they are compatible :-(. Bye TomArticle: 69395
On Saturday 08 May 2004 05:00 pm, Richard Stallman wrote: > One of the reasons free software is important is so that you can > control your computer and make sure you know what it does. > It's not enough to be able to see what someone claims is the > source code for the program you are using. To trust it, you have > to be able to compile it yourself. > > As hardware becomes more complex, the same issue may arise: how do > you know what you hardware really does? Free hardware designs > could be part of the solution, but we can't all afford fab lines, > so could we really solve the problem completely? The bigger problem is the complete lack of an open-source flow from RTL to implementation. There is simply no GCC equivalent for compiling digital logic -- every ASIC and FPGA designer is at the mercy of commercial tools on the font-end. (My biggest pet-peeve is FPGA synthesis. FPGAs have had dual-port RAMs for ~7 years now, yet we still can't infer dual-port block RAM from HDL. Arggh!) One hurdle to open-source synthesis and place&route is proprietary architectures. The major FPGA vendors refuse to disclose the underlying details needed to for a quality PAR tool or physical synthesis. But oddly enough the biggest roadblock to open-source EDA is ourselves. For some reason or another, there is an apparent lack of interest and motivation. Just a few examples: 1. Every couple of months the topic of open-source tools arise. Generates quite a bit of discussion, then dies as quickly as it started. http://www.opencores.org/forums.cgi/cores/2003/09/00014 http://archives.seul.org/geda/dev/Nov-2003/msg00012.html This thread started 4 days ago, and sums up the view of open-source in EDA. :-( http://groups.google.com/groups?q=comp.arch.fpga+status+open+source+tools 2. With Confluence under GPL, I have yet to receive a single bug report or source code contribution. http://www.eedesign.com/news/showArticle.jhtml;jsessionid=TIARDDA1PTO1CQSNDBGCKHY?articleId=18402723 3. Icarus Verilog, the foremost open-source Verilog implementation, still only has one active developer. http://www.icarus.com/eda/verilog/ 4. The only semi-successful FPGA packing, placement, and routing project haulted activity in March, 2000. http://www.eecg.toronto.edu/%7Evaughn/vpr/vpr.html 5. The one person who came the closest to reverse engineering the Virtex bit stream -- the critical step for physical synthesis -- became frustrated with the lack of support and interest from the FPGA community, and finally closed shop on 12/24/2003. Merry Christmas. http://neil.franklin.ch/Projects/VirtexTools/Logfile What can we do to improve open-source EDA? Regards, Tom -- Tom Hawkins Launchbird Design Systems, Inc. Home of the Confluence Logic Design Language http://www.launchbird.com/Article: 69396
Hi, I'm using the Xilinx PCI-X core (64bit/133MHz) on an add in card to perform a DMA from the card into the system's memory. The user application in the FPGA requests 4Kbyte bursts and after transfering the 4Kbyte it gets a new address from the device driver. This application works well in a PC with Intel E7505 memory controller and P64H2 bridge. We achieve a datarate of about 450 MB/s. But it doesn't work in a HP Proliant DL380 with Serverworks Grand Champion LE chipset and CIOB-X2 bridge. In this system we only can transfer data for some seconds if the blocksize of the DMA is reduced to 1 Kbyte and then the system suspends and has to be rebooted. Does anyone have experience with a dma application on such a system? Thank you, MatthiasArticle: 69397
Anybody knows where can I find 80186 core to be placed into FPGA device? Preferably 80186 extended memory adresing version...Article: 69398
ACM, Oh, that was really mature. Did you know that we need to start new wafers to supply Easypath? (can not rely on having enough die with one or two memory cells that are at fault to satisfy demand). Did you know that the cost savings are mostly from testing the chip for what the customer uses it for, rather than for testing it for what everyone of our 250 thousand seats of software might design it to do? Oh, and what about all those laser trimmed redundant chips out there, are those also scrap? After all, every one of those has a proven hardware faults! (PS: thanks for bringing this up again, and giving me the opportunity to reply -- it is so much fun to see the subject line of your posting promoted by someone else besides me) Austin acm wrote: > Easypath = EasyScrap... > > Hey, buy our excess scrapped inventory!!!! >Article: 69399
Hi all, This question might obvious, but I cannot find any other way to instatiate signals from a top of a design for simulation purposses. What I usually do is to add those signals as ports in each entity beginning from the bottom of the design and continuing the hierarchy until I arrive to the top. In order not to consider them in the synthesis I add "synthesis translate off/on" comments. Here you are an example: Imagine that I want to instantiate the internal signal of the subblock1 from the top entity top is port( -- synthesis translate off tb_out : out std_logic; -- synthesis translate on ... ); end top; architecture arch of top is begin uut: subblock1 port map( -- synthesis translate_off internal => tb_out, -- synthesis translate_on ... ); end; Then I instantiate the top in the same way from the testbench. I know that in verilog there is another way just with something like this. "top.subblock1.internal" I would be glad is someone could help. Thanks in advance, Arkaitz.
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