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Messages from 69400

Article: 69400
Subject: Re: PCIX DMA Serverworks chipset
From: Mark Schellhorn <mark@seawaynetworks.com>
Date: Mon, 10 May 2004 11:25:52 -0400
Links: << >>  << T >>  << A >>
We are debugging similar types of issues with a Xilinx based PCI-X card and the 
chipsets you mention. There are numerous possible causes for the general symptom 
you describe. I presume these are dual Xeon chassis' you are talking about? Make 
sure your s/w guys understand read/write ordering and use of semaphores in 
multi-threaded applications and SMP systems.

My first suggestion is to get the documentation for the PCI-X bridge that you 
are interfacing with. For the particular chipset that you describe that could 
prove difficult :).

My second suggestion is to buy one of these (or something like it):

http://www.futureplus.com/products/fs2007/pcix_summary.html

and hook it up to your logic analyzer (you can rent one too, that's what we 
did). Being able to observe what's going on on that bus will save you a _lot_ of 
debugging time.

     Mark


Matthias Müller wrote:
> Hi,
> I'm using the Xilinx PCI-X core (64bit/133MHz) on an add in card to
> perform a DMA from the card into the system's memory. The user
> application in the FPGA requests 4Kbyte bursts and after transfering the
> 4Kbyte it gets a new address from the device driver.
> This application works well in a PC with Intel E7505 memory controller
> and P64H2 bridge. We achieve a datarate of about 450 MB/s. But it
> doesn't work in a HP Proliant DL380 with Serverworks Grand Champion LE
> chipset and CIOB-X2 bridge. In this system we only can transfer data for
> some seconds if the blocksize of the DMA is reduced to 1 Kbyte and then
> the system suspends and has to be rebooted.
> Does anyone have experience with a dma application on such a system?
> Thank you,
> Matthias
> 
> 

Article: 69401
Subject: RAM inference and Standards
From: Jim Lewis <Jim@SynthWorks.com>
Date: Mon, 10 May 2004 08:58:33 -0700
Links: << >>  << T >>  << A >>
Was:  Re: One issue about free hardware

Tom,
 > My biggest pet-peeve is FPGA synthesis.
> FPGAs have had dual-port RAMs for ~7 years now, yet 
> we still can't infer dual-port block RAM from HDL.  Arggh!) 

The problem is not just getting RAM inference, it is getting
all synthesis tools to accept the same code and produce
the same hardware semantic (similar enough in implemenation
so they function the same).

You will be happy to know that both VHDL (IEEE 1076.6) and
Verilog (IEEE 1364.1) have standardized modeling styles
that support RAM inference.

The next step is to get EDA vendors to implement these
standards.  When EDA vendors support a standard they are
making an investment.  They need to know their investment
is important and will get them a return.

The only way for an EDA vendor to know if a feature is
important is for their users to tell them it is important.
So while open standards/tools are important, I would
encourage all to take a breather and let your current
vendors know what is important to you.  A real good time
to do this is when you are renewing your maintence or
buying new licenses ($$$ tend to amplify your message).

Unfortunately IEEE standards are not published for free,
however, I have written a couple of papers on 1076.6 and
they are free available at:
     http://www.synthworks.com/papers

Cheers,
Jim

-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training             mailto:Jim@SynthWorks.com
SynthWorks Design Inc.           http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Article: 69402
Subject: Re: Easypath question (was "Hard-tocopy" rant)
From: Jim Lewis <Jim@SynthWorks.com>
Date: Mon, 10 May 2004 09:21:27 -0700
Links: << >>  << T >>  << A >>
acm wrote:
> Easypath = EasyScrap...
> 
> Hey, buy our excess scrapped inventory!!!!
> 
What is wrong with taking lemons and making Lemonade?

Xilinx has taken the enviromentally sound practice
of taking parts that would have otherwise gone to the
dump, making them into something useful, and selling
them.

To me this reflects engineering brillance.

This is a kind of cool situation:  give customers
a good price, make environmentalists happy,
and make stockholders happy all at the same time.

If this makes you unhappy, seek help :)

Cheers,
Jim
P.S.
Usually it takes environmental activists and an
act of congress to get people to do envionmentally
correct things.
-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training             mailto:Jim@SynthWorks.com
SynthWorks Design Inc.           http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Article: 69403
Subject: Monolithic state machine or structured state machine?
From: "vax,3900" <vax3900@yahoo.com>
Date: Mon, 10 May 2004 12:23:38 -0400
Links: << >>  << T >>  << A >>
I am designing a state machine that will be fit into a CPLD (Xilinx XC95xx).
The state machine needs to wait certain number of clockes here and there (
for example, 80 clockes here, and 160 clockes there ). If I design
everthing with hand, I whould choose structured state machine; that is, a
state machine plus a counter. But since I am using VHDL, and the compiler
would take care of everything, I think I might be able to make a monolithic
state machine with the counter built in ( that is, to add 80 states here,
and 160 states there ). Excluding the counter, the state machine has about
100 states.

My question is, which approach is better, for a CPLD? The monolithic design
will require less FF's, maybe. Have you guys met this question in your
projects?

Article: 69404
Subject: How to simulator XILINX CPLD with off_chip wiring?
From: "vax,3900" <vax3900@yahoo.com>
Date: Mon, 10 May 2004 12:28:16 -0400
Links: << >>  << T >>  << A >>
I have a question when I simulator my VHDL code after fitting. I would like
to connect an IO pin to GCK2 pin, another IO pin to GSR pin. Is there a way
to include those information in the simulation?

vax, 3900

Article: 69405
Subject: Re: Which board to buy? Status of open source tools?
From: tom1@launchbird.com (Tom Hawkins)
Date: 10 May 2004 09:36:23 -0700
Links: << >>  << T >>  << A >>
jon@beniston.com (Jon Beniston) wrote in message news:<e87b9ce8.0405070500.7c9c4bcc@posting.google.com>...
> > Also, what's the status of open source tools?  (I like to tinker on
> > the software end of things, too, and I have a bad case of PowerBook
> > envy, and I haven't seen any software available other than x86 and
> > big-iron UNIX).  Can they go from VHDL/Verilog all the way to
> > downloading the file to the chip?  I see that compilation (Icarus
> > verilog) and downloading (found it in this group's FAQ) work, but what
> > about place and route?  Icarus' docs say it's a no-go for this; is
> > there anything else, or must I use the Xilinx tools?  (I guess I have
> > a Xilinx bias -- it's all I've used, and I don't see much else for
> > cheap development boards.)
> 
> Why bother with Open Source stuff when various incarnations of
> commerical tools are free to use?

Because in the long term, an open-source tool chain can out perform a
commercial tool.  Case in point: how many Unix/C developers compile
with a commercial alternative to GCC?

Unfortunately, the track record of open-source FPGA implementation
tools has been dismal.  Icarus is the only open-source tool I know
that attempts Xilinx synthesis.  I believe it handles synthesis and
technology mapping, but has little, if no optimization.

I did start a Virtex2 packer/placer awhile back.  I got as far as
parsing the post-synthesis EDIF netlist and building a graph of FPGA
primitives.  The goal was to pack and place the CLBs, then update the
UCF with LOC constraints.  I still have the code lying around in case
anyone is interested.

BTW, Confluence can compile it for Mac X.  It will solved your design,
simulation, and verification problems, but for FPGA compilation,
you're still locked into commercial tools.

-Tom

Article: 69406
Subject: Re: Floating Point With Xilinx EDK (PPC)?
From: apple2ebeige@yahoo.com (Dave)
Date: 10 May 2004 10:38:35 -0700
Links: << >>  << T >>  << A >>
jon@beniston.com (Jon Beniston) wrote in message news:<e87b9ce8.0405100033.5813aa55@posting.google.com>...
> apple2ebeige@yahoo.com (Dave) wrote in message news:<d4aa8e8a.0405091311.76c6a81c@posting.google.com>...
> > I'm having trouble using floats with the PPC compiler.  Any inclusion
> > of floats produces a pretty indecipherable (to me) linker error.   I
> > tried -lm but that doesn't help.  Any ideas?  Thanks.
> > 
> > -Dave
> 
> Posting the error message might help..
> 
> Cheers,
> JonB

Jon-

So many messages spew out of the build process it's hard to tell what
might be relevant.  Below is the tail end.  Also, the project is the
Memec/Insight ultracontroller "Time of Day" design, which I believe
derives from a Xilinx example.  Thanks.

 .comment       0x00000104       0x34
/xygdrive/c/EDK/gnu/powerpc-eabi/nt/bin/../lib/gcc-lib/powerpc-eabi/2.95.3-4/../../../../powerpc-eabi/lib/libc.a(exit.o)
 .comment       0x00000138       0x34
/xygdrive/c/EDK/gnu/powerpc-eabi/nt/bin/../lib/gcc-lib/powerpc-eabi/2.95.3-4/../../../../powerpc-eabi/lib/libc.a(impure.o)
 .comment       0x0000016c       0x34
/xygdrive/c/EDK/gnu/powerpc-eabi/nt/bin/../lib/gcc-lib/powerpc-eabi/2.95.3-4/../../../../powerpc-eabi/lib/libc.a(strcpy.o)
 .comment       0x000001a0       0x34
/xygdrive/c/EDK/gnu/powerpc-eabi/nt/bin/../lib/gcc-lib/powerpc-eabi/2.95.3-4/../../../../powerpc-eabi/lib/libc.a(strlen.o)
 .comment       0x000001d4       0x34
/xygdrive/c/EDK/gnu/powerpc-eabi/nt/bin/../lib/gcc-lib/powerpc-eabi/2.95.3-4/libgcc.a(dp-bit.o)
 .comment       0x00000208       0x34
/xygdrive/c/EDK/gnu/powerpc-eabi/nt/bin/../lib/gcc-lib/powerpc-eabi/2.95.3-4/libgcc.a(fp-bit.o)
 .comment       0x0000023c       0x34
/xygdrive/c/EDK/gnu/powerpc-eabi/nt/bin/../lib/gcc-lib/powerpc-eabi/2.95.3-4/libgcc.a(_lshrdi3.o)
collect2: ld returned 1 exit status
make: *** [ppc405_1/code/executable.elf] Error 1
Done.

Article: 69407
Subject: Re: SAA7111 YUV
From: "claps" <clapiton@aol.com>
Date: Mon, 10 May 2004 14:06:58 -0400
Links: << >>  << T >>  << A >>
Hi,

I can help you with this issue by providing you transformation formulaes.

However, please note that the formula heavily depends on the settings of
the SAA7111A. AND NOBODY USUALLY TELLS YOU ABOUT THIS !!!

So :

1) what are the values of your registers 0B, 0C and 0D. Namely BRIG , CONT
and SATN ???

You have to understand that no mathematics will work unless you know how
you've set-up the chip.

Talk to you later,

Regards,

Claps


Article: 69408
Subject: Re: Monolithic state machine or structured state machine?
From: Jim Lewis <Jim@SynthWorks.com>
Date: Mon, 10 May 2004 11:15:32 -0700
Links: << >>  << T >>  << A >>
Hi,
 > But since I am using VHDL, and the compiler
 > would take care of everything, ...
The compilers are not as smart as you think.
They are good and take care of many tedious problems,
but there are things you still must manage.  My
opinion is that this is one of them.  I recomment that
you stay with your old approach.

Code all arithmetic resources separately from your
statemachine.  Synthesis & Optimization bring many reasons
for doing this.
1) Random logic (statemachines) and structured logic
(Arithmetic) are optimized using different synthesis
algorithms.  For some tools you may get better quality of
results if the arithmetic is in a separate entity (file).
2) Writing your code explicitly, the counters can be
shared explicitly.  This is even more important when the
counters are potentially different sizes (7 bits vs  8 bits).
It gets much more difficult (if not impossible) for a
synthesis tool to share resources that are different sizes.

When you are counting resources, don't forget your end detect
(zero detect) logic is a resource and should be coded separately
from your statemachine.

I have mostly used ASICs and FPGAs, so I cannot address the
specifics of a CPLD, but with a big statemachine, FPGA/CPLD tools
tend to make them one hot - one register bit per state.
With counters, there is one bit per log2 states.  With
ASICs and FPGAs, counters tend to be more efficient than
statemachines.

Cheers,
Jim

vax,3900 wrote:
> I am designing a state machine that will be fit into a CPLD (Xilinx XC95xx).
> The state machine needs to wait certain number of clockes here and there (
> for example, 80 clockes here, and 160 clockes there ). If I design
> everthing with hand, I whould choose structured state machine; that is, a
> state machine plus a counter. But since I am using VHDL, and the compiler
> would take care of everything, I think I might be able to make a monolithic
> state machine with the counter built in ( that is, to add 80 states here,
> and 160 states there ). Excluding the counter, the state machine has about
> 100 states.
> 
> My question is, which approach is better, for a CPLD? The monolithic design
> will require less FF's, maybe. Have you guys met this question in your
> projects?


-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training             mailto:Jim@SynthWorks.com
SynthWorks Design Inc.           http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Article: 69409
Subject: Re: One issue about free hardware
From: Bassman59a@yahoo.com (Andy Peters)
Date: 10 May 2004 11:22:21 -0700
Links: << >>  << T >>  << A >>
tom1@launchbird.com (Tom Hawkins) wrote in message news:<833030c0.0405100613.55cb6793@posting.google.com>...
> But oddly enough the biggest roadblock to open-source EDA is
> ourselves.  For some reason or another, there is an apparent lack of
> interest and motivation.

Perhaps the reason is that hardware guys don't have the skill sets to
create these tools?  I know that my attempts are writing even the
simplest programs for Windows and for Mac OS X are pretty lame, and
the learning curves are quite steep.  I mean, it took waaaay too long
for me to write a simple Mac OS X GUI program that sent a report to a
USB device when I clicked a button.  It's not that I don't know C -- I
use C for embedded micros all the time -- but the APIs for each OS
present a significant hurdle.

It's not that we can't learn how to do this.  I think it's simply a
matter of time and priorities.  Most FPGA engineers are designing
hardware for a living and there's simply not enough time in the day to
take on a major programming effort.

Contrast this to the (stereotype of the) open-source software
developer.  Linus Torvalds started writing Linux as a college student,
and a lot of open-source programmers are in (or got their start) in
university.  The student's motivations (beer, girls/boys hacking)
certainly differ from those of the professional engineer (paying the
mortgage, paying the car payment, paying the insurance, paying the
rest of the bills).  To be honest, I've never really understood the
motivation behind giving away one's work.

I would imagine that the skills required to write an effective
FPGA-fitting algorithm are beyond those of the typical open-source
hacker.  If such a hacker exists, then it seems to me (s)he'd be
better off working for Altera or Xilinx (or Mentor or Synplicity or
Synopsys) getting paid real money.

As as for "free" vs "open source" -- they ARE two different things. 
Obviously, I have no problems with either;  I depend on emacs as an
editor and I use Mozilla for web-browsing and e-mail.  However, I
don't particularly care if EDA tools are free OR open source.  I *do*
care if they don't work, or are inadequate, because I have work to do!
 Of course, I also care about "reasonably priced," since if I can't
afford the software, I can't afford the software.  A couple of years
ago, I looked into sdcc because the Keil 8051 compiler is expensive. 
However, sdcc simply didn't work, and it didn't look like there was
any active development happening, so I sprung for the Keil tools and
haven't looked back.

A common argument is "I'm a starving college student and I can't
afford to pay the $$$$ for FPGA tools."  A very valid argument, too,
at least in the old days, although the argument was weakened when
Brands A and X released their free tools.  Both have "university
programs."  Part of the cost of software is the support and I would
guess that the support staffs of A and X don't want to waste their
time answering newbie questions (hence, the web support stuff and the
newsgroups) when there are serious customers with serious concerns to
be addressed.

You mention Icarus Verilog.  I downloaded and installed the IVIonOSX
packaged, and was immediately frustrated.  (The open-source community
really needs to get its shit together regarding documentation!)  Plus,
the command-line iverilog wouldn't compile some V2001 code, which
makes it useless.  I suppose I could send Steven the offending code
and ask him to support whatever feature breaks things, or I suppose I
could hack the code myself and submit my patches to Steven.   As for
the former, that's laziness on my part, although Steven indicates that
V2001 support is limited.  As for the latter, IANAP!

To be honest, there's really no point in fussing with with this when I
can use the free (as in beer) Xilinx version of ModelSim.  Yes, it's
"limited" but for the simple things I do at home there isn't any real
penalty.

As for FPGA tools, I'm not sure whether the push for open-source tools
is about the cost of the tools, access to the source, or simply
because people want to run the tools on their Linux box.  (I'll wager
that Option 1 is the real reason.  Running on a Windows box is a
detail.)  I've always believed that you buy the computer (and install
the OS) that runs the software you need to do your job, rather than
trying to make do with inadequate tools because you have a moral or
idealogical viewpoint.

(Aside: Hey, Mentor Graphics, Xilinx and Altera: I hate Windows!  I
want you to write your software for Mac OS X!  Seriously!)

Finally, an argument FOR free FPGA tools.  These tools are a MEANS TO
AN END, not an end in themselves.  One uses X's FPGA tools ONLY
because they are going to buy a boatload of X's FPGAs, and for that
reason it makes sense to provide the software for free (but charge for
direct tech support).  Of course, the Real Big customers get the
software for free and buy enough chips to make 'em cheap; it's the
small guys who eat the cost of the software and pay more for the same
chips.

Don't get me started on that abomination known as FlexLM.

OK, I'm done.

--a

Article: 69410
Subject: Re: Which board to buy? Status of open source tools?
From: Anna Acevedo <acevedo@xilinx.com>
Date: Mon, 10 May 2004 12:05:05 -0700
Links: << >>  << T >>  << A >>
Digilent Inc  (www.digilentinc.com) has several low cost boards mainly
used in academia but available to all. Soon they will be releasing a
Spartan-3 board and in a couple of months a Virtex-II Pro board.

Anna Acevedo - Manager
Xilinx University Program

Joel Hardy wrote:

> Howdy all,
>
> I'm looking to get an FPGA development board sometime soon.  When I
> was in college, I played with what was probably the Xess XSB-300E (fun
> stuff: we made a  PCMCIA interface and plugged it into an iPaq... but
> that's another story).  That's WAY outside of my price range (<
> $200US), but the XSA-50 doesn't look too bad.  Any comments on that
> one?  Also, I found this
> (www.nuhorizons.com/products/xilinx/spartan3/development-board.html),
> which looks considerably better to me, especially since my main
> prospective project would benefit from a large amount of fast RAM.
> Any advice?  Is there anything else in the sub-$200 I should look at?
>
> Also, what's the status of open source tools?  (I like to tinker on
> the software end of things, too, and I have a bad case of PowerBook
> envy, and I haven't seen any software available other than x86 and
> big-iron UNIX).  Can they go from VHDL/Verilog all the way to
> downloading the file to the chip?  I see that compilation (Icarus
> verilog) and downloading (found it in this group's FAQ) work, but what
> about place and route?  Icarus' docs say it's a no-go for this; is
> there anything else, or must I use the Xilinx tools?  (I guess I have
> a Xilinx bias -- it's all I've used, and I don't see much else for
> cheap development boards.)
>
> Thanks for the help!
> - Joel Hardy


Article: 69411
Subject: Re: Monolithic state machine or structured state machine?
From: "James Morrison" <jamesndi2004@yahoo.ca>
Date: Mon, 10 May 2004 19:05:22 GMT
Links: << >>  << T >>  << A >>
Actually Jim, what you wrote below is not really true.  I'm most familiar with Xilinx tools but I've used Altera's in the past and I believe they work the same.

For FPGA's where there is an abundance of flip-flops state machines default to one-hot encoding.  However for CPLD's where there is lots of logic resources available but not many flip-flops the synthesis defaults to minimise the number of flip-flops used and encodes the state as bit patterns (usually gray codes).  It is possible to override this behaviour either by spelling out the state encoding specifically or by setting a tool option somewhere.

Personally, I separate the logic out from the state transitions normally for the following reasons:
1)  I find it easier to see where logic may be reused.  Synthesis takes care of this but its good to have a gut feel.
2)  I find it easier to understand when I come back to the design a long time later.  Having logic embedded into state transitions and definitions is confusing.  It may save a few resources and make something fit but if you can afford the small inefficienty (although that is debatable) the increase in maintainability is huge.

Just my $0.02.

James.

~

>>> Jim Lewis<Jim@SynthWorks.com> 5/10/2004 2:15:32 PM >>>
Hi,
I have mostly used ASICs and FPGAs, so I cannot address the
specifics of a CPLD, but with a big statemachine, FPGA/CPLD tools
tend to make them one hot - one register bit per state.
With counters, there is one bit per log2 states.  With
ASICs and FPGAs, counters tend to be more efficient than
statemachines.



Article: 69412
Subject: Re: Monolithic state machine or structured state machine?
From: Jim Lewis <Jim@SynthWorks.com>
Date: Mon, 10 May 2004 12:31:45 -0700
Links: << >>  << T >>  << A >>
James,
 > what you wrote below is not really true
Confusing way to start when you agree with the
the approach I recommended.   Ok so the correction
is only FPGA tools like one-hot, CPLD tools prefer
other implementations.

The key thing is that we both agree that be it an ASIC,
FPGA, or CPLD, code arithmetic resources (counters)
separately from the statemachines.

If you don't factor out arithmetic resources, then there
are both potential quality of result issues and
readability/reusability issues.

Cheers,
Jim


James Morrison wrote:
> Actually Jim, what you wrote below is not really true.  I'm most familiar with Xilinx tools but I've used Altera's in the past and I believe they work the same.
> 
> For FPGA's where there is an abundance of flip-flops state machines default to one-hot encoding.  However for CPLD's where there is lots of logic resources available but not many flip-flops the synthesis defaults to minimise the number of flip-flops used and encodes the state as bit patterns (usually gray codes).  It is possible to override this behaviour either by spelling out the state encoding specifically or by setting a tool option somewhere.
> 
> Personally, I separate the logic out from the state transitions normally for the following reasons:
> 1)  I find it easier to see where logic may be reused.  Synthesis takes care of this but its good to have a gut feel.
> 2)  I find it easier to understand when I come back to the design a long time later.  Having logic embedded into state transitions and definitions is confusing.  It may save a few resources and make something fit but if you can afford the small inefficienty (although that is debatable) the increase in maintainability is huge.
> 
> Just my $0.02.
> 
> James.
> 
> ~
> 
> 
>>>>Jim Lewis<Jim@SynthWorks.com> 5/10/2004 2:15:32 PM >>>
> 
> Hi,
> I have mostly used ASICs and FPGAs, so I cannot address the
> specifics of a CPLD, but with a big statemachine, FPGA/CPLD tools
> tend to make them one hot - one register bit per state.
> With counters, there is one bit per log2 states.  With
> ASICs and FPGAs, counters tend to be more efficient than
> statemachines.
> 
> 


-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training             mailto:Jim@SynthWorks.com
SynthWorks Design Inc.           http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Article: 69413
Subject: Re: How to perform a timing simulation in Modelsim with QuartusII output file ?
From: Bassman59a@yahoo.com (Andy Peters)
Date: 10 May 2004 13:46:21 -0700
Links: << >>  << T >>  << A >>
ALuPin@web.de (ALuPin) wrote in message news:<b8a9a7b0.0405100255.9edda8b@posting.google.com>...
> Hi newsgroup people,
> 
> I want to perform a timing simulation of an SRAM controller with
> Modelsim (version Altera 5.7e) 
>
> I am working with Altera QuartusII software (version 4.0 SP1).
> 
> For the purpose of a timing simulation under Modelsim I would like to
> know how to make settings in QuartusII to get the correct output files
> and how to include them in Modelsim.

I'm sure this is all documented somewhere, so it's clearly time to
RTFM.

Basically, the fitter spits out a Verilog or VHDL model of your
design.  This model has the port interface, but the innards are
replaced with the particular FPGA's low-level features and the proper
interconnects.  By default, Quartus puts this file in the
<design_root>\simulation\modelsim directory.  Look for designname.vo. 
You'll also find the SDF (delay file) in that directory; it's called
designname_v.sdo.

Back to modelsim.  Add the .vo file to your project, and compile it. 
[You may have to go in and edit out the line: initial
$sdf_annotate("designname_v.sdo"); ModelSim complains about it)  Then
edit the simulation configuration and tell it to use designname_v.sdo
with your chip design.  I like to set all of the delays to MAX (I've
been bitten by back-annotated simulations using "typical" delays.)

Like I said, I'm sure that Altera's documention can tell you how to do
this.

-a

Article: 69414
Subject: unused IO on SPARTAN-IIE
From: "Amontec Team, Laurent Gauch" <laurent.gauch@amontecDELETEALLCAPS.com>
Date: Mon, 10 May 2004 23:31:17 +0200
Links: << >>  << T >>  << A >>
HI all,

I am designing on a FG256 package.

I have a large part of unused IOs.
Is that better to fix the unused IOS to VCCO or to GND or can I let all 
unused IOs float?

Regards,
Laurent


Article: 69415
Subject: Re: SAA7111 YUV
From: gabor@alacron.com (Gabor Szakacs)
Date: 10 May 2004 15:04:27 -0700
Links: << >>  << T >>  << A >>
Philips publishes the algorithm they use in their own
media processors (PNX 1300 series).  See:
http://www.semiconductors.philips.com/acrobat/literature/9397/75009542.pdf
Chapter 14 talks about the image coprocessor and includes the algorithms.
> Wang Feng <fwang11@pub3.fz.fj.cn> wrote in message
> news:c4l7v6$rkf$1@news.yaako.com...
> >
> > Hi,
> >
> > I have stored YUV422 16 bit data from Philips SAA7111A. The Y data and UV
> > data
> > in 2 files. Now how to combine Y and UV
> > into RGB format for display on PC?
> >
> > Please reply to fwang11@pub3.fz.fj.cn
> >
> > Thanks in advance.
> >
> > Wang, Feng
> >
> >
> >

Article: 69416
Subject: Re: SAA7111 YUV
From: gabor@alacron.com (Gabor Szakacs)
Date: 10 May 2004 15:14:15 -0700
Links: << >>  << T >>  << A >>
Sorry I posted a link to the glossy sales literature.
The data sheet is at:

http://www.support.trimedia.philips.com/trimedia/Download/pnx1300-CQS.pdf

This has the algoriths in chapter 14

> Wang Feng <fwang11@pub3.fz.fj.cn> wrote in message
> news:c4l7v6$rkf$1@news.yaako.com...
> >
> > Hi,
> >
> > I have stored YUV422 16 bit data from Philips SAA7111A. The Y data and UV
> > data
> > in 2 files. Now how to combine Y and UV
> > into RGB format for display on PC?
> >
> > Please reply to fwang11@pub3.fz.fj.cn
> >
> > Thanks in advance.
> >
> > Wang, Feng
> >
> >
> >

Article: 69417
Subject: Re: unused IO on SPARTAN-IIE
From: Austin Lesea <austin@xilinx.com>
Date: Mon, 10 May 2004 15:17:44 -0700
Links: << >>  << T >>  << A >>
Laurent,

Unused IOs can be left floating, unless you would prefer to use them to 
help reduce ground bounce.  By programming an unused IO pin next to a 
group of output IO pins to a '0' (like a LVCMOS 24 mA) and connecting it 
to ground, one can reduce the ground bounce by about 20% (by reducing 
the inductance of the ground return).  Pins past the ones nearest those 
IO pins switching do not provide a further benefit.

Leaving some pins floating is always a good idea for testing, as these 
pins can be used to probe internal nodes during debug (if you do not use 
Chipscope, which captures everything through the JTAG port).

Connecting pins to Vcco and programming them to a '1' will also reduce 
Vcco bounce, but as Vcco bounce is hardly ever a concern, it is hardly 
ever used that way.

Austin

Amontec Team, Laurent Gauch wrote:
> HI all,
> 
> I am designing on a FG256 package.
> 
> I have a large part of unused IOs.
> Is that better to fix the unused IOS to VCCO or to GND or can I let all 
> unused IOs float?
> 
> Regards,
> Laurent
> 

Article: 69418
Subject: Re: Monolithic state machine or structured state machine?
From: mike_treseler@comcast.net (Mike Treseler)
Date: 10 May 2004 16:13:55 -0700
Links: << >>  << T >>  << A >>
vax3900 wrote:
 
>I am designing a state machine that will be fit into a CPLD (Xilinx XC95xx).
>The state machine needs to wait certain number of clocks here and there (
>for example, 80 clocks here, and 160 clocks there ). If I design
>everything with hand, I would choose structured state machine; that is, a
>state machine plus a counter. But since I am using VHDL, and the compiler
>would take care of everything, I think I might be able to make a monolithic
>state machine with the counter built in ( that is, to add 80 states here,
>and 160 states there ).

Consider making the counter a separate 
variable. Saying n:= n + 1 in a
few places is much cleaner than 
describing hundreds of extra state transitions.

I said variable because I would write
this controller in a single process.
A counter signal and multiple processes would 
work fine too.

> Excluding the counter, the state machine has about
> 100 states.

See if you can't pull out a few other
count, shifter, mode or boolean variables to reduce
the number of states and clarify
the logic description.

>My question is, which approach is better, for a CPLD? The monolithic design
>will require less FF's, maybe.

Maybe, maybe not. 
To answer the utilization question, you would have
to try it both ways and see. I would expect
little difference. 

I have found that a clean description is a likely to
fit as any other.

    -- Mike Treseler

Article: 69419
Subject: Re: SAA7111 YUV
From: Jan Panteltje <pNaonStpealmtje@yahoo.com>
Date: Mon, 10 May 2004 23:15:00 GMT
Links: << >>  << T >>  << A >>
On a sunny day (10 May 2004 15:14:15 -0700) it happened gabor@alacron.com
(Gabor Szakacs) wrote in <8a436ba2.0405101414.243d7b94@posting.google.com>:

>Sorry I posted a link to the glossy sales literature.
>The data sheet is at:
>
>http://www.support.trimedia.philips.com/trimedia/Download/pnx1300-CQS.pdf
>
>This has the algoriths in chapter 14
panteltje:~/download/html# wget http://www.support.trimedia.philips.com/trimedia/Download/pnx1300-CQS.pdf
--01:13:57--  http://www.support.trimedia.philips.com/trimedia/Download/pnx1300-CQS.pdf
           => `pnx1300-CQS.pdf'
Connecting to www.support.trimedia.philips.com:80... connected!
HTTP request sent, awaiting response... 401 Authorization Required
Connecting to www.support.trimedia.philips.com:80... connected!
HTTP request sent, awaiting response... 401 Authorization Required
Authorization failed.
JP


Article: 69420
Subject: Re: Floating Point With Xilinx EDK (PPC)?
From: Siddharth Rele <siddharth.rele@xilinx.com>
Date: Mon, 10 May 2004 17:24:46 -0700
Links: << >>  << T >>  << A >>
Hi Dave:

Have you tried using the -lc -lm -lc instead of -lm ? If this does not 
fix your problem, could you send the entire error log instead of just a 
snippet.

Thanks
Sid

Dave wrote:
> jon@beniston.com (Jon Beniston) wrote in message news:<e87b9ce8.0405100033.5813aa55@posting.google.com>...
> 
>>apple2ebeige@yahoo.com (Dave) wrote in message news:<d4aa8e8a.0405091311.76c6a81c@posting.google.com>...
>>
>>>I'm having trouble using floats with the PPC compiler.  Any inclusion
>>>of floats produces a pretty indecipherable (to me) linker error.   I
>>>tried -lm but that doesn't help.  Any ideas?  Thanks.
>>>
>>>-Dave
>>
>>Posting the error message might help..
>>
>>Cheers,
>>JonB
> 
> 
> Jon-
> 
> So many messages spew out of the build process it's hard to tell what
> might be relevant.  Below is the tail end.  Also, the project is the
> Memec/Insight ultracontroller "Time of Day" design, which I believe
> derives from a Xilinx example.  Thanks.
> 
>  .comment       0x00000104       0x34
> /xygdrive/c/EDK/gnu/powerpc-eabi/nt/bin/../lib/gcc-lib/powerpc-eabi/2.95.3-4/../../../../powerpc-eabi/lib/libc.a(exit.o)
>  .comment       0x00000138       0x34
> /xygdrive/c/EDK/gnu/powerpc-eabi/nt/bin/../lib/gcc-lib/powerpc-eabi/2.95.3-4/../../../../powerpc-eabi/lib/libc.a(impure.o)
>  .comment       0x0000016c       0x34
> /xygdrive/c/EDK/gnu/powerpc-eabi/nt/bin/../lib/gcc-lib/powerpc-eabi/2.95.3-4/../../../../powerpc-eabi/lib/libc.a(strcpy.o)
>  .comment       0x000001a0       0x34
> /xygdrive/c/EDK/gnu/powerpc-eabi/nt/bin/../lib/gcc-lib/powerpc-eabi/2.95.3-4/../../../../powerpc-eabi/lib/libc.a(strlen.o)
>  .comment       0x000001d4       0x34
> /xygdrive/c/EDK/gnu/powerpc-eabi/nt/bin/../lib/gcc-lib/powerpc-eabi/2.95.3-4/libgcc.a(dp-bit.o)
>  .comment       0x00000208       0x34
> /xygdrive/c/EDK/gnu/powerpc-eabi/nt/bin/../lib/gcc-lib/powerpc-eabi/2.95.3-4/libgcc.a(fp-bit.o)
>  .comment       0x0000023c       0x34
> /xygdrive/c/EDK/gnu/powerpc-eabi/nt/bin/../lib/gcc-lib/powerpc-eabi/2.95.3-4/libgcc.a(_lshrdi3.o)
> collect2: ld returned 1 exit status
> make: *** [ppc405_1/code/executable.elf] Error 1
> Done.


Article: 69421
Subject: Re: Which board to buy? Status of open source tools?
From: rickman <spamgoeshere4@yahoo.com>
Date: Mon, 10 May 2004 20:32:25 -0400
Links: << >>  << T >>  << A >>
Tom Hawkins wrote:
> 
> jon@beniston.com (Jon Beniston) wrote in message news:<e87b9ce8.0405070500.7c9c4bcc@posting.google.com>...
> > > Also, what's the status of open source tools?  (I like to tinker on
> > > the software end of things, too, and I have a bad case of PowerBook
> > > envy, and I haven't seen any software available other than x86 and
> > > big-iron UNIX).  Can they go from VHDL/Verilog all the way to
> > > downloading the file to the chip?  I see that compilation (Icarus
> > > verilog) and downloading (found it in this group's FAQ) work, but what
> > > about place and route?  Icarus' docs say it's a no-go for this; is
> > > there anything else, or must I use the Xilinx tools?  (I guess I have
> > > a Xilinx bias -- it's all I've used, and I don't see much else for
> > > cheap development boards.)
> >
> > Why bother with Open Source stuff when various incarnations of
> > commerical tools are free to use?
> 
> Because in the long term, an open-source tool chain can out perform a
> commercial tool.  Case in point: how many Unix/C developers compile
> with a commercial alternative to GCC?

I have been evaluating tools for the ARM MCU and all my info says that
gcc is a less efficient tool than the commercial ones.  I guess it only
stands to reason that the commercial tools must be better, why else
would they sell well enough to keep the companies in business?  


> Unfortunately, the track record of open-source FPGA implementation
> tools has been dismal.  Icarus is the only open-source tool I know
> that attempts Xilinx synthesis.  I believe it handles synthesis and
> technology mapping, but has little, if no optimization.

I think John Jakson summed it up pretty well, open source FPGA tools are
not practical for a number of reasons that have been discussed here many
times before.  Some people seem to think that FPGA and ASIC tools are
the same as compiliers, but in reality they are very different.  


> I did start a Virtex2 packer/placer awhile back.  I got as far as
> parsing the post-synthesis EDIF netlist and building a graph of FPGA
> primitives.  The goal was to pack and place the CLBs, then update the
> UCF with LOC constraints.  I still have the code lying around in case
> anyone is interested.
> 
> BTW, Confluence can compile it for Mac X.  It will solved your design,
> simulation, and verification problems, but for FPGA compilation,
> you're still locked into commercial tools.

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 69422
Subject: Re: VHDL Beginner: Reset a counter (instead of "000000000....000000") - better way ?
From: "jtw" <wrightjt @hotmail.invalid>
Date: Tue, 11 May 2004 02:40:10 GMT
Links: << >>  << T >>  << A >>
Allan & Jason B. show the typical ways; alternatively, if you are using
numeric_std, you could write:

    counter <= std_logic_vector(to_unsigned(0,27));

I have found this format useful on occasion where I want to load a constant
that is not all 0's or all 1s.

Jason T. Wright

"Allan Herriman" <allan.herriman.hates.spam@ctam.com.au.invalid> wrote in
message news:3fot909ludqtgfrf8r9q7bs09p29fbqssm@4ax.com...
> On Sun, 9 May 2004 22:40:10 +0200, "Martin Maurer" <capiman@clibb.de>
> wrote:
>
> >Hello,
> >
> >i have a counter which is 27 bit long.
> >
> >signal counter : STD_LOGIC_VECTOR(26 downto 0);
> >
> >Is there a "better" way to reset than counter <= "00000000...00000" ?
> >Something like counter <= 0 (26 downto 0) or counter <= 0 ?
>
>
> counter <= (others => '0');
>
> This is in the comp.lang.vhdl FAQ,
> http://www.vhdl.org/comp.lang.vhdl/
> http://www.vhdl.org/comp.lang.vhdl/FAQ1.html#const_vectors
>
> Regards,
> Allan.



Article: 69423
Subject: Re: is it possible to design usb only with fpga?
From: "jtw" <wrightjt @hotmail.invalid>
Date: Tue, 11 May 2004 02:43:14 GMT
Links: << >>  << T >>  << A >>
Not if I recall correctly.  There are specific rise/fall-time requirements
(and I forget what else) that FPGA I/Os don't support (or at least, didn't.)

Jason T. Wright

"rat" <rattt@col.edu.cn> wrote in message
news:c7kjvf$2l0m$1@mail.cn99.com...
> Hi,
>   Is it possible to make a USB 1.1 interface only with FPGA chip, I mean,
> without addtional transceiver chip?
>   Thanks a lot!
>
> Regards,
> rat



Article: 69424
Subject: Re: Serial Data Capture
From: "Weddick" <weddick@comcast.net>
Date: Tue, 11 May 2004 03:40:09 GMT
Links: << >>  << T >>  << A >>
Thanks for the response.  Your description on the data is correct.  The
enable is active for the whole 32 bits of data, then goes low for one clock
and then starts over again.  I'll check out the VHDL group also.

Joel

"Marc Randolph" <mrand@my-deja.com> wrote in message
news:l7adnSaEOovP6gLdRVn-gQ@comcast.com...
> Weddick wrote:
> > It's been 20 plus years since I did any real design work.  I currently
am
> > starting to learn VHDL in order to create a design that will capture
serial
> > data.  The serial interface I need to capture data from consists of a 1
Mhz
> > Clock, Data (32 bits) and Enable signals.
> >
> > Any help on where to look for examples or how to get started would be
> > appreciated.  If this is the wrong news group, let me know.
>
> Howdy Joel,
>
>      The fpga and VHDL news groups seem to support each other sometimes.
>   This sounds like a purely VHDL question, unless you're trying to do
> something fancy or tricky with the FPGA to solve your problem.
>
> You'll probably need to provide a better description of your data stream
> to get a good answer on what you need.  For example, is the enable like
> a sync pulse, where it occurs once per 32 bits, or is it active for each
> bit that is valid?  If it happens on every bit, how is your circuit
> supposed to know which bit on the serial line is to be the MSB of the 32
> bit word?  Is there a framing sequence in the data?
>
> The fact that the clock is sent along with the data makes this a
> relatively straight forward problem.  If the enable bit is sent once per
> 32 bits, it could pre-set a synchronous counter which counts down to 0.
>   The counter could be used to index into a std_logic_vector(31 downto
> 0),  and when it hit zero, you will have a 32 bit word ready to work
> with (latch into a second set of flip flops).
>
>     Marc





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