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Hi Colin, Spurious interrupts occur when Nios is interrupted before a handler has been installed. Open the generated excalibur.h (under *_sdk/inc) and look the *_irq definition which is assigned 28. This will tell you what source is causing that interrupt. Why it's being generated is the question ... if it's an interrupt driven by I/O, it could be a floating pin or any number of things. Check the Quartus compile results to make sure all the pins are defined for starters. To help debugging, or at least allow you to use the system until you find the problem, you can disable spurious interrupt trapping by double-clicking Nios in SOPC Builder, click the software tab, disable the option, and rebuild. HTH, -- Pete csim036@ec.auckland.ac.nz (Colin) wrote in message news:<eeab73c0.0406291629.38bb526b@posting.google.com>... > Hi, > > I'm trying to use the Nios Ethernet Development Kit to run a simple > example program, it build fine, but when I run it it comes up with a > "spurious interrupt number: 0000 001C" error. Does anyone know how to > solve this problem. > > I'm using the Excalibur Apex development board, Nios 3.0, and the Nios > Ethernet Development Kit 2.0. > > Thanx.Article: 70851
If anyone can offer help with this (or a pointer to a more suitable forum) it
would be greatly appreciated. I am posting here because I know there is some
some folks with expertise who frequent this group (and we're using a Xilinx core
:)).
We are attempting to perform 64B burst PCI-X DMA write transfers from our add-in
card into host memory on a dual Xeon system.
Our linux device driver (kernel 2.24.x/2.26.x) is notified via an interrupt &
single dword "doorbell" write that the larger 64B entry is available for processing.
The order of operation on the PCI-X bus is as follows:
64B data write --> 4B doorbell write --> interrupt.
Upon receiving the interrupt, the device driver polls the location in memory
where the 4B doorbell write is expected to show up. Once he sees the doorbell
location written, he reads the 64B data location. PCI ordering should guarantee
that the 64B data location is written to system memory before the 4B doorbell
write is.
The above writes are performed as Memory Write Block transactions (we have also
tried Memory Write transactions), the No Snoop bit is cleared, and the Relaxed
Ordering bit is cleared.
We consistently encounter a situation where the device driver correctly receives
the interrupt & single dword doorbell write, but the 64B write fails to appear
in memory. Instead, the device driver reads a stale 64B block of data (data from
the last successful DMA write).
As a debug measure, we had the FPGA on our add-in card perform a readback
(Memory Read Block) of the 64B entry immediately after writing it. We obeserved
that the data read back was stale and matched the stale data that the device
driver saw. Eg:
1) Location 0xABCDEF00 is known to contain stale 64B data 0xAAAA....AAAA.
1) FPGA does Memory Write Block 64B 0xBBBB....BBBB at address 0xABCDEF00.
2) FPGA does Memory Read Block 64B at address 0xABCDEF00 (Split esponse).
3) Split Completion is returned by bridge with data 0xAAAA....AAAA.
This appears to be a violation of PCI ordering rules. Again, the No Snoop and
Relaxed Order bits are cleared for all of these transactions.
The device driver *never* writes to the 64B location, so there should be no
possibility of a collision occurring where he writes/flushes stale data that
overwrites the incoming DMA write.
This tells me that the location is NOT getting written because, according to PCI
ordering rules, the FPGA read *must* push the Memory Write Block into system
memory before reading back the location.
We observe this behaviour in dual Xeon systems with both the Intel E7501 chipset
and the Broadcom Serverworks GC-LE chipset.
We observe this in SMP and single processor configurations.
When bus traffic is light at 133MHz, or whenever the bus is running at 66MHz, we
do *not* observe this problem. We occasionally observe the problem when the bus
is running at 100MHz with heavy traffic. This suggests that we are hitting a
narrow timing window at higher bus speeds.
We are suspicious that we might be encountering a cache errata in the Xeon, and
are wondering if anyone can confirm this and possibly provide a workaround?
We've been banging our heads on this for a couple of weeks now.
Mark
Article: 70852I am looking for a FPGA Development Board, with a FPGA that supports fully asynchronous RAMs. I know that Altera APEX20k supports fully asynchronous RAMs. Are there also Xilinx FPGAs that provide this functionality (large FPGAs like the APEX20K1000C or APEX20K1500E)? regards GottfriedArticle: 70853
Hi Markus, The "Equations section (Compilation Report)" section in Quartus Help seems to provide a fairly complete description. -- Pete news:<40E18B51.9040206@web.de>... > Hi, > > Altera Quartus-II produces *.eqn files. Does anyone know where I can > find a detailed description of this fileformat? > > Thanks, Markus.Article: 70854
If you need small RAMs, sure! But small is the key word. The two types of memory in the Xilinx devices are BlockRAMs which require the clock for the read and CLB SelectRAM distributed memory. In the Virtex-II and Virtex-IIPro devices support up to 128 bit depth for single port memories or 64 bit for dual port. The memories can be any width, distributed throughout the logic fabric. While BlockRAMs are more efficient, supplying 18kbit chunks, they require a clock to get the read value. The CLB SelectRAMs are fully asynchronous read. You still need an edge for the write - the write pulse is generated internally from the supplied edge - but you have the asynchronous nature you just *have* to have. "Fuchs Gottfried" <fuchs@ecs.tuwien.ac.at> wrote in message news:40E2DB28.20501@ecs.tuwien.ac.at... > I am looking for a FPGA Development Board, with a FPGA that supports > fully asynchronous RAMs. I know that Altera APEX20k supports fully > asynchronous RAMs. > Are there also Xilinx FPGAs that provide this functionality (large FPGAs > like the APEX20K1000C or APEX20K1500E)? > > regards > Gottfried >Article: 70855
Xilinx has a Spartan-3 kit selling for $99, via their web site. Price from Insight (UK) will be 70 GBP, but they don't know when they will be in stock. Leon -- Leon Heller, G1HSM http://www.geocities.com/leon_hellerArticle: 70856
I'm new to this, and momentarily baffled. Some time ago, I bought an inexpensive programmer to work with PALs; it worked fine for that project. Today, I'm working with Lattice GAL22V10Ds and find that the programmer can't write to them, despite the documentation's claim that it handles GAL22V10 and GAL22V10As, although it can read and verify parts programmed elsewhere. The programmer manufacturer says that the timing table is different for the D-suffix part. They say their programmer "... can write the left 32 columns of data to GAL22V10D, [but] the right 8 columns can not be written by using GAL22V10A's timing table." That might be so, but _I_ can successfully write to GAL22V10Ds using GALBlast.exe, a simple home-built parallel-port adapter, and two power supplies. GALBlast reads the PES to determine at least one timing parameter and displays the programming voltage that the part needs. I assume the programmer does the same, but it merely erases the part, apparently can't write and, of course, fails to verify. My current project is back on track, but I'm concerned that I don't understand something fundamental here. Does someone have a better understanding of why this might be so? TIA. TomArticle: 70857
"Chris Carlen" <crcarle@BOGUS.sandia.gov> wrote in message news:cbt2af01rlh@news3.newsguy.com... > Kevin Neilson wrote: > > Chris, > > The format of the text file has to be in hex bytes, like this: > > ff // first byte > > ff ff // second and third byte > > aa bb cc // more bytes > > > > You can't use the 4'hf notation of Verilog. > > You can get more flexibility by using the Verilog 2001 I/O commands. > > -Kevin > > > Thanks for the input. > > Using the tip provided by Duane Clark, I have fixed the syntax error. I > simply needed to use an initial statement. > > But while my compiler is no longer reporting a syntax error, I have yet > to run a sim and verify that the data is correctly read. > > So I will have to confirm what you are saying later. But if you are > correct, then I will need this part of the picture too, so thanks! > > Where can I learn about these Verilog 2001 IO commands? Are they > implemented in Modelsim? I have read the documentation a little bit. > I'll have to look in there some more. > > Good day! > I don't know if you'll have luck finding help in the Modelsim documentation. That will tell you what commands are implemented, but not how to use them. I think the best bet may be to get out a C book and look up 'fscanf' and 'getc' and such. I think the Verilog commands are supposed to operate just like the C ones. -KevinArticle: 70858
Markus Koechy <markus.koechy@web.de> wrote in message news:<40E18B51.9040206@web.de>... > Hi, > > Altera Quartus-II produces *.eqn files. Does anyone know where I can > find a detailed description of this fileformat? > > Thanks, Markus. Hi Markus, The Quartus on-line help describes the eqn format. Do a search for "equations" and you'll see a bunch of help. The best format overview is in "Equations Section (Compilation Report)". Vaughn AlteraArticle: 70859
Xilinx LUT-RAMs read asynchronously and write synchronously (clocked). Xilinx BlockRAMs perform read and write operations synchronously (clocked). In most situations, clocked operation is preferrable and inherently more reliable. Peter Alfke > From: Fuchs Gottfried <fuchs@ecs.tuwien.ac.at> > Newsgroups: comp.arch.fpga > Date: Wed, 30 Jun 2004 17:24:24 +0200 > Subject: FPGA with fully asynchronous RAM > > I am looking for a FPGA Development Board, with a FPGA that supports > fully asynchronous RAMs. I know that Altera APEX20k supports fully > asynchronous RAMs. > Are there also Xilinx FPGAs that provide this functionality (large FPGAs > like the APEX20K1000C or APEX20K1500E)? > > regards > Gottfried >Article: 70860
Tim wrote: > Brian Philofsky wrote: > >>Finding the right answer record is not always easy as there >>is a lot of information available there but if you type in >>the right key words, it generally comes out in the top few >>and should not be too hard to find. > > > But nowhere near as easily as if you had a Google-style search > interface. Searching answers at X is absurdly difficult unless > you are in the priesthood. > > For me, it is generally not too difficult to find what I want there but I generally have a good idea what to type to get it. In other words, I have enough knowledge about what I am searching for to type in the correct keywords and the practice using the system and understanding the search tips (http://www.xilinx.com/support/tips.htm) to get the right items to show up to the top (and I didn't even realize I have joined the priesthood). I realize that I may not be the typical user of this resource though so it is always good to hear from others. It is my understanding that people within Xilinx are actively looking at the search engine for improvements but what would help is a little more information on how people are using it. If you are searching for something and do not find it, spend a few moments to notify Xilinx about this and give the specifics about how you were attempting to get that information. Sending this feedback can be as easy as clicking on the first Answer record that pops up, select the Feedback link and let them know what you typed, what you are looking for, the fact you could not easily find it and that this was the first answer record displayed but unrelated to what you were trying to find. It is this specific information that will likely best help in improving the search engine more-so that just telling us it is difficult to find information. This really should not take much time to do and hopefully that feedback will improve the search in the future and end up giving back that time and then some by better displaying the appropriate information more quickly. -- BrianArticle: 70861
That's because $99 / 1.81 = £55. Cheers, Syms. "Leon Heller" <leon_heller@hotmail.com> wrote in message news:40e2e1f9$0$291$cc9e4d1f@news-text.dial.pipex.com... > Xilinx has a Spartan-3 kit selling for $99, via their web site. Price from > Insight (UK) will be 70 GBP, but they don't know when they will be in stock. > > Leon > -- > Leon Heller, G1HSM > http://www.geocities.com/leon_heller > >Article: 70862
>But nowhere near as easily as if you had a Google-style search >interface. Searching answers at X is absurdly difficult unless >you are in the priesthood. Doesn't real google work? An amazing number of sites think their slow/dumb search kludge is useful. I didn't think Xilinx had made that bluder. I know I find lots of things on their site via google, but I'm not sure about the answers section. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 70863
Kevin Neilson wrote: > "Chris Carlen" <crcarle@BOGUS.sandia.gov> wrote in message > news:cbt2af01rlh@news3.newsguy.com... > >>Where can I learn about these Verilog 2001 IO commands? Are they >>implemented in Modelsim? I have read the documentation a little bit. >>I'll have to look in there some more. >> >>Good day! >> > > I don't know if you'll have luck finding help in the Modelsim documentation. > That will tell you what commands are implemented, but not how to use them. > I think the best bet may be to get out a C book and look up 'fscanf' and > 'getc' and such. I think the Verilog commands are supposed to operate just > like the C ones. -Kevin > > If all you are planning to do is read in binary or hex data from an external file, I find the $readmemb and $readmemh command much easier to use. Since they are Verilog95, most simulators support it and the reading of the data for these commands can be done in a couple of lines in the testbench without too much thought. The newer Verilog 2001 file commands take a bit more thought and more typing to get to work but do give added flexibility, especially if you want to read something other than binary/hex, need to parse the file, need to write/update the file or do anything more advanced than simply reading data and storing in an array. Also, if you are reading in a lot of data, the new commands can be more memory efficient since you can read in pieces at a time however doing so can also slow down simulation since every time you go to the disk to get or write information can stall the simulation from operating at full speed (similar to going to swap/paging when you run low on memory). In general though, anytime you read/write to a file, you can slow down simulation so I generally try to use sparingly. In terms of ModelSim support, it depends on which version of simulator you are using. From the original post, it looks like Chris is using 5.7c which I am fairly sure supports most of the Verilog 2001 file I/O commands. There is is a section in the new 6.2i Language Templates that also explains the use of these new commands at: Verilog --> Simulation Constructs --> System Tasks and Functions --> File I/O --> Read/Write to a File. There should be enough information to get someone started with this but may take a little trial and error to get fully working the way you intend to use it (at least that is how it usually works for me). On a related but slightly off-topic note, Chris mentions that he is using 5.2i but using 5.7c of ModelSim-XE. If memory serves, 5.7c was the version of ModelSim-XE designed to be used with 6.1i. It is important to keep the MTI-XE release in sync with the ISE version used because MTI-XE comes with pre-compiled libraries for the version of ISE it is released with. It is possible problems can arise later when post-translate, post-map or post-par (timing) simulation is performed as the simulation netlist will be created by 5.2i but the pre-compiled libraries are for 6.1i if MTI-XE 5.7c is used. Since updates are periodically necessary in the timing parameters and interfaces to the models, it is never suggested to mix netlists generated with one version of ISE with libraries from another. Good luck, -- BrianArticle: 70864
The Xilinx online store has stock will ship boards to practically anywhere on this planet. Payment is by credit card so you receive the exchange rate offered by your bank. However, shipping and local taxes do apply. Any difference charged by your local distributor is likely import duties, taxes, and fees charged by the applicable governing body (pesky governments). --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/II/IIE FPGAs http://www.xilinx.com/spartan3 --------------------------------- Spartan-3: Make it Your ASIC "Symon" <symon_brewer@hotmail.com> wrote in message news:2kg8l9F1v8isU1@uni-berlin.de... > That's because $99 / 1.81 = £55. > Cheers, Syms. > "Leon Heller" <leon_heller@hotmail.com> wrote in message > news:40e2e1f9$0$291$cc9e4d1f@news-text.dial.pipex.com... > > Xilinx has a Spartan-3 kit selling for $99, via their web site. Price from > > Insight (UK) will be 70 GBP, but they don't know when they will be in > stock. > > > > Leon > > -- > > Leon Heller, G1HSM > > http://www.geocities.com/leon_heller > > > > > >Article: 70865
pinod01@sympatico.ca (Pino) wrote in message news:<b7ed9648.0406291101.30563548@posting.google.com>... <snip> > > tri_state_bridge_0/avalon_slave is not connected to any Master. > Please connect it to a master of type avalon. > > Note that the Master peripheral defined is of type avalon and so is > the SDRAM controller (as defined within the Memory devices in the > System Contents directory tree). > > Can someone explain how I can properly connect a Master peripheral > (user-defined of course) to the SDRAM controller slave? Why does the > tristate bridge not allow this connection to occur? > > P.S. If this same excercise is done using a NIOS processor master + > tristate bridge + SDRAM controller everything is connected with no > errors. The only difference that I see is that my Master is a > user-defined peripheral. > > > Regards, > Pino Hi Pino, I believe the problem here is because of the various ways you can construct a system with SDRAM. First, are you using Altera's SDRAM controller that comes with Nios/SOPC Builder? Our controller has two modes of operation with respect to its external pins: 1. No pin 'sharing'. This is the default behavior, and is what you'd select if your board had I/O pins dedicated to SDRAM and SDRAM only. In this mode, your master (or a CPU) connects directly to the SDRAM controller. There should be no tri-state bridge in between (in fact, SOPC Builder shouldn't let you make this connection legally, perhaps this is where the issue is...) 2. SDRAM controller shares some of its pins with a tri-state bus. This allows you to save FPGA I/O if your system also has some other external memory (Flash, SRAM, etc.). Specifically the dq/dqm/address pins are shared. This is activated with a checkbox in the SDRAM controller GUI in SOPC Builder. In this mode, Avalon masters *must also* directly connect to the controller (your logic, Nios, etc.), but in addition, there will be a "More <sdram name> Settings" Page in SOPC Builder that appears, and allows you to choose which (if more than one) tri-state bridge you wish to route the shared I/O through. In this case, the Avalon master/slave connections you make will be similar to the first mode I described above: The master (your logic) would connect directly to the SDRAM controller, in addition to the tri-state bridge. I just made a simple test-case to verify this using QII4.0/SOPCB4.0 and it generates fine/no warning messages. If you want, feel free to email me and I will send you the system's files. Jesse Kempa Altera Corp. jkempa at altera dot comArticle: 70866
Hi Gottfried, I assume you're talking about on chip RAM? If so, I respectfully suggest that you don't need asynchronous RAMs at all. What you do need to do is think harder about your application! You'll have a more robust solution if you keep everything synchronous. cheers, Syms. "Fuchs Gottfried" <fuchs@ecs.tuwien.ac.at> wrote in message news:40E2DB28.20501@ecs.tuwien.ac.at... > I am looking for a FPGA Development Board, with a FPGA that supports > fully asynchronous RAMs. I know that Altera APEX20k supports fully > asynchronous RAMs. > Are there also Xilinx FPGAs that provide this functionality (large FPGAs > like the APEX20K1000C or APEX20K1500E)? > > regards > Gottfried >Article: 70867
Just wonder - Is there any chance the same board will be loaded with a bigger chip ? lukasz Steven K. Knapp wrote: > The Xilinx online store has stock will ship boards to practically anywhere > on this planet. Payment is by credit card so you receive the exchange rate > offered by your bank. However, shipping and local taxes do apply. > > Any difference charged by your local distributor is likely import duties, > taxes, and fees charged by the applicable governing body (pesky > governments). > --------------------------------- > Steven K. Knapp > Applications Manager, Xilinx Inc. > General Products Division > Spartan-3/II/IIE FPGAs > http://www.xilinx.com/spartan3 > --------------------------------- > Spartan-3: Make it Your ASIC > > > > "Symon" <symon_brewer@hotmail.com> wrote in message > news:2kg8l9F1v8isU1@uni-berlin.de... > >>That's because $99 / 1.81 = £55. >>Cheers, Syms. >>"Leon Heller" <leon_heller@hotmail.com> wrote in message >>news:40e2e1f9$0$291$cc9e4d1f@news-text.dial.pipex.com... >> >>>Xilinx has a Spartan-3 kit selling for $99, via their web site. Price > > from > >>>Insight (UK) will be 70 GBP, but they don't know when they will be in >> >>stock. >> >>>Leon >>>-- >>>Leon Heller, G1HSM >>>http://www.geocities.com/leon_heller >>> >>> >> >> > >Article: 70868
"rat" <rattt@col.edu.cn> wrote in message news:<cbt6sg$2p58$1@mail.cn99.com>... > Hi,friends > I am designing a pci target interface with cpld. And I want to meet the > 66Mhz pci timing requirement with lattice's ispMACH 4256V-5 (Tpd=5ns). It > seems that it is hard to meet the Tsu (<= 3ns) requirement with all of the > input pins. One way is to register every signal at the input side, just like > pipeline. But is it possible to register the IRDY signal? from my > understanding, I have to check the IRDY every clock phase in a transaction > to see if the data is valid to send or receive, and the target has to > respond immediately ( from example, in a single data phase read transaction, > once irdy is asserted and data is valid at some posedge of clock, we should > deassert the trdy signal immediately) > Any suggestion is welcome:) Thanks! > > Regards > > BTW: is the performance of the Altera QuartusII web edition worse than ISE > webpack or Lattice's tool? I synthesize the same design in Quartus and > Lattice's ispLevel starter ( with synplicity lattice edition), in Quartus, > the device choosed is max3128a-5, in ispLevel, device is ispMACH4128v-5. But > the timing analysis result is so different, ispMACH is better. What is the > problem? Hi, I do not believe it is possible to register all the PCI inputs, nor the IRDY signal, for PCI. I've never seen anyone do this. Every PCI core I've ever seen has logic between many pins and the first bank of registers, and IRDY and TRDY are two of the critical signals given their high fanout. This does result in very tight Tsu timing, but that's fundamental to the standard. The MAX 7000A family is not 66 MHz PCI compliant. To get to 66 MHz, you have to use the faster MAX 7000B family. Vaughn AlteraArticle: 70869
Steven K. Knapp wrote: > The Xilinx online store has stock will ship boards to practically > anywhere on this planet. Alightly off-topic, but it would be really really helpful if the online store could move into the 20th century and start selling FPGAs. No need to stock all speed grades or compete on price. And, as I've said before, if X management don't want to handle this, subcontract it to Amazon or DigiKey or whoever. Just make it possible for designers to order prototype quantities without going through the distributor tarpit - it would help your overall business.Article: 70870
csim036@ec.auckland.ac.nz (Colin) wrote in message news:<eeab73c0.0406291629.38bb526b@posting.google.com>... > Hi, > > I'm trying to use the Nios Ethernet Development Kit to run a simple > example program, it build fine, but when I run it it comes up with a > "spurious interrupt number: 0000 001C" error. Does anyone know how to > solve this problem. > > I'm using the Excalibur Apex development board, Nios 3.0, and the Nios > Ethernet Development Kit 2.0. > > Thanx. Hi, This has been discussed before: http://groups.google.com/groups?hl=en&lr=&ie=UTF-8&frame=right&th=3532f9a4282a0e69&seekm=95776079.0304221410.52a9616%40posting.google.com#link3 Jesse Kempa Altera Corp. jkempa at altera dot comArticle: 70871
I see the device used is a XC3S200-4FT256. You can get XC3S400 and XC3S1000 parts in that package according to my datasheet. I bet it'll cost more than 70 quid though!! Cheers, Syms. "Lukasz Salwinski" <lukasz@mbi.ucla.edu> wrote in message news:cbuuto$dd5$1@daisy.noc.ucla.edu... > Just wonder - Is there any chance the same board will be loaded > with a bigger chip ? > > lukasz >Article: 70872
csim036@ec.auckland.ac.nz (Colin) wrote in message news:<eeab73c0.0406282305.66935eb7@posting.google.com>... > Hi, > > As part of a project my partner and I are required to use the APEX > board and the NIOS Ethernet Development Kit for internet > communication. We need an indepth understanding of the software code > needed to program the ethernet board, e.g. initiallizing, sending, > etc. however the manual and online resources don't have alot of > information. > > Is there anyone who has used the ethernet adapter board and has > managed to make an application using it? because i'm having difficulty > intialising the plug and using the structures avaible (from the > manual) to get simple application going.. your help is most most > appreciated!! :)) > > Cheers Hi Colin, I talked to our application group. They don't have a nice document which shows how to create an Ethernet application. However, the example web server code is commented fairly well. If you have knowledge of sockets and then read through the Plugs manual and the example web server code, they believe you'll have a pretty good understanding of how things fit together. If you are doing something quite different from the web server, then it may be more difficult unless you understand sockets well. They suggest becoming familiar with sockets (if you aren't already) and then looking at the example web server code in the Nios installation (<install>/examples/nios_apex_20k200/standard_cs8900_xx or standard_lan91c111_xx, depending on which MAC/PHY card you have). Hope this is helpful, and good luck. Vaughn AlteraArticle: 70873
rat wrote: > Hi,friends > I am designing a pci target interface with cpld. And I want to meet the > 66Mhz pci timing requirement with lattice's ispMACH 4256V-5 (Tpd=5ns). It > seems that it is hard to meet the Tsu (<= 3ns) requirement with all of the > input pins. One way is to register every signal at the input side, just like > pipeline. But is it possible to register the IRDY signal? from my > understanding, I have to check the IRDY every clock phase in a transaction > to see if the data is valid to send or receive, and the target has to > respond immediately ( from example, in a single data phase read transaction, > once irdy is asserted and data is valid at some posedge of clock, we should > deassert the trdy signal immediately) > Any suggestion is welcome:) Thanks! > > Regards > > BTW: is the performance of the Altera QuartusII web edition worse than ISE > webpack or Lattice's tool? I synthesize the same design in Quartus and > Lattice's ispLevel starter ( with synplicity lattice edition), in Quartus, > the device choosed is max3128a-5, in ispLevel, device is ispMACH4128v-5. But > the timing analysis result is so different, ispMACH is better. What is the > problem? > > Hi Our PCI target core registers every signal, IRDY and TRDY too. It works greatly, and it was used in about 11 commercial products. Regards, Laurent Gauch www.amontec.comArticle: 70874
In article <2kgekuF25eavU1@uni-berlin.de>, Symon <symon_brewer@hotmail.com> wrote: > I see the device used is a XC3S200-4FT256. You can get XC3S400 and > XC3S1000 parts in that package according to my datasheet. I bet > it'll cost more than 70 quid though!! "A million gates for twelve dollars", remember :) [and a magazine I looked at today claimed the 70kLUT Cyclone II is $70 in those asymptotic quantities. Sadly, I doubt there are 10^5 FPGA hobbyists on the planet ...] Tom
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