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Messages from 70425

Article: 70425
Subject: Re: Altera CLKLK_FB use when OPERATION_MODE=NORMAL
From: prv3299@yahoo.com (Paulo Valentim)
Date: 16 Jun 2004 08:27:47 -0700
Links: << >>  << T >>  << A >>
I put this up on altera's site. They answered:

OK, when the ALTCLKLOCK is in Normal mode, CLKLK_FB inputs are not
used by the PLL (i.e. the PLL ignores the external FB pin).

However, you cannot use the CLKFBIN pin (R6 for your device
EP20K200EFI484-2X) as a general purpose I/O, as it is a dedicated
input pin for use with the PLL only. (in the pinout file generated by
Quartus this pins usage will be designated with a GND+ which means
this pin should be connected to GND if unused.

Note however that pin P6  (CLKLK_FB2n) can be used as a general
purpose I/o, as this is not a dedicated input pin.

Take care!!!

- Paulo Valentim

prv3299@yahoo.com (Paulo Valentim) wrote in message news:<5ed45146.0406150200.44986214@posting.google.com>...
> Hi, I am currently using an APEX20KE device.
> 
> When using the altclklock megafunction, I use OPERATION_MODE = NORMAL.
> I would like to know what is the function of the CLKLK_FB pin when in
> this mode? Does it act as a normal I/O? Thanks a lot!
> 
> - Paulo Valentim

Article: 70426
Subject: Re: a newbie question
From: "Symon" <symon_brewer@hotmail.com>
Date: Wed, 16 Jun 2004 09:45:44 -0700
Links: << >>  << T >>  << A >>
Hi Charles,
I often use a circuit posted by 'Rickman'. Go to Google groups advanced
search
http://www.google.com/advanced_group_search?hl=en
and search for the phrase "simple sync circuit" in comp.arch.fpga. Another
favourite of mine is Xilinx's 'self addressing fifo' design too. Find it in
XAPP291 on their website.
Good luck, Syms.

"charles" <czheng@ieee.org> wrote in message
news:LmNzc.47043$0y.10378@attbi_s03...
>   But what is the best way to
> handle clock domain crossing where you need to synchronize between the two
> domains.



Article: 70427
Subject: Re: >Math Skills = >Engineer ?
From: "Brannon King" <bking@starbridgesystems.com>
Date: 16 Jun 2004 13:09:33 EDT
Links: << >>  << T >>  << A >>
Let me give you a list of math/CS skills used by myself and two coworkers in
the past year and expect to use on a regular basis as a reconfigurable
computing engineer:

Basic trig and linear algebra: BLAS accelerator, ray tracer, 3D
transformations and rendering
Numerical methods for integration and general integration: Seismic data
processing
General calculus minimization and maximization technics
Turing complete issues, BNF, language design, compiler design
DCT, FFT, general butterfly expansion and theory
General algorithms such as Greedy, general Branch and Bound, Dijkstra (sp?),
etc.
General timing, error percentages, error bayesian
Seive and other prime number searches and manipulations
On a daily basis I do pointer calculations/arithmatic and some kind timing
analisys

I work with two other engineers who have insufficient math. They are total
peons. They have nothing to do with any product design because, basically,
they can't. They just don't have the background, the nomencalture, and the
mental partioning ability to be a part of the process. If you base your
"better engineer" criteria on how well a person follows orders, comments
code, and produces bugfree code, which seem to be standard mesurements, then
let me ask you this? Wouldn't you feel better knowing they understand the
orders, understand the code they're commenting, and can effectively prove
their code is bugfree? These skills all require an understanding of what's
going on at all levels, and you can't have that without math.


<user@domain.invalid> wrote in message
news:w8tzc.540$XFF1.47@news04.bloor.is.net.cable.rogers.com...
> Does better math skills really equal a better engineer in the future?
>



Article: 70428
Subject: Re: >Math Skills = >Engineer ?
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Wed, 16 Jun 2004 17:55:36 GMT
Links: << >>  << T >>  << A >>

>>How about digital logic design engineer? What kind of math required other
>>than basic arithmetic? And don't they need a lot less math than say an RF
>>engineer?

Simon Peacock wrote:
 > same as RF engineer .. ever seen what a 2 gig processor
 > looks like :-)...    infact anything over 500 MHz is RF

500MHz is the low end of the microwave region.

The US government runs a radio transmitter on 60kHz, so I
would have to call that the low end of RF.  They used to
run one at 20KHz, but don't anymore.

That is not counting the 7Hz transmitter used to communicate
with submarines.  (The resonant frequency of the earth.)

-- glen


Article: 70429
Subject: Re: Using Altera libraries for Nios Dev Board
From: kempaj@yahoo.com (Jesse Kempa)
Date: 16 Jun 2004 11:32:14 -0700
Links: << >>  << T >>  << A >>
jolivier@ee.umanitoba.ca (Justin) wrote in message news:<5d865b7e.0406150715.2a8c399b@posting.google.com>...
> Hi,
> 
> I'm currently working on a project at my university for testing and
> developing rate based protocols and I've been having some problems
> with my dev board. I've been using the Altera Nios proffesional dev
> board (with stratix FPGA). So far I've ran tests with UDP (over 2 dev
> boards) to test the utilization of my network, which is 100 Mbps and I
> keep getting numbers just under 10 Mbps. I've done tests on the lines
> over PC's and they achieve over 40 so I know the line is not the
> problem. The only thing I can see is that maybe the Ethernet/PHY chip
> they use defaults to 10 Mbps, even though it says it auto detects to
> 100 or 10.
> 
> I was wondering if anyone has experience with the low level libraries,
> like lan91c111.c, and could point me in the right direction. I would
> be satisfied to just get a printout of the register status to see if
> it is acutally setting itself to 10 Mbps. I've tried to use
> nr_lan91c111_dump_registers() but it won't give me a printout of the
> register banks. The lack of documentation also doesn't really help.
> Any help would be great.
> 
> Thanks, Justin.

Hi Justin,

In addition to what Hal posted about just checking the link speed (and
yes, all the C code that handles how the MAC/PHY are reset is in the
91c111 driver), I am curious what your software looks like that is
sending Ethernet data? The reason is that the 91c111 *should* boot up
and auto-negotiate to the highest speed available. On the other hand,
the typical bottleneck when doing embedded etherent communications is
with the CPU & protocol stack assembling packets to send.

Example: If you're running Nios at typical clock speeds and are
sending UDP data via the plugs stack, it would not surprise me at all
if the throughput was around 10Mbit. This can be accelerated quite
nicely through some simple HW acceleration (checksum & DMA use up most
of the CPU time). So, if the link speed is not the cause of your
problems, feel free to send me an email and I can send back an article
on this subject and some examples.

Jesse Kempa
Altera Corp.
jkempa at altera dot com

Article: 70430
Subject: Re: C Header files for User Design Logic in the Nios.
From: kempaj@yahoo.com (Jesse Kempa)
Date: 16 Jun 2004 11:39:36 -0700
Links: << >>  << T >>  << A >>
etd606@hotmail.com (Ted) wrote in message news:<58811c5e.0406151809.2e18b0dc@posting.google.com>...
> 
> My C code in the src directory is as follows:
> 
> #define point1 *((int *)(na_user_logic_altera_avalon_pwm_0_base))
> 
> void main()
> {
> 	while(1)
> 	{
> 	  point1=1;
> 	}
> }     
> 
> I am assuming that I am writing directly to the write_data port (In
> VHDL) so I should be expecting a dim LED for the MSB and a bright one
> at the LSB. However, all I get is 2 bright LEDs (else condition). I
> checked the manuals but there wasn't any explicit instructions on how
> to use the header files for user design logic. Any direct help will be
> greatly appreaciated. Any reference to material will also be welcomed
> too. Cheerio!
> 
> Ted

Hi Ted,

A couple of potential issues:

1. point1 is declared a pointer, when you assign it something "point1
= something", what you're doing is changing the address it points to.
Use * to dereference the pointer (standard C code stuff)... so the
first thing I'd do is change point1 = 1; to *point1 = 1;

2. If you're using Nios I with a data cache, you should declare point1
to be "volatile int*(blah)"... this isn't critical as the Nios I data
cache was write-through, but it is good practice and will prevent
cache-coherency issues down the road. If you're using Nios II (without
the legacy SDK) we have some I/O macros which direct the CPU to bypass
the cache.

Obviously your C code above is pretty simple, but in a more complex
situation its advisable to use the debugger to see what is happening
(at least with the pointers & variables declared in your C code)....
the debugger would probably catch, for example, that the pointer's
address was being written, rather than the actual address off in
memory.

Another general suggestion: when designing a peripheral as you are,
consider (at least for bring-up purposes), include registers that
allow you to read back the data... some HDL pseudo code would look
like this (I am a Verilog guy :) --

at posedge clock
  handle reset
  if (chipselect and write)
    case addressbus:
       00:
         reg0 = writedata
       01: 
         reg1 = writedata
       ...
     ...
  if (chipselect and read)
    case addressbus:
      00:
        readdata = reg0
      01:
        readdata = reg1


...and so forth. You'll burn some logic in the registers, but again,
this is a fine idea for prototyping as it allows you to debug your
hardware straight from the C code (then you can dereference the
pointer and call printf() to display what is going on in your
peripheral), which is kind of nice depending on what you're used to.
Once you're up and running and want to shave off LEs, remove the
registers and read logic as appropriate. This is just one idea, of
course.. Additional debug options include using signal tap and
triggering on the chipselect to your peripheral, or simulating in
ModelSim (see the app note on simulating Nios systems) -- you can have
an RTL view of what happens when your C code executes.

Hope this helps.

Jesse Kempa
Altera Corp.
jkempa at altera dot com

Article: 70431
Subject: XCS10-84PC: How JTAG-Pins as I/O ?
From: "\(beta-\) Frank Nitzsche" <beta-frank@beta-x.de>
Date: Wed, 16 Jun 2004 21:19:49 +0200
Links: << >>  << T >>  << A >>
Hello all,

I use Xilinx Foundation 1.5 and VHDL for a SPARTAN XCS-10 . I have to use
the JTAG-Pins as I/O-pins (TDI, TCK, TMS = I/O, TDO=O). How to do? The
data-sheet give me not enough information...

Thanks

Frank
smartie@snafu.de



Article: 70432
Subject: Re: Interfacing FPGA to on-board SRAM Stratix EP1S40F780C5
From: kempaj@yahoo.com (Jesse Kempa)
Date: 16 Jun 2004 13:18:11 -0700
Links: << >>  << T >>  << A >>
ang_edward@hotmail.com (Edward) wrote in message news:<21076d77.0406130250.6af19ab5@posting.google.com>...
> Thanks for the tip. Yes, I forgot to add that I have the Stratix Nios
> Development Kit (Professional). I have another problem though. I can
> add symbols in the .bdf files i.e. lpm_add, lpm_mult etc. However,
> these basic components are not avialable in the MegaWizard Plugin. I
> tried adding new IP blocks (SDRAM controller) to the wizard and this
> does not show in the Wizard like the guide said it would. That's after
> re-installation of the Quartus 2 (v4), service pack 1 and the Nios CD
> (Installation did not produce any errors). I tried editing the
> wizard.lst file and yes, it did show up on the Wizard interface but
> the component is still not available. An exhaustive search of manuals
> and online documentation didn't reveal anything. Any suggestions?
> 

Hi Edward,

I'm not sure about this -- you may want to give an FAE a call about
it. I myself just removed Quartus & installed a new version, and sure
enough, the basic lpm's are all included in the megawizard, so it is
definitely something that should be present with a proper
installation.

One note, however: the components available in the megawizard and
those in SOPC Builder are mutually exclusive; the SDRAM controller in
SOPC Builder that works with Nios (or any Avalon system) isn't the
same as the one you can download and put into the megawizard
independent of SOPC Builder... just wanted to address any confusion
there.

Jesse Kempa
Altera Corp.
jkempa at altera dot com

Article: 70433
Subject: Many UARTs on Avalon bus with NIOS cpu
From: "Pszemol" <Pszemol@PolBox.com>
Date: Wed, 16 Jun 2004 15:19:55 -0500
Links: << >>  << T >>  << A >>
I am looking for a nice idea of hooking up many (12) simplified UART devices
to NIOS II cpu using Avalon bus and fitting everything in Altera Cyclone FPGA.
The problem I see is all UARTs are using one baudrate generator with 8 outputs
for TX/RX clocks selectable for each UART. What would be the best way of
incorporating such components into one SOPC? Or... maybe is there a way to
make a mega-wizard component out of them with selectable number of UARTs and
one baudrate generator to save space on duplicated multiple counters/dividers?

Article: 70434
Subject: Re: Xilinx Parallel Cable IV vs. Linux
From: Stephen Williams <spamtrap@icarus.com>
Date: Wed, 16 Jun 2004 14:07:48 -0700
Links: << >>  << T >>  << A >>
Neil Glenn Jacobson wrote:

>>> Stephen Williams wrote:

>> Even if this is iMPACT bundled with ISE *6.1i*? I was under the
>> impression (based on APP notes and the like) that under Linux,
>> iMPACT starts supporing the PCIV cable at ISE 6.2. Certainly, when
>> I start impact, the radio button for Parallel Cable IV is grayed
>> out. Are you saying that when the cable arrives, I'll be able to
>> plug it in, install the Linux driver, and un-gray the selection? 
> 
> 
> You know sometimes I wonder just how awake I am...
> Yes, Linux usage of the parallel cable was first supported in 6.2i thus 
> all statements about Xilinx application support refer to release 6.2i 
> and later.
> This means that if you are unable to upgrade to 6.2i or later and need 
> to use the parallel cable and Linux then you are stuck.
> The (slower) MultiLINX cable is your only download option on Linux 
> previous to 6.2i

I use ISE Foundation in support of my Icarus Verilog work. I use
it to make sure Icarus Verilog simulations can support the various
libraries shipped with Xilinx products, and I also use the back end
tools to help me validate the FPGA code generator. (I generate EDIF
files that I feed to map/par and FPGAEdit.)

I have various Xilinx based boards that are a product of day-job,
and also a few other demo boards that people are likely to use while
playing with Icarus Verilog. (A Digilent board, a Wallace JTAG board,
an in-house PPC based board, another in-house board w/ Virtex and ACE...)

Since this is a open source (read: GPL, free) project, I can't really
afford the $2000+ of ISE. In fact, my current ISE 6.1i is a generous
contribution from your employer.

So yes, I'm stuck. But it's not holding me up.


-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."


Article: 70435
Subject: Re: XCS10-84PC: How JTAG-Pins as I/O ?
From: "Steven K. Knapp" <steve.knappNO#SPAM@xilinx.com>
Date: Wed, 16 Jun 2004 14:36:42 -0700
Links: << >>  << T >>  << A >>
A good starting place would be the following Xilinx Answer Record.

How do I instantiate JTAG pins (TDI, TDO, TCK, TMS) in HDL as general I/O?
http://support.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=4641

---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
Spartan-3/II/IIE FPGAs
http://www.xilinx.com/spartan3
---------------------------------
Spartan-3:  Make it Your ASIC

"(beta-) Frank Nitzsche" <beta-frank@beta-x.de> wrote in message
news:caq6i0$495$1@news.eusc.inter.net...
> Hello all,
>
> I use Xilinx Foundation 1.5 and VHDL for a SPARTAN XCS-10 . I have to use
> the JTAG-Pins as I/O-pins (TDI, TCK, TMS = I/O, TDO=O). How to do? The
> data-sheet give me not enough information...
>
> Thanks
>
> Frank
> smartie@snafu.de
>
>



Article: 70436
Subject: Re: XCS10-84PC: How JTAG-Pins as I/O ?
From: Philip Freidin <philip@fliptronics.com>
Date: Wed, 16 Jun 2004 21:39:43 GMT
Links: << >>  << T >>  << A >>
On Wed, 16 Jun 2004 21:19:49 +0200, "\(beta-\) Frank Nitzsche" <beta-frank@beta-x.de> wrote:
>Hello all,
>
>I use Xilinx Foundation 1.5 and VHDL for a SPARTAN XCS-10 . I have to use
>the JTAG-Pins as I/O-pins (TDI, TCK, TMS = I/O, TDO=O). How to do? The
>data-sheet give me not enough information...
>
>Thanks
>
>Frank
>smartie@snafu.de
>

Look in the Libraries guide. I believe you will find some
special I/O pad symbols with appropriate names.

Note that these I/O pins do not have a full IOB behind them,
so no input or output flip flops.

I seem to remember that you can only use IBUF and OBUF
for these pins. (maybe OBUFT too)

Philip



Philip Freidin
Fliptronics

Article: 70437
Subject: Re: Suse 9.1 Linux and Xilinx ISE 6.2i
From: Stephen Williams <spamtrap@icarus.com>
Date: Wed, 16 Jun 2004 14:45:14 -0700
Links: << >>  << T >>  << A >>
salman sheikh wrote:
> Hello,
> 
> I just installed Xilinx ISE 6.2i on a Linux box and it is sluggish as 
> anything.  Does anyone know why? I am running on a P4 1.7GHz w/ 1GB of 
> RAM.  On windows, it is much more zippy. Could it be the gui toolkit 
> that Xilinx is using (it seems like JAVA.......slow as a slug....)?

Well, I run ISE 6.1i on a dual Opteron 244 w/ 3GIG of DRAM. Just
starting the ISE project manager takes 15+ seconds. And it's amazing
that such a fast machine can feel so slow. impact is also embarassingly
slow to start up.

It looks like JAVA widgets, although I've also seen hints of
compatibility libraries in use. I'm not privy.

The GUI stuff really is gawd-awful slow, but other than fpga_editor
and iMPACT, I stick with command line tools. My impression there
is that the command line tools work just fine.

-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."


Article: 70438
Subject: help for finding a company which can provide FPGA based PCI board with ethernet port
From: tomgoogle2000@yahoo.com (tom)
Date: 16 Jun 2004 15:50:01 -0700
Links: << >>  << T >>  << A >>
Hi, guys, I try to find a company which can provide a FPGA based PCI
board with ethernet port, thanks in advance.
the system requirement:
1. since my algorithm is computation intensive, it should be run on
FPGA, I try to find a FPGA based PCI board, the desirable FPGA would
be xilinx virtex II or virtex pro
2. the FPGA based PCI board has a ethernet port, and there is windows
2k or XP driver for this port
3. it is better the company can also provide A/D and D/A board 
thanks,
Tom

Article: 70439
Subject: Xilinx RAM64x1D simulation problems
From: "Doug Miller" <nospam_doug_miller@worldnet.att.net>
Date: Thu, 17 Jun 2004 00:50:00 GMT
Links: << >>  << T >>  << A >>
When I try to simulate writing into a RAM64x1D, the output (signal "douta")
becomes indeterminate.  My testbench file and instantiation file are in the
text that follows.  Am I doing something wrong, or is there a problem with
the Xilinx simulation libraries?

Thanks,
Doug

---------------- Cut Here -----------------------------
-- TestBench Template

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.numeric_std.ALL;

use ieee.std_logic_arith.ALL;

use ieee.std_logic_signed.ALL;

library unisim; -- required for Xilinx components instantiated in the design

use unisim.vcomponents.ALL;

ENTITY dp64x1d_tb IS

END dp64x1d_tb;

ARCHITECTURE behavior OF dp64x1d_tb IS

component dp64x1d is

Port (

clk : in std_logic;

-- Input Side

wr_en : in std_logic;

in_addr : in std_logic_vector(5 downto 0);

din : in std_logic;

douta : out std_logic;

-- Output side

out_addr : in std_logic_vector(5 downto 0);

doutb : out std_logic

);

end component;

signal rst : std_logic;

signal clk : std_logic;

signal wr_en : std_logic;

signal in_addr : std_logic_vector(5 downto 0);

signal din : std_logic;

signal douta : std_logic;

signal out_addr : std_logic_vector(5 downto 0) := "000000";

signal doutb : std_logic;

constant CLK100_HALF_PERIOD :time := 5 ns; -- 100 MHz

begin

clk100MHz_proc: process

begin

clk <= '0';

wait for CLK100_HALF_PERIOD;

clk <= '1';

wait for CLK100_HALF_PERIOD;

end process clk100MHz_proc;

generate_some_activity: process(clk,rst)

begin

if (rst = '1') then

in_addr <= (others => '0');

elsif (clk'event and clk = '1') then

if (in_addr /= "111111") then

in_addr <= in_addr + 1;

else

in_addr <= (others => '0');

end if;

end if;

end process;

generate_wr_en: process(clk,rst)

begin

if (rst = '1') then

wr_en <= '0';

elsif (clk'event and clk = '0') then

wr_en <= not rst;

end if;

end process;

din <= in_addr(0) after 1 ns; -- Just put something in there...

-- Component Instantiation

uut: dp64x1d

Port map (

clk => clk,

-- Input Side

wr_en => wr_en,

in_addr => in_addr,

din => din,

douta => douta,

-- Output side

out_addr => out_addr,

doutb => doutb

);



-- ---------------------------------------------------------------

-- Generate the rst pulse

---------------------------------------------------------------

rst_proc: PROCESS

BEGIN

-- Reset the core

rst <= transport std_logic'('1');

WAIT FOR 200 ns;

rst <= transport std_logic'('0');

-- Process the input stimulus data file

WAIT FOR 2 sec;

END PROCESS;

end;

----------------------Cut Here -------------------------------

---------------------------------------------------------------------------

--

-- This is a simple file created to investigate RAM64X1D behavior

--

---------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

library UNISIM;

use UNISIM.VComponents.all;

entity dp64x1d is

Port (

clk : in std_logic;

-- Input Side

wr_en : in std_logic;

in_addr : in std_logic_vector(5 downto 0);

din : in std_logic;

douta : out std_logic;

-- Output side

out_addr : in std_logic_vector(5 downto 0);

doutb : out std_logic

);

end dp64x1d;

architecture rtl of dp64x1d is

component RAM64X1D

port (

D : in std_logic;

WE : in std_logic;

WCLK : in std_logic;

A0 : in std_logic;

A1 : in std_logic;

A2 : in std_logic;

A3 : in std_logic;

A4 : in std_logic;

A5 : in std_logic;

DPRA0 : in std_logic;

DPRA1 : in std_logic;

DPRA2 : in std_logic;

DPRA3 : in std_logic;

DPRA4 : in std_logic;

DPRA5 : in std_logic;


SPO : out std_logic;

DPO : out std_logic);

end component;




begin



dp: RAM64X1D

port map (

WCLK => clk,

WE => wr_en,

D => din,

A0 => in_addr(0),

A1 => in_addr(1),

A2 => in_addr(2),

A3 => in_addr(3),

A4 => in_addr(4),

A5 => in_addr(5),

DPRA0 => out_addr(0),

DPRA1 => out_addr(1),

DPRA2 => out_addr(2),

DPRA3 => out_addr(3),

DPRA4 => out_addr(4),

DPRA5 => out_addr(5),


SPO => douta,

DPO => doutb

);

end rtl;

------------------------------- end ---------------------------------



Article: 70440
Subject: Re: Xilinx RAM64x1D simulation problems
From: "Doug Miller" <nospam_doug_miller@worldnet.att.net>
Date: Thu, 17 Jun 2004 01:09:01 GMT
Links: << >>  << T >>  << A >>
OK, just got a little stranger - I ran this at home on my free Xilinx
Edition Modelsim, and it ran fine.  At work, I have Modelsim PE, which
generates the indeterminate output.  Does this mean that I need to recompile
my Xilinx Unisim library on PE?

Doug


"Doug Miller" <nospam_doug_miller@worldnet.att.net> wrote in message
news:YU5Ac.23866$Di3.5949@bgtnsc05-news.ops.worldnet.att.net...
> When I try to simulate writing into a RAM64x1D, the output (signal
"douta")
> becomes indeterminate.  My testbench file and instantiation file are in
the
> text that follows.  Am I doing something wrong, or is there a problem with
> the Xilinx simulation libraries?
>
> Thanks,
> Doug
>
> ---------------- Cut Here -----------------------------
> -- TestBench Template
>
> LIBRARY ieee;
>
> USE ieee.std_logic_1164.ALL;
>
> USE ieee.numeric_std.ALL;
>
> use ieee.std_logic_arith.ALL;
>
> use ieee.std_logic_signed.ALL;
>
> library unisim; -- required for Xilinx components instantiated in the
design
>
> use unisim.vcomponents.ALL;
>
> ENTITY dp64x1d_tb IS
>
> END dp64x1d_tb;
>
> ARCHITECTURE behavior OF dp64x1d_tb IS
>
> component dp64x1d is
>
> Port (
>
> clk : in std_logic;
>
> -- Input Side
>
> wr_en : in std_logic;
>
> in_addr : in std_logic_vector(5 downto 0);
>
> din : in std_logic;
>
> douta : out std_logic;
>
> -- Output side
>
> out_addr : in std_logic_vector(5 downto 0);
>
> doutb : out std_logic
>
> );
>
> end component;
>
> signal rst : std_logic;
>
> signal clk : std_logic;
>
> signal wr_en : std_logic;
>
> signal in_addr : std_logic_vector(5 downto 0);
>
> signal din : std_logic;
>
> signal douta : std_logic;
>
> signal out_addr : std_logic_vector(5 downto 0) := "000000";
>
> signal doutb : std_logic;
>
> constant CLK100_HALF_PERIOD :time := 5 ns; -- 100 MHz
>
> begin
>
> clk100MHz_proc: process
>
> begin
>
> clk <= '0';
>
> wait for CLK100_HALF_PERIOD;
>
> clk <= '1';
>
> wait for CLK100_HALF_PERIOD;
>
> end process clk100MHz_proc;
>
> generate_some_activity: process(clk,rst)
>
> begin
>
> if (rst = '1') then
>
> in_addr <= (others => '0');
>
> elsif (clk'event and clk = '1') then
>
> if (in_addr /= "111111") then
>
> in_addr <= in_addr + 1;
>
> else
>
> in_addr <= (others => '0');
>
> end if;
>
> end if;
>
> end process;
>
> generate_wr_en: process(clk,rst)
>
> begin
>
> if (rst = '1') then
>
> wr_en <= '0';
>
> elsif (clk'event and clk = '0') then
>
> wr_en <= not rst;
>
> end if;
>
> end process;
>
> din <= in_addr(0) after 1 ns; -- Just put something in there...
>
> -- Component Instantiation
>
> uut: dp64x1d
>
> Port map (
>
> clk => clk,
>
> -- Input Side
>
> wr_en => wr_en,
>
> in_addr => in_addr,
>
> din => din,
>
> douta => douta,
>
> -- Output side
>
> out_addr => out_addr,
>
> doutb => doutb
>
> );
>
>
>
> -- ---------------------------------------------------------------
>
> -- Generate the rst pulse
>
> ---------------------------------------------------------------
>
> rst_proc: PROCESS
>
> BEGIN
>
> -- Reset the core
>
> rst <= transport std_logic'('1');
>
> WAIT FOR 200 ns;
>
> rst <= transport std_logic'('0');
>
> -- Process the input stimulus data file
>
> WAIT FOR 2 sec;
>
> END PROCESS;
>
> end;
>
> ----------------------Cut Here -------------------------------
>
> --------------------------------------------------------------------------
-
>
> --
>
> -- This is a simple file created to investigate RAM64X1D behavior
>
> --
>
> --------------------------------------------------------------------------
-
>
> library IEEE;
>
> use IEEE.STD_LOGIC_1164.ALL;
>
> use IEEE.STD_LOGIC_ARITH.ALL;
>
> use IEEE.STD_LOGIC_UNSIGNED.ALL;
>
> library UNISIM;
>
> use UNISIM.VComponents.all;
>
> entity dp64x1d is
>
> Port (
>
> clk : in std_logic;
>
> -- Input Side
>
> wr_en : in std_logic;
>
> in_addr : in std_logic_vector(5 downto 0);
>
> din : in std_logic;
>
> douta : out std_logic;
>
> -- Output side
>
> out_addr : in std_logic_vector(5 downto 0);
>
> doutb : out std_logic
>
> );
>
> end dp64x1d;
>
> architecture rtl of dp64x1d is
>
> component RAM64X1D
>
> port (
>
> D : in std_logic;
>
> WE : in std_logic;
>
> WCLK : in std_logic;
>
> A0 : in std_logic;
>
> A1 : in std_logic;
>
> A2 : in std_logic;
>
> A3 : in std_logic;
>
> A4 : in std_logic;
>
> A5 : in std_logic;
>
> DPRA0 : in std_logic;
>
> DPRA1 : in std_logic;
>
> DPRA2 : in std_logic;
>
> DPRA3 : in std_logic;
>
> DPRA4 : in std_logic;
>
> DPRA5 : in std_logic;
>
>
> SPO : out std_logic;
>
> DPO : out std_logic);
>
> end component;
>
>
>
>
> begin
>
>
>
> dp: RAM64X1D
>
> port map (
>
> WCLK => clk,
>
> WE => wr_en,
>
> D => din,
>
> A0 => in_addr(0),
>
> A1 => in_addr(1),
>
> A2 => in_addr(2),
>
> A3 => in_addr(3),
>
> A4 => in_addr(4),
>
> A5 => in_addr(5),
>
> DPRA0 => out_addr(0),
>
> DPRA1 => out_addr(1),
>
> DPRA2 => out_addr(2),
>
> DPRA3 => out_addr(3),
>
> DPRA4 => out_addr(4),
>
> DPRA5 => out_addr(5),
>
>
> SPO => douta,
>
> DPO => doutb
>
> );
>
> end rtl;
>
> ------------------------------- end ---------------------------------
>
>



Article: 70441
Subject: Re: help for finding a company which can provide FPGA based PCI board with ethernet port
From: Philip Freidin <philip@fliptronics.com>
Date: Thu, 17 Jun 2004 03:41:44 GMT
Links: << >>  << T >>  << A >>
On 16 Jun 2004 15:50:01 -0700, tomgoogle2000@yahoo.com (tom) wrote:
>Hi, guys, I try to find a company which can provide a FPGA based PCI
>board with ethernet port, thanks in advance.
>the system requirement:
>1. since my algorithm is computation intensive, it should be run on
>FPGA, I try to find a FPGA based PCI board, the desirable FPGA would
>be xilinx virtex II or virtex pro
>2. the FPGA based PCI board has a ethernet port, and there is windows
>2k or XP driver for this port
>3. it is better the company can also provide A/D and D/A board 
>thanks,
>Tom

The following URL lists pretty much all boards that are available.

   http://www.fpga-faq.com/FPGA_Boards.shtml




===================
Philip Freidin
philip.freidin@fpga-faq.com
Host for WWW.FPGA-FAQ.COM

Article: 70442
Subject: Re: MGT pin details(Xilinx Virtex 2 PRO)
From: Andrew Dyer <andrew.spam.dyer@comcast.net>
Date: Thu, 17 Jun 2004 04:26:53 GMT
Links: << >>  << T >>  << A >>
On Wed, 16 Jun 2004 19:32:31 +1000, Allan Herriman wrote:

> On a recent design, I tied VCCAUXTX, VCCAUXRX, VTRX to +2.5V and left
> the TxP, TxN, RxP, RxN pins open.
> 
> The RocketIO™ Transceiver User Guide
> http://www.xilinx.com/bvdocs/userguides/ug024.pdf
> doesn't appear to say anything about the VTRX pins when the
> transceiver is unused.
> 
> Note that the pinout of the BGA package is such that the VCCAUXTX,
> VCCAUXRX and VTRX are all in a row.  It's easier to tie the VTRX pins
> to +2.5V than to leave them open.
> 

Somewhere in the v2pro datasheet or user guide there is a recommendation
on what to do with unused MGT pins.  On our board we have the same setup
as Allan, and I know we followed the recommendations.

Article: 70443
Subject: Re: Xilinx ParallelCable IV vs. Linux
From: Rudolf Usselmann <russelmann@hotmail.com>
Date: Thu, 17 Jun 2004 12:29:34 +0700
Links: << >>  << T >>  << A >>
Stephen Williams wrote:

> 
> Does anybody know if the Xilinx Paralel cable IV cable can
> be made to work under Linux w/ ISE 6.1i.03? And to make it
> even more interesting, my Linux is AMD64, will the driver work
> at all on this system?
> 
> 
> .... and while we're on the subject, the Linux driver source is
> itself is pretty basic. Is there programming informatino for the
> cable that one can use to write custom software to drive the
> device.


Stephen,

not sure if this will help:

I have faced the same problem - not being able to program
Xilinx Devices using Xilinx Software and Xilinx hardware
under linux. So I wrote a small dumb program that can take
a bit stream and directly upload it to an FPGA.

You can find it here: http://www.asics.ws/tools/ljp.c.gz

This works with both Parallel Cable 3 and 4.

Regards,
rudi               
========================================================
   ASICS.ws   ::: Solutions for your ASIC/FPGA needs :::
..............::: FPGAs * Full Custom ICs * IP Cores :::
FREE IP Cores -> http://www.asics.ws/  <- FREE EDA Tools


Article: 70444
Subject: Re: Xilinx ParallelCable IV vs. Linux
From: Philip Freidin <philip@fliptronics.com>
Date: Thu, 17 Jun 2004 05:39:28 GMT
Links: << >>  << T >>  << A >>
On Fri, 11 Jun 2004 11:31:18 -0700, Stephen Williams <spamtrap@icarus.com> wrote:
>
>Does anybody know if the Xilinx Paralel cable IV cable can
>be made to work under Linux w/ ISE 6.1i.03? And to make it
>even more interesting, my Linux is AMD64, will the driver work
>at all on this system?
>
>
>.... and while we're on the subject, the Linux driver source is
>itself is pretty basic. Is there programming informatino for the
>cable that one can use to write custom software to drive the
>device.

I am not sure how relevant this is, but there is some source code
and other notes in the FAQ:   "Downloading a Bitstream under Linux"
Here's the URL

    http://www.fpga-faq.com/FAQ_Pages/0028_Downloading_a_Bitstream_under_Linux.htm




===================
Philip Freidin
philip.freidin@fpga-faq.com
Host for WWW.FPGA-FAQ.COM

Article: 70445
Subject: Re: RAM in Altera EABs and Xilinx Block Rams
From: rickman <spamgoeshere4@yahoo.com>
Date: Thu, 17 Jun 2004 01:42:07 -0400
Links: << >>  << T >>  << A >>
Rajeev wrote:
> 
> I wish I had something more constructive to offer...  I have a Stratix
> design and I use read latency of 2 cycles everywhere (one for address in,
> one for data out.)  While one can eliminate the data output register it
> adds enough ns that it's just not worth it.
> 
> I can't help noticing the (huge?) disparity between the 1K50 and the
> 3S400, and am surprised that you're still using the ACEX parts.  In that
> vein, I'm carrying around the notion that _all_ newer FPGAs are or will
> require registered ports... so why not bite the bullet and go synchronous ?

In my design it adds a clock cycle delay to have a register on the data
out side of the RAM.  So that slows things down a lot.  I am using the
ACEX parts because I need the 5 volt tolerance that has been left behind
by the newer parts.  For that function, they work very well.  


> I'm also not sure from your post whether "pipelined" is synonymous with
> "registered", ie you're trying to do something like one instruction per
> clock cycle and/or you can't tolerate the 2 ticks latency.

Yes, if you have more than one register in the fetch-decode-execute
cycle, then more than one clock cycle is needed and if you want to start
a new instruction on every clock (as I do) it would have to be
pipelined.  Non-pipelined MCUs are *much* simpler and not necessarily
slower in the time to execute any given instruction.  Pipelining only
lets you add more hardware to overlap execution of multiple
instructions.  You also don't have to deal with throwing away prefetches
if you don't pipeline.  

After looking at the structure of the Xilinx Spartan 3 block rams, I see
that I can't escape the output register.  But seeing the mode where the
read is done post-write I realized that I can add a mux and an output
register which will always reflect the top of the stack without a read
delay!  I am still not certain it will work ok in the Xilinx part, but
this works great in the Altera parts and it speeds up the cycle time a
lot.  I can decode and execute the current instruction and fetch the
next instruction in no more than two levels of logic and one RAM delay
per clock cycle.  I expect this to run at 60 to 80 MHz without too much
trouble.  If I work on optimizing the placement and routing, I might
even get 100MHz out of this.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 70446
Subject: Re: RAM in Altera EABs and Xilinx Block Rams
From: rickman <spamgoeshere4@yahoo.com>
Date: Thu, 17 Jun 2004 01:56:07 -0400
Links: << >>  << T >>  << A >>
roller wrote:
> 
> i dont know exactly how the spartan3 is related to the spartan2, but it
> might help you, check this out
> 
> http://toolbox.xilinx.com/docsan/xilinx4/data/docs/lib/dsgnelpr5.html
> 
> it says that when you write data, one of the ports reads what you're
> writting. From Coregen options i'd guess that you can also set it up as
> read-after-write (this one) or write-after-read (which would read the
> previous contents, and then write)

Yes, I saw that.  It gave me an idea of how I can deal with the read
delay in the Altera part.  But I belive the Xilinx part still gives you
a two clock delay on reading the new data.  I am using the RAM for
stacks among other things.  So I can use a separate register to always
hold the top of stack.  But if it pushes to the stack on one clock cycle
and on the next clock cycle pops, the data on the output of the Xilinx
RAM is still stale.  I guess I can use the dual port and always have the
read one address below the write.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 70447
Subject: Re: RAM in Altera EABs and Xilinx Block Rams
From: rickman <spamgoeshere4@yahoo.com>
Date: Thu, 17 Jun 2004 02:00:07 -0400
Links: << >>  << T >>  << A >>
Peter Alfke wrote:
> 
> Xilinx (Virtex2 or Spartan3) BlockRAM reading while writing:
> Any write operation also performs a read, and outputs it on the Do output.
> The user can choose: write before read (= output the data that is being
> witten), or read before write (=output the previous content that is now
> being overwritten) or "no change"( keep the old data on the Do lines.

But it still has a two cycle delay from writing to read data out,
right?  So if I want the data that was just written on the next clock
cycle (like in a stack) I need to use an external register and use
separate read and write addresses.  Correct?  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 70448
Subject: Re: RAM in Altera EABs and Xilinx Block Rams
From: rickman <spamgoeshere4@yahoo.com>
Date: Thu, 17 Jun 2004 02:07:53 -0400
Links: << >>  << T >>  << A >>
Symon wrote:
> 
> Hi Rick,
> I can offer my experiences with Xilinx blockram. You're correct that both
> the read and write are synchronous. There are three write options,
> WRITE_FIRST, READ_FIRST and NO_CHANGE. Carefully (!) read about these in the
> data sheet. I use WRITE_FIRST almost exclusively, where the "same clock edge
> that writes the data input (DI) into the memory also transfers DI into the
> output registers DO".
> When I did my processor design, I also used one as a stack. Like your design
> I didn't use pipelining. This was to keep the design small and simple. On
> the BlockRAM I used one port for PUSHING/POPPING registers, and the other
> for CALL/RETURN subroutine addresses. The catch with these blockrams is
> that, if you read from one port whilst you're writing to the *same* address
> on the other port, the read data is indeterminate. This makes sense if you
> think about what the BlockRAM is doing. Check out 'Conflict Resolution' in
> the user guide (I'm looking at ug012 for V2PRO). This means for me that I
> can't do a POP instruction immediately after doing a CALL subroutine, and I
> can't do a RETURN immediately after doing a PUSH. No problem to avoid this
> in the code, of course. It's a wierd thing to do anyway.
> The ModelSIM simulator also warns if conflicts occur and, of course,
> simulates the RAM accurately.

Sounds like we are doing similar things.  I am not trying to share one
ram for two stacks though.  In the Altera part, I can have an async read
and a clocked write all with the same address (single port).  So
whenever I write (push) the data is available on the read output in the
second half of the next clock cycle.  To speed up the delay I am adding
a mux and a register to hold the top of stack when the stack is written
and to get the second to top on pops (new top).  Since this is
registered, I don't have to worry about the cascaded delays on the
address setup and the RAM read times.  On a return instruction it would
have two RAM delays (return stack and instruction memory) and some three
or four LUT delays (decode, mux).  

But with the Xilinx part, the two clock cycle thing really gets in the
way of implementing one clock cycle stacks.  You can't even do a push
followed by a pop which is not at all uncommon... "1 2 add"... two
pushes followed by a pop.  I can do the same muxed register trick I do
with the Altera part, but I have to have two addresses and use two
ports, one for read and one for write.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 70449
Subject: Re: RAM in Altera EABs and Xilinx Block Rams
From: rickman <spamgoeshere4@yahoo.com>
Date: Thu, 17 Jun 2004 02:14:36 -0400
Links: << >>  << T >>  << A >>
John_H wrote:
> 
> Quoting Peter's text from below, "When one port performs a write operation,
> the other port must not write into the same location, unless both ports
> write identical data."
> 
> For a one-port dedicated read and one-port dedicated write configuration
> that I *believe* rickman is pursuing, a little trick could be used:  feed
> the data to *both* write ports and enable the write to the nomally read-only
> port when a RdAddr==WrAddr compare is valid.  This increases the effective
> address setup time but gives the desired WRITE_FIRST functionality without
> increasing the Clk-to-out time.

To implement a stack you don't normally need separate read and write
ports since you only do one thing at a time.  The Xilinx block RAMs
can't do a read in less than two clock cycles which gets in the way of a
stack.  So I would need to use a separate register to hold the top of
stack and refresh that on POPs from the RAM using a separate read port
with a separate address.  In that case there is never the problem of
simulaneous reads and writes to the same address because you only ever
do one thing at a time.  

I have not thought about my program or data memory.  I may really be
hosed there and have to abandon the one clock cycle instruction idea.  I
guess I could use a two up clock or something similar.  I belive the
Spartan 3 block rams are fast enough that I likely won't have a speed
issue even with a 2x clock.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX



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