Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
It looks very different to me !
any clue ?
------------ With testpoint at PF0 pin ( being PF0='0' when a(11 to
15)="00000" and nwr='0' )
-- Equation name is 'PA0', type is output
PA0 = LCELL( _EQ017 $ GND);
_EQ017 = !a8 & !a9 & !a10 & d0 & PF0
# PA0 & !PF0
# a9 & PA0
# a10 & PA0
# _LC111;
------------ Without testpoint
-- Equation name is 'PA0', type is output
PA0 = LCELL( _EQ017 $ PA0);
_EQ017 = !a8 & !a9 & !a10 & !a11 & !a12 & !a13 & !a14 & !a15 & d0 & !nwr
&
!PA0
# !a8 & !a9 & !a10 & !a11 & !a12 & !a13 & !a14 & !a15 & !d0 & !nwr
&
PA0;
Article: 70576Frank Benoit <nospam@xyz.com> wrote in message news:<pan.2004.06.19.20.15.14.179200@xyz.com>... > > Have a look at the SAVE NET FLAG constraint in the cgd.pdf documentation. > > http://toolbox.xilinx.com/docsan/xilinx5/pdf/docs/cgd/cgd.pdf Using LOC and SAVE NET FLAG with no results. The PARer gives the warnings: "logical net on "signal" has no load" and "Attribute LOC on "signal" is on the wrong type of object." Then looking at the project.pad_txt file, "signal" does not show up. I thought about using the dummy function, but the inputs are just discrete interrupts from outside that update a register that gets read/reset at some later time. What better 'dummy' funtion? I can see how it could get optimized out, but those inputs are needed whether XST thinks they are or not. Reading the docs leads me to believe the SAVE NET FLAG should do the job, but..... Thanks again for the suggestions. Knowing where to find that doc is worth the post!Article: 70577
Xilinx and Altera have free downloadable design software available for their range of FPGAs, the problem is that it requires Windows. I have searched for free design software for Linux but can't find any. Both Xilinx and Altera sell software for Linux but I can't find the free software like that available for Windows. Are there any FPGA vendors out there that provide free design software for Linux? Why do Altera and Xilinx offer free software for Windows but not for Linux? Maybe free software is available and I haven't found it yet. Regards AndrewArticle: 70578
On 21 Jun 2004 04:06:06 -0700, t_naimesh@rediffmail.com (Naimesh) wrote: >I need to use spartan series FPGA for a design.( As design have only 5 >V supply available). when I start a new project in XILINX ISE 6.1 I >dont get option of Spartan in Device selection list. can anyone help >me out. which software do I need. > >Thanks for any help Although Xilinx does sell most Spartan and SpartanXL devices still (except those in PC84 and CSxxx packages), you have to use ISE 4.1 to work with those families. ================================ Greg Neff VP Engineering *Microsym* Computers Inc. greg@guesswhichwordgoeshere.comArticle: 70579
> I'm using the output CLKFX of a DCM in a virtexII pro with CLKIN = 10MHz. > The M factor is 27 and the D factor is 10 so that I get CLKFX = 27MHz. Since the > PLL mode does not support CLKIN < 24 MHz should I still keep the feedback loop > between CLK0 and CLKFB. Hi, I had with the Spartan 3 DCM same problem. If you use Feedback, then input freq. can't be below ca. 24 MHz. But if you do not use Feedback, then input freq. can't be below ca. 1 MHz. Without Feedback is only problem Phase. Tarmo PalmArticle: 70580
"andrew<AT>rogerstech<DOT>co<DOT>uk rogerstech co uk >" <"andrew<ATDOTDOT>
wrote in message news:40d6db9f_1@127.0.0.1...
> Xilinx and Altera have free downloadable design software available for
> their range of FPGAs, the problem is that it requires Windows. I have
> searched for free design software for Linux but can't find any. Both
> Xilinx and Altera sell software for Linux but I can't find the free
> software like that available for Windows.
>
> Are there any FPGA vendors out there that provide free design software
> for Linux?
>
> Why do Altera and Xilinx offer free software for Windows but not for
> Linux? Maybe free software is available and I haven't found it yet.
>
> Regards
> Andrew
>
For Altera, I believe the reason they don't have a web edition for Linux is
that their Linux port uses a library ("mainwin" ?) for the gui on Linux. I
don't know for sure, but I guess it is basically an implementation of (parts
of) the win32 api on X so that Altera don't have to maintain two seperate
guis. Mainwin presumably costs Altera money per seat, since you need a
license to run it, so Altera can't give it away free. It might be possible
to get the rest of Quartus II web edition to run under Linux - after all, it
consists of a variety of command-line programs glued together with tcl,
perl, and bash scripting, which are perfectly at home on Linux. Maybe one
day Altera will notice that there are plenty of free cross-platform gui
libraries, plus a free win32 api for X, which would make a Linux web edition
easy, but I suppose that comes down to customer demand and development
priorities.
No doubt the situation for Xilinx is somewhat similar, and when one of the
two produces free Linux tools, the other will quickly follow.
Article: 70581"Brannon King" <bking@starbridgesystems.com> wrote in message snipping > I work with two other engineers who have insufficient math. They are total > peons. They have nothing to do with any product design because, basically, > they can't. They just don't have the background, the nomencalture, and the Its part of the job to work with "peons" unfortunately. Not sure if I would have broadcast that from the company email though:-) Next time I think of SB, I will remember those 2 "peons";, poor guys! regards johnjakson_usa_comArticle: 70582
Consider shelling out the cash for a regulator (about 69 cents?) and use one of the new - read this as "inexpensive" - Xilinx devices. The functionality, capability, and support are all superior to the older devices. If you have 5V interface concerns, know that the LVTTL I/O format easily drive 5V logic and compliance with >3.3V inputs can be achieved with a series resister per Xilinx recommendations. It's such a good way to go. "Naimesh" <t_naimesh@rediffmail.com> wrote in message news:ecee4f8a.0406210306.3bea9972@posting.google.com... > I need to use spartan series FPGA for a design.( As design have only 5 > V supply available). when I start a new project in XILINX ISE 6.1 I > dont get option of Spartan in Device selection list. can anyone help > me out. which software do I need. > > Thanks for any helpArticle: 70583
I'd recommend contacting your Altera rep to find out if the MaxPlus-II devices are available for you. For your application, these chips could be the cheapest way to go. Normally a CPLD in >> 128 macrocells won't be extremely inexpensive. Not bad, but not the savings you can achieve. The MaxPlus-II devices are like tiny, old-generation FPGAs with embedded flash memory giving you full functionality without external boot memories. The no-frills architecture (who needs PLLS or RAM for your application?) fits with no-frill requirements. If these relatively new devices are available, they may be the most cost-effective way to go. "Richard Cooke" <rcooke_@symbolgoeshere_redmtnengr.com> wrote in message news:9i5cd0ht0rc0u76htnkc78dguklrm700jk@4ax.com... > Hello, > > I'm new to the world of CPLDs or FPGAs so please be easy on me. We > have a requirement for an 8 channel (12 channel would be better) > countdown timer at 12 to 14 bit resolution with a 20MHz clock input. > > All we need is to be able to load the channel's timer value via the > processor's data bus and start the timers after the last channel is > loaded. We need 8 (or 12) outputs that go high during the countdown > and turns off when the timer times out and stays off until the next > time they are loaded. > > Is this possible in a relatively cheap CPLD and which "family" would > be a good starting point? If this is a complicated design we would > certainly entertain the possibility of farming this out. > > Thanks, > > RichardArticle: 70584
If you cut & pasted from your code, I don't see anything wrong. The READ_FIRST should only be an issue when reading from / writing to the same port. Verify in your test case that you're not using the same clock and address in both ports such that the code sees that you "want" a single port memory even though the code should normally infer a dual-port. If you are tying things together in the upper module, perhaps you can force the dual_port_ram entity not to be "optimized" into the single port by using compiler directives. "Acciduzzu" <pmihail@gmx.net> wrote in message news:9a9b05a9.0406201355.2448da61@posting.google.com... > Hi all, > > Maybe this question has been asked before, but I couldn't find a > suitable answer on this group until now. Having followed the coding > styles recommended by Xilinx, I ended up with the following code: > > > library IEEE; > use IEEE.std_logic_1164.all; > use IEEE.numeric_std.all; > > > entity dual_port_ram is > generic ( > WIDTH : integer := 32; > DEPTH : integer := 10 > ); > port ( > w_clk : in std_logic; > w_en_in : in std_logic; > w_addr_in : in std_logic_vector(DEPTH-1 downto 0); > w_data_in : in std_logic_vector(WIDTH-1 downto 0); > > r_clk : in std_logic; > r_addr_in : in std_logic_vector(DEPTH-1 downto 0); > r_data_out : out std_logic_vector(WIDTH-1 downto 0) > ); > end entity; > > > architecture xilinx of dual_port_ram is > > type memory_type is array (natural range <>) of > std_logic_vector(WIDTH-1 downto 0); > signal memory : memory_type(2**DEPTH-1 downto 0); > > begin > > write : process(w_clk) > begin > if w_clk'event and w_clk = '1' then > if w_en_in = '1' then > memory(to_integer(unsigned(w_addr_in))) <= w_data_in; > end if; > end if; > end process; > > read : process(r_clk) > begin > if r_clk'event and r_clk = '1' then > r_data_out <= memory(to_integer(unsigned(r_addr_in))); > end if; > end process; > > end architecture; > > > Yet, instead of BlockRAM, XST implements this as distributed RAM (with > combinational output) plus registers at the output, issuing the > following: > > INFO:Xst:1435 - HDL ADVISOR - Unable to extract a block RAM for signal > <memory>. The read/write synchronization appears to be READ_FIRST and > is not available for the selected family. A distributed RAM will > usually be created instead. To take advantage of block RAM resources, > you may want to revisit your RAM synchronization or check available > device families. > Found 1024x32-bit dual-port distributed RAM for signal <memory>. > > What is this read/write RAM synchronization after all? Maybe the > Xilinx folks (Peter Alfke & Co.) could help ;) > > ThanksArticle: 70585
Johan Bernspång wrote:
> Hi all,
>
> I'm using the code below to generate a pulse which is 16x57600 from a
> 51.2 MHz clock signal to controll the sampling in a rs232 module. The
> pulse generator does not work however. It generats a constant high
> signal instead of a 921.6 kHz pulse.
>
> Can anyone see what might be faulty with my design? I'm clueless...
Johan,
Since it looked like this thread has side-tracked a little, I wanted to
follow up on the original code as it was not too bad, just a few
mistakes. I took out the attribute and component declarations which are
not necessary if you include the library UNISIM and use
UNISIM.VComponents.all statements and removed all of the translate_off
and translate_on's and the implpemented code worked just like the
behavioral simulation did. I do not think there was an inherent problem
with this code other than the fact that you were using the
transalte_off/on's in the code and the SRL was not getting intitialized
properly because of it. At the speeds you are talking about, the code
should run fine, as-is but if you did need speed, you could use SRLC16's
which use a dedicaed net for cascading that runs faster and you could
have the feedback path to the intitial SRL in the chain derived from the
register as the clock-to-out of the register is faster than the SRL but
as I said, at 51 MHz, probably not necessary.
I will attach your modified code below for refernce.
-- Brian
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity baud16 is
port(
Clk : in std_logic;
baud_pulse : out std_logic);
end entity baud16;
architecture imp of baud16 is
signal clkdv56 : std_logic;
signal clkdv56_i1 : std_logic;
signal clkdv56_i2 : std_logic;
signal clkdv56_i3 : std_logic;
-- signal clkdv14_4 : std_logic;
signal baud_pulse_i : std_logic;
begin
--Denna SRL dividerar inklockan med 14
Del_8 : SRL16E
generic map (
INIT => X"0000")
port map (
CE => '1', -- [in std_logic]
D => clkdv56, -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => '1', -- [in std_logic]
A1 => '1', -- [in std_logic]
A2 => '1', -- [in std_logic]
A3 => '0', -- [in std_logic]
Q => clkdv56_i1); -- [out std_logic]
Del_16_1 : SRL16E
generic map (
INIT => X"0000")
port map (
CE => '1', -- [in std_logic]
D => clkdv56_i1, -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => '1', -- [in std_logic]
A1 => '1', -- [in std_logic]
A2 => '1', -- [in std_logic]
A3 => '1', -- [in std_logic]
Q => clkdv56_i2); -- [out std_logic]
Del_16_2 : SRL16E
generic map (
INIT => X"0000")
port map (
CE => '1', -- [in std_logic]
D => clkdv56_i2, -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => '1', -- [in std_logic]
A1 => '1', -- [in std_logic]
A2 => '1', -- [in std_logic]
A3 => '1', -- [in std_logic]
Q => clkdv56_i3); -- [out std_logic]
Del_16_3 : SRL16E
generic map (
INIT => X"0001")
port map (
CE => '1', -- [in std_logic]
D => clkdv56_i3, -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => '1', -- [in std_logic]
A1 => '1', -- [in std_logic]
A2 => '1', -- [in std_logic]
A3 => '1', -- [in std_logic]
Q => clkdv56); -- [out std_logic]
DFF : FD
port map (
C => Clk, -- [in std_logic]
D => clkdv56, -- [in std_logic]
Q => baud_pulse); -- [out std_logic]
end architecture imp;
>
> /Johan
>
>
Article: 70586
Ted,
I think you have a bug in your VHDL. The reason you always see two
bright LEDs is that on every clock cycle _except_ the one in which you
access your peripheral, your else clause (counter<= "01010000";) is
active.
I think you intended your count_proc to be more like this (caveat: I'm
not fluent in VHDL):
count_proc: process(clk, control, counter, write_data)
begin
if clk'event and clk='1' and control='1' then
if ((write_data="00")) then
counter<=(OTHERS=>'1');
elsif ((write_data="01")) then
counter<=counter+1;
elsif ((write_data="10")) then
counter<="00001111";
else
counter<= "01010000";
end if;
end if;
end process count_proc;
By the way, your point1 #define should work, but you really should
make it a volatile pointer (as another poster said). Also, I'm more
used to seeing something like this:
#define point1 ((volatile int
*)(na_user_logic_altera_avalon_pwm_0_base))
and then to access the peripheral,
*point1 = 1;
Hope this helps.
etd606@hotmail.com (Ted) wrote in message news:<58811c5e.0406151809.2e18b0dc@posting.google.com>...
> Hello Guys,
>
> I am using the SOPC builder to design a simple system that integrates
> a couple of UARTS, a soft processor and a VHDL blackbox (Connected
> internally in user design logic). I export a 8-bit wide signal which
> are connected to LEDs on-board from the blackbox. I am using the Nios
> Development Board Pro Edition. My VHDL code is as follows:
> Libraries blah blah...
> entity count is
> port(
> clk: in std_logic;
> write_con: in std_logic;
> chipsel: in std_logic;
> write_data: in std_logic_vector(1 downto 0);
> export
> dataout: out std_logic_vector(7 downto 0));
> end count;
>
> architecture RTL of count is
>
> signal counter: std_logic_vector(7 downto 0);
> signal write_data_d: std_logic_vector(1 downto 0);
> signal resetn_d: std_logic;
> signal control: std_logic;
>
> begin
>
> control<= write_con and chipsel;
>
> count_proc: process(clk, control, counter, write_data)
> begin
> if clk'event and clk='1' then
> if ((write_data="00") and control='1') then
> counter<=(OTHERS=>'1');
> elsif ((write_data="01") and control='1') then
> counter<=counter+1;
> elsif ((write_data="10") and control='1') then
> counter<="00001111";
> else
> counter<= "01010000";
> end if;
> end if;
> end process count_proc;
>
> dataout<= counter;
>
> end RTL;
> ////////////////////////////////////////////////////////////////////////////
>
> My C code in the src directory is as follows:
>
> #define point1 *((int *)(na_user_logic_altera_avalon_pwm_0_base))
>
> void main()
> {
> while(1)
> {
> point1=1;
> }
> }
>
> I am assuming that I am writing directly to the write_data port (In
> VHDL) so I should be expecting a dim LED for the MSB and a bright one
> at the LSB. However, all I get is 2 bright LEDs (else condition). I
> checked the manuals but there wasn't any explicit instructions on how
> to use the header files for user design logic. Any direct help will be
> greatly appreaciated. Any reference to material will also be welcomed
> too. Cheerio!
>
> Ted
Article: 70587Uwe Bonnes wrote: > Marc Kelly <marc@redbeard.demon.co.uk> wrote: > > : Commandline tools fly, we place and route on a duel hyperthreded xeon (4 > : logical cpus) and setting 4 designs off in parallel gives impressive > : performace, made the time spent building large Makefiles worth while. > > I'd appreciated if you would post a simple command file. Makefiles/Perl/CSH/etc. are great at times for FPGA implementation, especially when you are doing something really unique with the way you are running the tools but if anyone wants to run the Xilinx tools from command-line, the easiest way is using xflow. Xflow is a single command that can run the Xilinx tools from HDL code to bitstream and most everything in between including simulation netlisting. An example command running xflow is the following: xflow -implement high_effort -tsim modelsim_verilog <design>.edf That command will take that EDIF file run it through all the of the implementation tools to take it through place and route with a high effort level, create a static timing report and create a timing simulation model for ModelSim in the Verilog language. Or if you want to run synthesis to bitstream, you could try: xflow -p xc2vp7fg456-6 -synth synplicity_vhdl -implement balanced -config bitgen <design_name>.prj Here it will synthesize a VHDL project through Synplicity targeting a 2VP7, implement the design using medium effort (balancing runtime and CPU effort) and then create a bitstream. The prj file contains all of the VHDL files for synthesis. There are many other ways to run and customize the tools. You can also specify customized options for any part of the flow if the blanket options are not to your liking. I thought I would share this as xflow has been around for a long time now but it seems not many know about it. I use it quite a bit to run the tools, especially when running the tools remotely (i.e. logging onto my Linux machine at work from home and running a quick nohup xflow run). -- BrianArticle: 70588
Do not feed back CLK0 to CLKFB. Then your input frequency can be as low as 1 MHz, if your output frequency is above 24 MHz. So you are o.k. You do not have a defined phase relationship between input and output, but that should not be a real loss, considering the ratio of your frequencies. 10 MHz and 27 MHz coincide only once every microsecond... Peter Alfke > From: tpalm@harmanbecker.com (Tarmo Palm) > Organization: http://groups.google.com > Newsgroups: comp.arch.fpga > Date: 21 Jun 2004 06:52:40 -0700 > Subject: Re: Frequency synthesizer. > >> I'm using the output CLKFX of a DCM in a virtexII pro with CLKIN = 10MHz. >> The M factor is 27 and the D factor is 10 so that I get CLKFX = 27MHz. Since >> the >> PLL mode does not support CLKIN < 24 MHz should I still keep the feedback >> loop >> between CLK0 and CLKFB. > > Hi, > > I had with the Spartan 3 DCM same problem. If you use Feedback, then > input freq. can't be below ca. 24 MHz. But if you do not use Feedback, > then input freq. can't be below ca. 1 MHz. Without Feedback is only > problem Phase. > > Tarmo PalmArticle: 70589
The XC3020 was introduced in 1988, which makes it 16 years old. By my rule of 1 FPGA year = 15 human year, the XC3020 is a 240-year old senior citizen. It deserves a quiet final resting place. (Museum or landfill) Get yourself a modern part (Virtex or Spartan) and enjoy the better performance and superior software support... Peter Alfke > From: General Schvantzkoph <schvantzkoph@yahoo.com> > Organization: Desert Porn > Newsgroups: comp.arch.fpga > Date: Sun, 20 Jun 2004 13:57:36 -0400 > Subject: Re: Is the Xilinix XC3020 atill supported? > > On Sun, 20 Jun 2004 17:45:27 +0000, Gregg C Levine wrote: > >> Hello from Gregg C Levine >> I have here an XC3020, and matching configuration storage EEPROM, an >> XC1736DPC, the were originally purchased for another project. We ended up not >> doing that project. Now we'd like to use both for something completely >> different. >> Are these parts still supported by Xilinix? Has anyone heard differently? >> We'd also >> prefer to do the programming under Linux. >> Gregg C Levine drwho8 atsign att dot net > > The 3000 series hasn't been supported for years. As for programing it in > Linux, Linus was in grade school when the 3000s were current so you aren't > going to find any Linux native tools that support them. However you should > be able to run the old DOS based XACT tools under wine.Article: 70590
Allan Herriman wrote: > On 18 Jun 2004 14:33:28 -0700, henk@mediatronix.com (Henk van Kampen) > wrote: > >>Allan: >>The Picoblaze cores are, although VHDL, just instantiations of LUTS >>and FF's. So a straight translation should be possible. > > > Possible, yes, but would it be frowned upon by Xilinx? I am not the official word of Xilinx but if you are buying Xilinx devices to use that code in, I doubt you will have a problem with this. If you are trying to re-target this code to another vendor's FPGA, then you might. The code was written to sell Xilinx FPGAs and as long as it does that in either VHDL or Verilog form, then I would not worry to much about the translation. My suggestion however is to just synthesize your design with the processor defined as a black-box in you Verilog code and use the provided NGC file. If you want to run a behavioral Verilog sim using it, then you can translate the NGC file to a structural UNISIM-based model using NGC2HDL. Since it sounds like the original is structural, this should be practically the same thing as the VHDL version. I would not suggest implementing the Verilog file produced by NGC2HDL however as it is only really intended to be used for simulation so I would stick with the original NGC file for implementation to be safe. -- Brian > > Regards, > Allan.Article: 70591
BlockRAM read during write: In Virtex and Spartan2, (i.e. before Virtex-II and Spartan3,) a write operation also performs a read of the new data and puts it on the Do lines. (Nice, but not very useful) In Virtex-II and Spartan3, the user can specify one of 3 options: 1. Write before read (as described above), 2. Read before write (i.e. reald the old data that is being overwritten) 3. "no change", hold Do unchanged , whatever it was before. Note that this only affects the read data output during a write operation, something most dsigners might not really be interested in. But if you want to read the previous data while you right the new one, then Virtex-II and Spartan3 offer an interesting option. This is all clearly described in the data sheet / user guide. Peter Alfke > From: pmihail@gmx.net (Acciduzzu) > Organization: http://groups.google.com > Newsgroups: comp.arch.fpga > Date: 20 Jun 2004 14:55:20 -0700 > Subject: XST: Inferring dual-port RAM from VHDL with BlockRAM > > Hi all, > > Maybe this question has been asked before, but I couldn't find a > suitable answer on this group until now. Having followed the coding > styles recommended by Xilinx, I ended up with the following code: > > > library IEEE; > use IEEE.std_logic_1164.all; > use IEEE.numeric_std.all; > > > entity dual_port_ram is > generic ( > WIDTH : integer := 32; > DEPTH : integer := 10 > ); > port ( > w_clk : in std_logic; > w_en_in : in std_logic; > w_addr_in : in std_logic_vector(DEPTH-1 downto 0); > w_data_in : in std_logic_vector(WIDTH-1 downto 0); > > r_clk : in std_logic; > r_addr_in : in std_logic_vector(DEPTH-1 downto 0); > r_data_out : out std_logic_vector(WIDTH-1 downto 0) > ); > end entity; > > > architecture xilinx of dual_port_ram is > > type memory_type is array (natural range <>) of > std_logic_vector(WIDTH-1 downto 0); > signal memory : memory_type(2**DEPTH-1 downto 0); > > begin > > write : process(w_clk) > begin > if w_clk'event and w_clk = '1' then > if w_en_in = '1' then > memory(to_integer(unsigned(w_addr_in))) <= w_data_in; > end if; > end if; > end process; > > read : process(r_clk) > begin > if r_clk'event and r_clk = '1' then > r_data_out <= memory(to_integer(unsigned(r_addr_in))); > end if; > end process; > > end architecture; > > > Yet, instead of BlockRAM, XST implements this as distributed RAM (with > combinational output) plus registers at the output, issuing the > following: > > INFO:Xst:1435 - HDL ADVISOR - Unable to extract a block RAM for signal > <memory>. The read/write synchronization appears to be READ_FIRST and > is not available for the selected family. A distributed RAM will > usually be created instead. To take advantage of block RAM resources, > you may want to revisit your RAM synchronization or check available > device families. > Found 1024x32-bit dual-port distributed RAM for signal <memory>. > > What is this read/write RAM synchronization after all? Maybe the > Xilinx folks (Peter Alfke & Co.) could help ;) > > ThanksArticle: 70592
Acciduzzu wrote:
> Hi Phil,
>
> I am targeting a Spartan-IIe btw. What I do not know is what that
> read/write synchronization is. Maybe you know also how I can infer a
> dual-ram for Spartan-IIe?
>
> Cheers
READ_FIRST is one of a few new modes added to the BLOCKRAM functionality
for the Virtex-II devices and later. This mode will put the "old data"
on the output of the port being written to before writing the new
contents to them memory array. Since Spartan-IIE is an older device
using the previous architecture BlockRAM, it does not support this
feature. To be honest, I do not think that message fully explains the
problem though. Synthesis tools look at templates to decide how to
transform code like this into appropriate resources. The code you chose
looked most like the templates it expect to see to create a READ_FIRST
RAM and thus that is why you got the result you saw. If you look at the
XST Users Guide and take the code example for the two clock read-through
RAM, it should be able to create the appropriate BlockRAM for the
Spartan-IIE architecture. I would modify your code like the following
and it should be able to create BlockRAMs for you:
---- Begining of code ------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity dual_port_ram is
generic (
WIDTH : integer := 32;
DEPTH : integer := 10
);
port (
w_clk : in std_logic;
w_en_in : in std_logic;
w_addr_in : in std_logic_vector(DEPTH-1 downto 0);
w_data_in : in std_logic_vector(WIDTH-1 downto 0);
r_clk : in std_logic;
r_addr_in : in std_logic_vector(DEPTH-1 downto 0);
r_data_out : out std_logic_vector(WIDTH-1 downto 0)
);
end entity;
architecture xilinx of dual_port_ram is
type memory_type is array (natural range <>) of
std_logic_vector(WIDTH-1 downto 0);
signal memory : memory_type(2**DEPTH-1 downto 0);
signal r_addr_int: std_logic_vector(DEPTH-1 downto 0);
begin
write : process(w_clk)
begin
if w_clk'event and w_clk = '1' then
if w_en_in = '1' then
memory(to_integer(unsigned(w_addr_in))) <= w_data_in;
end if;
end if;
end process;
read : process(r_clk)
begin
if r_clk'event and r_clk = '1' then
r_addr_int <= r_addr_in;
end if;
end process;
r_data_out <= memory(to_integer(unsigned(r_addr_int)));
end architecture;
---- End of Code ----
Good luck,
-- Brian
Article: 70593Stephen Williams wrote: > Neil Glenn Jacobson wrote: > >>>> Stephen Williams wrote: > > >>> Even if this is iMPACT bundled with ISE *6.1i*? I was under the >>> impression (based on APP notes and the like) that under Linux, >>> iMPACT starts supporing the PCIV cable at ISE 6.2. Certainly, when >>> I start impact, the radio button for Parallel Cable IV is grayed >>> out. Are you saying that when the cable arrives, I'll be able to >>> plug it in, install the Linux driver, and un-gray the selection? >> >> >> >> You know sometimes I wonder just how awake I am... >> Yes, Linux usage of the parallel cable was first supported in 6.2i >> thus all statements about Xilinx application support refer to release >> 6.2i and later. >> This means that if you are unable to upgrade to 6.2i or later and need >> to use the parallel cable and Linux then you are stuck. >> The (slower) MultiLINX cable is your only download option on Linux >> previous to 6.2i > > > I use ISE Foundation in support of my Icarus Verilog work. I use > it to make sure Icarus Verilog simulations can support the various > libraries shipped with Xilinx products, and I also use the back end > tools to help me validate the FPGA code generator. (I generate EDIF > files that I feed to map/par and FPGAEdit.) > > I have various Xilinx based boards that are a product of day-job, > and also a few other demo boards that people are likely to use while > playing with Icarus Verilog. (A Digilent board, a Wallace JTAG board, > an in-house PPC based board, another in-house board w/ Virtex and ACE...) > > Since this is a open source (read: GPL, free) project, I can't really > afford the $2000+ of ISE. In fact, my current ISE 6.1i is a generous > contribution from your employer. > > So yes, I'm stuck. But it's not holding me up. > > If you just want to download, you can use the free WebPACK version of iMPACT. This would include the latest software and be backward compatible with bitstreams generated from any version of ISE ou have. So you are not actually stuck.Article: 70594
Tom Dillon wrote: > > I also couldn't run ISE 6.2i on Mandrake 10.0 but would be interested in > trying under wine. Can some one point me to an install procedure to get > in working under wine. > While I am using RH9 rather than Mandrake 10, I suspect that to run the Linux versions of the tools you need to do: LD_ASSUME_KERNEL=2.4.1 export LD_ASSUME_KERNEL You can add that to the "settings.sh" script that Xilinx provides. For the Windows version, you should be able to run the Xilinx installer directly under Wine. I suggest using a December 2003 version of Wine for now. Some changes have been made in Wine since then that seems to break some things in the Xilinx tools. Be aware that running ISE under Wine, processing will run very slow without a patch to the Wine source (a bug in Wine's named pipe implementation). The command line tools however run fine. I will be happy to provide a patch to Wine if you want to try running ISE, which of course means you will need to use the Wine source, rather than a binary. -- My real email is akamail.com@dclark (or something like that).Article: 70595
Greg Neff wrote: > > Although Xilinx does sell most Spartan and SpartanXL devices still > (except those in PC84 and CSxxx packages), you have to use ISE 4.1 to > work with those families. > Also, it can be downloaded at no cost from: http://www.xilinx.com/webpack/classics/index.htm You do have to provide a design entry (synthesis) tool however as that is not included. I also agree that it is much better to use a newer device if possible however. -- BrianArticle: 70596
Stephen Williams wrote: > Neil Glenn Jacobson wrote: > >>>> Stephen Williams wrote: > > >>> Even if this is iMPACT bundled with ISE *6.1i*? I was under the >>> impression (based on APP notes and the like) that under Linux, >>> iMPACT starts supporing the PCIV cable at ISE 6.2. Certainly, when >>> I start impact, the radio button for Parallel Cable IV is grayed >>> out. Are you saying that when the cable arrives, I'll be able to >>> plug it in, install the Linux driver, and un-gray the selection? >> >> >> >> You know sometimes I wonder just how awake I am... >> Yes, Linux usage of the parallel cable was first supported in 6.2i >> thus all statements about Xilinx application support refer to release >> 6.2i and later. >> This means that if you are unable to upgrade to 6.2i or later and need >> to use the parallel cable and Linux then you are stuck. >> The (slower) MultiLINX cable is your only download option on Linux >> previous to 6.2i > > > I use ISE Foundation in support of my Icarus Verilog work. I use > it to make sure Icarus Verilog simulations can support the various > libraries shipped with Xilinx products, and I also use the back end > tools to help me validate the FPGA code generator. (I generate EDIF > files that I feed to map/par and FPGAEdit.) > > I have various Xilinx based boards that are a product of day-job, > and also a few other demo boards that people are likely to use while > playing with Icarus Verilog. (A Digilent board, a Wallace JTAG board, > an in-house PPC based board, another in-house board w/ Virtex and ACE...) > > Since this is a open source (read: GPL, free) project, I can't really > afford the $2000+ of ISE. In fact, my current ISE 6.1i is a generous > contribution from your employer. > > So yes, I'm stuck. But it's not holding me up. > > Ooops. I forgot. Xilinx does not release a LInux version of WebPACK. Nix that previous message.Article: 70597
You could also allow XST to read in the "module" NGC with -read_cores option. Xst will read in your NGC to recognize the logic and infer IO appropriately to the ports that need IO buffers. However, your solution of a wrapper is more general and more appropriate. As it is possible to use this approach in other synthesis tools. As your customer may prefer a 3rd party synth tool over XST. Jake Janovetz wrote: > Yes, but there are some pins that I needed to add iobufs on, so this > isn't an option. XST applies that parameter to all i/os, and you > cannot apply selectively. > > I ended up having to write a wrapper for my module. The wrapper > contains the I/Os and requires synthesis, but the underlying block > does not. > > Jake > > > "Brannon King" <bking@starbridgesystems.com> wrote in message news:<cav27m$svb@dispatch.concentric.net>... > >>In XST use the -iobuf NO parameter to turn off the automatic buffer >>insertion. >> >> >>"Jake Janovetz" <jakespambox@yahoo.com> wrote in message >>news:d6ad3144.0406171545.68f3e376@posting.google.com... >> >>>(I'm not sure why, but Google apparently loses about 50% of my posts, >>>so I'll try this again) >>> >>>I have a few modules that I would provide to customers. They are all >>>quite simple, but by not providing Veriog/VHDL I shelter them from the >>>implementation details and possible warnings that would come from >>>synthesis. So, I'd prefer to provide library "objects" in NGC format. >>> >>>Most of the modules are 'internal' (not requiring IOBs), but one needs >>>to map to IO pins, including an 8-bit bidirectional bus. If I -don't- >>>include IOBs in the module, the parent design synthesizes OBUFs for >>>the bidir bus and completely ignores the inputs. If I manually map >>>the OBUFTs within the module, I get complaints during parent synthesis >>>because apparently the parent is adding OBUFs which compete with the >>>OBUFTs in the module. >>> >>>I'd prefer a solution which requires as little 'extra' work on the >>>parent side of things, but would appreciate any suggestions. >>> >>> Cheers, >>> Jake -- / 7\'7 Paulo Dutra (paulo.dutra@xilinx.com) \ \ ` Xilinx hotline@xilinx.com / / 2100 Logic Drive http://www.xilinx.com \_\/.\ San Jose, California 95124-3450 USAArticle: 70598
Peter Alfke wrote: > > Just to clarify Rickman's "Two-clock-cycle thing": > Xilinx BlockRAMs need ONE clock to perform any operation, be it a read or a > write. As a bonus, the write operation also performs a read operation on the > same location, showing either the old or the new data (user option). > And this is all on one port. You can obviously use the other port > independently from the first. > The one thing you cannot do is an asynchronous read without a clock edge. > > If anybody has any questions about Xilinx BlockRAMs, I am more than happy to > explain. Perhaps I didn't understand the documentation. I think I got mixed up in the description of the read port latches. Sometimes I forget the distinction between latches and registers. First, let me say that I am designing a stack using a single block ram. My understanding is that I can use the RAM as either a single port ram with a single address bus, a write data bus and a read data bus or a dual port ram with two independant interfaces like the single port interface. Using the single port interface it appears to me that the address and control signals are registered. Looking at the timing diagram for the WRITE_FIRST option, I see that the data output changes with one clock delay. So can I consider the register to be on the input side (address, control) with the read data output using no register? I belive that will work for a stack. When data is being pushed, the incremented address is set up and the write is clocked in, while the data output is steady until the clock edge (old top of stack). Following the clock edge, the data written will be presented on the output (new top of stack). To pop the stack, the address is decremented and a read is done with the new data available following the clock edge (new top of stack). A write (pop and push) is done by not changing the address and registering a new write with the read data changing after the clock edge. Will the single port WRITE_FIRST ram mode work this way? I also need program and data memories and the register delay may interfere with full speed operation on these. I might be able to clock the data and instruction memory from "not clock" to allow the read data to be available during the second half of the current clock cycle. This may result is a bit slower clock cycle, but it should be better than a two clock cycle. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 70599
John Larkin wrote: > > Forgive me if this has been asked before, but does anybody have > comments or links to simple methods of compressing/decompressing > Xilinx configuration bitstreams? I've been perusing a few of my .rbt > files, and they have long bunches of 1s and 0s (interestingly, > different designs seem to have more 1s, others mostly 0s.) I'd think > that something very simple might achieve pretty serious (as, maybe > 2:1-ish) compression without a lot of runtime complexity. We generally > run a uP from EPROM, with the uP code and the packed Xilinx config > stuff in the same eprom, with the uP bit-banging the Xilinx FPGA at > powerup time. So a simple decompressor would be nice. > > I did google for this... haven't found much. I see that no one has addressed the basic issue of just how compressable these files are and when you can expect to achieve good compression and bad compression. The runs of 1's and 0's are typically located in areas of the bitstream that represent unused portions of the chip. So for designs that are sparce, you can get high levels of compression, not unlike the basic form of compression that Xilinx provides in the Virtex chips (frame compression). But as the utilization of the chip goes up, the bitstream becomes more random and the compressability of the bitsteam goes down. It largely does not matter how you compress the data, once the chip is largely used, you won't be able to get much compression. So in the end, compression will help you reduce the size of your bit steam when the design is much smaller than the chip (where you could use a smaller chip), but if your design grows the compression will be reduced and you will end up needing nearly as large a memory as an uncompressed bit stream. So reducing the size of the chip may be a better solution if your memory will ultimately limit the size of your design. A smaller FPGA reduces the size of the bit stream and also costs less. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z