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Krishna Kumar wrote: > > Hello, > I am trying to choose between a Xilinx XC3S1000 FG456 and XC2V1000 > FG456. Listed below is a comparison based on the parameters that I am > looking for: > > XC3S1000 FG456 XC2V1000FG456 > I/Os 333 324 > GCK 8 16 > Price $47(per 100 piece) >$120 (per 100 piece) > > Now there is a vast difference in price between the 2. The user I/Os > are comparable and I think 8 GCK in spartan 3 should suffice. But my > only concern is Spartan 3 is not yet in full production. Xilinx is > manufacturing only "ES" parts which is an abbreviation for Engineering > samples. I hear from the local FAEs that ES may have some errata and > the availability is not guaranteed. What does the errata contain? Does > anybody have any info on the pricing, availability and contents of the > errata? I need to know my devices thoroughly before I can use them in > my design. Any suggestions are welcome. That is news to me. Over a month ago, I was quoted a delivery of around 8 weeks IIRC. The ES parts I could have from stock. The part I was asking about was the XC3S400, so perhaps the 1000 is a bit behind. Did they tell you *when* you could expect production parts? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 71901
Gupta wrote: > > Hi > > I am new to the newsgroup and the FPGA world. I am trying to figure > out how I should choose between the various FPGA offerings. Xilinx > and Altera are clearly the market leaders, but the Flash-based FPGAs > from Actel seem compelling (denser than Xilinx ?), but they seem to be > a generation behind (does that matter ?). Also, Lattice recently > announced low cost FPGAs with DSP blocks (50 bucks). Also, I saw on > Lattice's website that they too have Flash based FPGAs. Does Flash > really have an advantage over SRAM (claim is that Flash is one > transistor versus 6 transistors required for SRAM) ? > > Got any tips on how to evaluate the various offerings ? I am looking > at about a 1 million gate design, with moderate/easy performance > requirements. Does this analysis change if I am working on a 500K > gate design ? Whether a part is a generation behind or how many transistors are in the config memory is not really relvant to the board designer, now is it? You should care about speed, size, price, availability and support. Sure one transistor should be smaller than 6, but if it is not reflected in the price, then why would you care? Focus on the requirements you care about, not how the chip maker meets your requirements. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 71902
Hi all, Hoping for a little bit of insight from all of you: We're currently looking at implementing a small, low-cost PLD implementation on one of our products -- managed Ethernet switch. As Xilinx and Altera are fighting tooth and nail to get in, it's difficult to discern who is telling the truth. The most bothering of all are rumours that Xilinx has yet to perfect the 90um fab, and has dumped IBM as one of their 90um suppliers (and are left with just one fab). As a result customers have been waiting and waiting for parts. Is this true at all? We're looking at the Spartan-3 3S50ES part. Another rumour is that other customers have yet to receive production versions of this part, and have actually be shipped 3S50JES parts (where the J is indicative of a stripped down ram-less, DLL-less, non-3.3V compatible part). This is concerning as we require 3.3V compatibility. Anyone here have any similar experiences or can tell otherwise? TIA, Gordon Lau Hardware Designer RuggedCom Inc.Article: 71903
I expect their 90um fab is fine. It's the 90nm fib that I'd worry about... cheers, Syms. "Gordon" <elf_ster@hotmail.com> wrote in message news:4a2e9945.0408031133.2ec1e29f@posting.google.com... > > As Xilinx and Altera are fighting tooth and nail to get in, it's > difficult to discern who is telling the truth. The most bothering of > all are rumours that Xilinx has yet to perfect the 90um fab, and has > dumped IBM as one of their 90um suppliers (and are left with just one > fab). As a result customers have been waiting and waiting for parts.Article: 71904
"Krishna Kumar" <krishk24@gmail.com> wrote in message news:e23e0547.0408030936.767426b1@posting.google.com... > Hello, > I am trying to choose between a Xilinx XC3S1000 FG456 and XC2V1000 > FG456. Listed below is a comparison based on the parameters that I am > looking for: [snip] > samples. I hear from the local FAEs that ES may have some errata and > the availability is not guaranteed. What does the errata contain? Does > anybody have any info on the pricing, availability and contents of the > errata? I need to know my devices thoroughly before I can use them in > my design. Any suggestions are welcome. [snip] At present, there are no known errata for the XC3S1000 FPGAs. Errata for the other Spartan-3 FPGAs is available to registered users of the Xilinx Support web site at ... http://www.xilinx.com/support For pricing and availability, I would recommend contacting your local Xilinx sales representative, listed at the following link. http://www.xilinx.com/company/sales/ww_reps.htm#TEXAS If I remember Texas geography correctly, Richardson is close to Dallas. Bonser-Philhower Sales 689 W. Renner Rd., Suite 101 Richardson, TX 75080 (972) 234-8438 Fax: (972) 437-0897 Alternatively, the local Xilinx distributor should also have the same information. http://www.xilinx.com/company/sales/ww_disti.htm --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/II/IIE FPGAs http://www.xilinx.com/spartan3 --------------------------------- Spartan-3: Make it Your ASICArticle: 71905
MIKE, It's like asking the question how big a gas tank do I need on my sports car to get 300 miles on a tank. It all depends on who's driving it and where. If you really want worst case, you've gotta plug in the max toggle rate on all the CLBs, FFs and BRAMs to the power consumption tool. But is anyone gonna drive with their pedal to the metal constantly for an hour? Not even Michael Schumacher does that. Cheers, Syms.Article: 71906
>Correct, jogging all the way in a circle around that package is >130 mm. >Jogging in wide circles may be a healthy exercise for humans, but it is not >recommended for timing-critical signals. I think it's reasonably common to use a "long" trace on a PCB as a short delay. But suppose the delay is "timing-critical"? How stable is FR4 over temperature? Humidity? Is there anything else that influences the delay on an existing board? How repeatable is the delay from batch to batch? I think the delay only depends upon the dielectric constant and that probably depends upon the ratio of glass to plastic. Are there layout patterns that make it easier for the board house to make the same result consistently? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 71907
No worries, Philip. I'm just relieved we seem to have got away with mentioning the 'M' word without getting a 200 post thread! I reckon your excellent FAQ with the articles from yourself and various distinguished contributors is doing its job! Cheers, Syms. "Philip Freidin" <philip@fliptronics.com> wrote in message news:b8ptg0hbggb7gngqdh8kbekmgt6f5lusuo@4ax.com... > > Thanks again for the ref to a good article, > > PhilipArticle: 71908
\On Wed, 21 Jul 2004 13:02:10 -0700, George wrote: > I've attempting to select an FPGA for a new design. > > The design will have 9 of the following: > 12 bit latches > 12 bit down counter > 1 bit output latch > > So one measure of the size might be 25 registers * 9 = 225 registers. > > The counting freq is 15 MHz. > > The latches get loaded from an existing micro. So I need a 12 input > pins for a data buss, 4 input pins for which register, a clock pin and > let's say 4 pins for control lines. > Along with the 9 output signals. > > So another measure is 12+4+1+4+9 = 30 pins not counting power and > ground. > > It would also be desirable to be packaged in a PLCC but TQFP in ok. > > And the device should be reprogrammable using JTAG (add 4 more pins). > > Voltage is not much of an issue. However 5 V tolerant I/O would be > nice. > > I've looked at Lattice and Altera and haven't found the perfect > solution. I can use larger than necessary Altera devices (ACEX1K) > but that seems to be the wrong direction. > > Any suggestions/recommendations. > > Thanks > George You don't need an FPGA for something that simple, look at CPLDs.Article: 71909
I'm looking at using a V2P RocketIO transmitter to synthesize a clock by bypassing the 8B10B encoder and feeding it 01010101 data words. I would vary the output clock frequency by varying the reference clock and/or the data pattern (00110011, 00001111, etc.). Is there any reason this would not work? Thanks, Robert (Reply email address is bogus. Please reply to group.)Article: 71910
Hal, The use of pcb traces for circuits (delays, filters, etc.) has a long tradition. I have heard that the characteristics can be held to +/- 3% easily (almost without thinking as long as the materials used to make the board are specified: layer thicknesses, pre-preg thicknesses, copper thickness). Cell phones are just one miracle that use a lot of pcb 'components'. Austin Hal Murray wrote: >>Correct, jogging all the way in a circle around that package is >130 mm. >>Jogging in wide circles may be a healthy exercise for humans, but it is not >>recommended for timing-critical signals. > > > I think it's reasonably common to use a "long" trace on a PCB > as a short delay. But suppose the delay is "timing-critical"? > > How stable is FR4 over temperature? Humidity? Is there anything > else that influences the delay on an existing board? > > How repeatable is the delay from batch to batch? I think the > delay only depends upon the dielectric constant and that probably > depends upon the ratio of glass to plastic. Are there layout > patterns that make it easier for the board house to make the > same result consistently? >Article: 71911
Does anyone know if there exists an FPGA development board that has a PCI express interface? I would also be nice if it had video i/o on board I need to do real time quick image processing, and eventually face detection algorithms... thanks Geoffrey Wall Masters Student in Electrical/Computer Engineering Florida State University, FAMU/FSU College of Engineering wallge@eng.fsu.edu Cell Phone: 850.339.4157 ECE Machine Intelligence Lab http://www.eng.fsu.edu/mil MIL Office Phone: 850.410.6145 Center for Applied Vision and Imaging Science (will be updated soon) http://cavis.fsu.edu/ CAVIS Office Phone: 850.645.2257Article: 71912
Does anybody know how this works for a LCD display? Using my laptop as a reference system, if I select the 1024 x 768 I get a full screen display. If I select a lower resolution display, 800 x 600 I get a smaller size image inset on the display. Is this characteristic of LCD displays? If somebody could point me to a resource that describe how to generate the signals necessary for LCD display I would greatly appreciate it. Derek SimmonsArticle: 71913
I see no reason to doubt this. In fact, I intend to do the same thing. Note that in V2Pro the parallel interface is 10 or 20 bits wide, not 8 or 16 bits. This requires some digital trickery once you go beyond 4-bit patterns on the parallel side. Let me know if you run into any snags... Peter Alfke > From: "Robert Sefton" <rsefton@abc.net> > Newsgroups: comp.arch.fpga > Date: Tue, 3 Aug 2004 13:36:09 -0700 > Subject: clock synthesis with RocketIO > > I'm looking at using a V2P RocketIO transmitter to synthesize a clock by > bypassing the 8B10B encoder and feeding it 01010101 data words. I would > vary the output clock frequency by varying the reference clock and/or > the data pattern (00110011, 00001111, etc.). Is there any reason this > would not work? > > Thanks, > > Robert > > (Reply email address is bogus. Please reply to group.) > >Article: 71914
Hi, I need to generate a 1-bit signal with very high resolution on the position of the edges. I would need about 2 to 3GHz resolution. It is quite hard to have a 3Ghz clock nowadays, so I wonder if the RockedIO could be used for that. Thanks, DaveArticle: 71915
"Steven K. Knapp" <steve.knappNO#SPAM@xilinx.com> writes:
> At present, there are no known errata for the XC3S1000 FPGAs. Errata for
> the other Spartan-3 FPGAs is available to registered users of the Xilinx
> Support web site at ...
> http://www.xilinx.com/support
I'm registered, but I certainly can't find any errata there. Doing a
search for "errata" says:
Query was : errata
Your search matched 0 of 0 documents.
0 - 0 of 0 are presented, ranked by relevance.
A little more help finding it would be appreciated, as without seeing
the errata I can't tell whether the XC3S400 ES parts will be acceptable for
my design, or whether I'll have to wait for non-ES.
Thanks,
Eric
Article: 71916I'm an analog engineer who's familiar with analog PLL's but not with digital PLL's. I've been searching the internet for the NCO equivalent of Kvd of an VCO and the Kphi of an 'exclusive or' phase detector. I thought if I had those, I could use the analog transfer functions to analyzer a PLL. Also, can you point me toward any NCO vendor webpages that would have some application note using their product in an DPLL. Thanks for any help. D. KruseArticle: 71917
You can use RocketIO. In Virtex-IIPro it can handle 3.125 Gbps, which means a ~320 ps bit time. Just run the MGT with a 156.25 MHz Fref, and apply the appropriate data pattern on the parallel ( 10 or 20-bit) side. In Virtex-IIProX you can go more than 3 times faster... Peter Alfke > From: gretzteam@hotmail.com (David) > Organization: http://groups.google.com > Newsgroups: comp.arch.fpga > Date: 3 Aug 2004 14:11:48 -0700 > Subject: Can I use RocketIO to generate pulse edge with very high precision? > > Hi, > I need to generate a 1-bit signal with very high resolution on the > position of the edges. I would need about 2 to 3GHz resolution. It is > quite hard to have a 3Ghz clock nowadays, so I wonder if the RockedIO > could be used for that. > > Thanks, > DaveArticle: 71918
Rune Christensen wrote: > Hello > > Is it possible to connect a RS422 differential signal directly to a FPGA > instead of using a converter from RS422 to TTL voltage levels? > Would it be possible for a FPGA to create a RS422 signal? > > Is there any information about this on the internet? Possible, yes. Practical, maybe not. Most FPGAs have differential IP modes, so could accept RS422 IPs, with the caveat, WITHIN their common mode range. For true RS422/485 devices, that is around -7V..+12V, which allows ground movement between ends of the cable. FPGA pin common mode is much less than this, but you could extend it with a resistor pad (which also attenuates the wanted signal ) Then there is ESD protection. Most separate RS422/485/CAN transcievers have higher tolerance to ESD, than FPGA. RS422 output needs sufficent drive current, and balanced drive, but that is within the capability of FPGA. For short-haul, and within-the-box signaling, this could be do-able, but perhaps not for connection to 100m cables in a factory... -jgArticle: 71919
"M.Randelzhofer" <techseller@gmx.de> wrote in message
news:2na4hoFule1vU1@uni-berlin.de...
> Hello Steve,
>
> thanks for the information.
> The power tool is a nice piece of SW, but fully unusable for my purposes.
> I want to design a robust evaluation system.
> Therefor i need a worst case maximum value for the currents for the
> X3S200TQ144 and X3S400TQ144 devices.
> It's not the exact value like 845,8765mA and 988,887mA i need for the
given
> voltages, but the general range.
> I expect, there are special test patterns for your semiconductor end
tests -
> like all FF's toggling or shifting which needs a certain amount of current
> on vccint or vccaux.
> What's the average current in these 'all chip resources tests' at the
> thermal limit ?
The Web Power Tool will provide this information. If you believe the end
application will have all nodes switching, then you can model this in Web
Power Tool. However, most applications have a much smaller portion of the
device toggling.
However, you may be asking a different question. The performance of a
device is guaranteed up to a specific junction temperature--85C for the
commercial temperature range or 100C for the industrial.
Using the expected ambient temperature range, zero airflow, and the thermal
characteristics of the package, you can calculate the maximum possible power
that you can dissipate through the package and not violate the maximum
junction temperature.
For example, the Theta-JA of the XC3S200 in the TQ144 package is 34.1
degrees C per Watt. Assume that the ambient operating temperature is 25C.
25C + 34.1C/W (P) = 85C
Solving for P ...
P = 1.76 Watts maximum
> Ok, this question is rather weird because of the limit definitions, but i
> hope you understand what i mean.
> The Xilinx Spartan-2 Starter Kit (an excellent and low priced system) uses
a
> 500mA regulator for the VCCAUX and a 1000mA regulator for VCCINT. Are
these
> ranges recommended from Xilinx, or a rough estimation of an experienced
> designer ?
Although the Spartan-3 Starter Kit board has an XC3S200 in the FT256 ball
grid array package, the regulator is sized larger than actually required.
We used the Web Power Tool to generate a number of expected applications.
The board as presently defined meets the requirements of every XC3S200
design we could contemplate. It also meets most every XC3S400 design and
almost every XC3S1000 design, giving ourselves maximum flexibility with the
PCB design. Yes, you can create pathological designs that will break one or
more supply limits, but these require effort.
If you are interested, the schematics are available online.
Spartan-3 Starter Kit Board web site
http://www.xilinx.com/s3boards
Schematics (part of the Spartan-3 Starter Kit Board User Guide starting on
page 53)
http://www.xilinx.com/bvdocs/userguides/ug130.pdf
---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
General Products Division
Spartan-3/II/IIE FPGAs
http://www.xilinx.com/spartan3
---------------------------------
Spartan-3: Make it Your ASIC
Article: 71920Aaaargh! Looks like the search function was broken. I just checked it a few minutes ago and all was working. To save time, here is a specific link. How can I view errata documentation and receive an alert if it changes? http://support.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=18815 --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/II/IIE FPGAs http://www.xilinx.com/spartan3 --------------------------------- Spartan-3: Make it Your ASIC "Eric Smith" <eric-no-spam-for-me@brouhaha.com> wrote in message news:qhk6wfj533.fsf@ruckus.brouhaha.com... > "Steven K. Knapp" <steve.knappNO#SPAM@xilinx.com> writes: > > At present, there are no known errata for the XC3S1000 FPGAs. Errata for > > the other Spartan-3 FPGAs is available to registered users of the Xilinx > > Support web site at ... > > http://www.xilinx.com/support > > I'm registered, but I certainly can't find any errata there. Doing a > search for "errata" says: > > Query was : errata > Your search matched 0 of 0 documents. > 0 - 0 of 0 are presented, ranked by relevance. > > A little more help finding it would be appreciated, as without seeing > the errata I can't tell whether the XC3S400 ES parts will be acceptable for > my design, or whether I'll have to wait for non-ES. > > Thanks, > EricArticle: 71921
If you are using a Virtex 2 Pro device, you can use iMPACT to load the SRAM via the boundary-scan interface of the Power PC Vivek Joshi wrote: > I had a question on whether you can use Chipscope pro to load an > external SRAM connected to the FPGA. I want to use ChipSCope Pro to load > data into an SRAM, is there a way to automate this, any suggestions or > comments regarding this? Is this a feasible idea?Article: 71922
"Gordon" <elf_ster@hotmail.com> wrote in message news:4a2e9945.0408031133.2ec1e29f@posting.google.com... > Hi all, [snip] > As Xilinx and Altera are fighting tooth and nail to get in, it's > difficult to discern who is telling the truth. The most bothering of > all are rumours that Xilinx has yet to perfect the 90um fab, and has > dumped IBM as one of their 90um suppliers (and are left with just one > fab). As a result customers have been waiting and waiting for parts. I see that our friendly competitor's spin machine has been at it again. UMC (not IBM) is and always was the primary manufacturing facility for Spartan-3 FPGAs. It is true that other Xilinx product lines used IBM as a production line and that Xilinx built some initial Spartan-3 FPGA engineering samples at IBM but there is no connection between IBM and Spartan-3 FPGA production. Xilinx will likely be in production on 90 nm for 4 quarters and 2M+ units before the nearest competitor. Xilinx has shipped over 600K Spartan-3 FPGAs to date, mostly to fulfill some initial high-volume customers. This quarter, Xilinx will produce another 600K+ units and will stock distributors with Spartan-3 FPGAs in about 3 weeks. By the end of September, there should be relatively good inventories up through the XC3S1500. The XC3S200 and XC3S400 are in full production now with the XC3S50, XC3S1000, and XC3S1500 starting production this month. The XC3S2000 through XC3S5000 will be available 1H05. > Is this true at all? We're looking at the Spartan-3 3S50ES part. > Another rumour is that other customers have yet to receive production > versions of this part, and have actually be shipped 3S50JES parts > (where the J is indicative of a stripped down ram-less, DLL-less, > non-3.3V compatible part). > > This is concerning as we require 3.3V compatibility. Anyone here have > any similar experiences or can tell otherwise? The XC3S50 and XC3S1000 are the two most recent additions to the product family and are presently ramping for full production. XC3S50 ES parts are available through Xilinx distributor, but may not be in their inventories just yet depending on package style. The XC3S50 has four 18K block RAMs, two Digital Clock Managers (DCMs), and is 3.3V compatible. You will not receive the older XC3S50J unless you specifically order the 'J' device. Xilinx stopped building the 'J' engineering samples quite awhile ago. --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/II/IIE FPGAs http://www.xilinx.com/spartan3 Tel: (408) 626-7447 E-mail: steve.knapp@xilinx.com --------------------------------- Spartan-3: Make it Your ASICArticle: 71923
[snip] > We're looking at the Spartan-3 3S50ES part. I forgot to mention one other item. If you want to create some initial designs for your XC3S50 application without needing to build hardware, you might want to investigate the Spartan-3 Starter Kit Board. It has an XC3S200 FPGA in the FT256 package, plus a host of other interfaces, 1M of SRAM, a JTAG download cable, plus software. The board is in stock and sells for $99 plus applicable tax and shipping. Spartan-3 Starter Kit Board http://www.xilinx.com/s3boards --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/II/IIE FPGAs http://www.xilinx.com/spartan3 --------------------------------- Spartan-3: Make it Your ASICArticle: 71924
Simon wrote: > So, I'll consult the collective wisdom of the group - which is probably > what I ought to have done in the first place :-) Can I ask if there's > anyone who's used Foundation on both architectures... > > o If there are any differences between the two ? > o Is there anything you can't do from the Linux environment ? > o Is Linux a completely self-contained environment for development ? > o How stable is it ? > o What version of Linux are you running it on ? > o Have you tried it on an AMD64 processor ? > o Anything else I've missed ? I'm running it on Linux/AMD64 (A dual Opteron) w/ SuSE Linux. It works well enough that I can't say anybody here has even bothered to install it under Windows. All the GUI stuff is embarassingly slow. That toolkit they are using is clearly a dog in need of a slug. However, all the command line tools work just fine. It seems to be stable enough. impact also works fine, but none of the external hardware devices work on AMD64. The PC-IV cable can be made to work on any i386 Linux, because there is a .a and source code shell to allow you to compile the drivers for your kernel (if you must) but that precompiled .a file cannot be used on AMD64, so the Linux drivers are useless on AMD64. Impact makes ACE files well enough. -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."
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