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When one is working on a development board one is often turning on parts of the board and turning off other parts. So when I tried to shut down one chip hanging off my Spartan 3 by basically doing nothing with its outputs I got this NgdBuild:755 Could not find net(s) error and it would not generate. It would seem to me if the synthesizer saw constraints not used in the source VHDL, it should possibly give a warning, but should be able to complete the design. PACE wouldn't open but I removed the outputs (that is: the FPGA inputs) from the constraint file with the text editor. This is remenisent of compilers that complain when a subroutine doesn't get called. I would like to enter all my board design IOs into the constraint file whether I use them or not. BradArticle: 72101
> Eirik Seljelid wrote: > > considered the PA7536, but I find it way easyer to get an older version > > of ABEL, compile the code for 82S100 and burn the chips. > Eirik, Have you located it? I'm not familiar with the 82S100. I have an ancient version of ABEL, circa 1988. Is that too ancient? MikeArticle: 72102
Hi Brad,
Brad Smallridge wrote:
> It would seem to me if the synthesizer saw constraints not used in the
> source VHDL, it should possibly give a warning, but should be able to
> complete the design.
[snip]
> I would like to enter all my board design IOs into the constraint file
> whether I use them or not.
Indeed. I think you want to pass the -aul option to ngdbuild:
From `ngdbuild --help`:
-aul Allow unmatched LOC constraints
I'd like the inverse of this - the option to generate an error (not just
a warning) if there are unconstrained pins. On a development board with
lots of off-chip resources, randomly scattering unLOCd pins to the 4
winds can yield very unpredictable results! I ended up writing a little
awk script that parses the build log to see if the number of LOCd pins
matches the total number of pins in the design.
Cheers,
John
Article: 72103
yujia jin wrote:
> Hi,has anyone used ncsim for simulation with edk6.2.03i? I am having
> trouble finding the precompiled edk cores (e.g. microblaze) for ncsim.
> The documentation states that ncsim is supported, but the compedklib
> utility complains that it can't find any precompliled cores nor does
> any thing resembling it exists anywhere in the EDK installation.
> Thanks in advance for any help.
Have you tried `compedklib --help` ?
==== quote====
Use Case I: Compiling HDL sources in the built-in repositories in
the EDK
The most common use case is as follows:
compedklib -o <compedklib-output-dir-name>
-X <compxlib-output-dir-name>
In this case the 'pcores' available in the EDK install are compiled
and the stored in <compedklib-output-dir-name> . The value to the
'-X' option indicates the directory containing the models outputted
by 'compxlib'. such as the 'unisim', 'simprim' and 'XilinxCoreLib'
compiled libraries.
==== end quote ====
Does that work?
Regards,
John
Article: 72104Hi Barron, Barron Barnett wrote: > I am currently working with a digilent pegasus board and trying to > connect wtih their Ram module using the OPB_emc. The problem is I am not > really sure where to start, I have the data sheets and shcematics for the > ram and boards. But i am confused on how the external memory controller > itself will deat with the ram. Any good tutorials you can point me towards > doing this would be very helpful. First I'd ask your Digilent FAE. They should have a suite of reference designs that exercise the various hardware resources on each board. Secondly the emc controller is not a particular complicated beast - you basically need to translate the timing requirements of your SRAM into the various timing parameters specified to the emc controller. The emc data sheet also has extensive discussion about mapping the signals, in terms of physical memory width vs logical (bus) width and so on. If you are still stuck, post some details about the SRAM devices and how they are connected to the FPGA, we might be able to provide some pointers. Regards, JohnArticle: 72105
This site has some very good tutorials which got my and my colleague started with EDK. http://www.eece.unm.edu/xup/ Although they use a ML300 board they explain very thoroughly how to connect every signal. Hope it helps... With regards // JonasArticle: 72106
hi I am doing a research on comparing the different design methodologies for vhdl with altera maxplus2 and xilinx ise webpack software. I am trying to find out the propagation delay ie maximum delay parameter in the synthesis report from altera maxplus2 but couldnt find it?can any body of u help me in this regard? in the maxplus2 there is one option assign > global project timing requirements.. here we need to enter the value of the propagation time.but i thought it is some value which is decided after the design is synthesized and is available in the synthesis report as in xilinx ise webpack...... some light on this topic will be of great help to me . thank you shahabArticle: 72107
Does anyone have impact running under wine? Can I configure my Spartan3 Starter Kit from GNU/Linux? If so, how? I have tried to run impact under wine but it fails to connect even as root. Perhaps this is due to some wrong configuration in my wine.conf. Thanks AndrewArticle: 72108
"Digvijay Raghavan" <digvijaymr@yahoo.com> wrote in message news:7e63f9c5.0408060326.4cc87edb@posting.google.com... > Hi, > I am not even a novice in this area but I do know that the > technology that IBM was employing was trying to mimic logic levels > similar to semiconductor based logic. They had a lot of problems doing > that and the final clock frequencies that they could achieve was > rather low for the investment. It was then that two researchers from > MSU, Moscow (Dr Likharev and Dr Semenov) came up with the idea of RSFQ > logic wherein logic is defined in terms of the presence or absence of > a quantum flux in the presence of a clock (which again is quantum flux > pulse). I hear that this approach has infact generated a lot of > quantifiable results and recently NEC, Japan even demonstrated a > partially functional RSFQ Processor. Here, in the U.S, Hypres Inc in > collaboration with a Prof from Stony Brook has generated a lot of > results and are even currently funded by NSF or DARPA for a RSFQ ADC > to be employed in the very first Software Defined Radio. Seeing all > this, I believe that "superconducting chips" are far from dead. Maybe > for certain applications, they might prove to be the only solution, > only time can tell. I have no idea though about what it takes to be a > researcher in this area nor can I comment on the future that it > entails. ISTR that some of the work on quantum computers is using super cooled circuitry. Might be worth reading up on that. StephenArticle: 72109
Hi, I have read that using a single always block(synchronous) for implementing a state machine is not a good practice. Can somebody tell me how does the synthesis tool handle this?? Thanks in advance! SandhyaArticle: 72110
You may want to check out the websites for FCCM, ERSA, and FPL conferences for conference programs. "supradeep narayana" <supradeep@gmail.com> wrote in message news:3e4ee61a.0408051030.43438c60@posting.google.com... > Hi, > I am looking for a topic for my Ms thesis on reconfigurable systems > design. I would like to know which are the current topics of research > in this area. > I would very much appreciate your help. > thanking you, > supradeepArticle: 72111
Shahab, I suggest using the Altera Quartus II web edition software instead of Maxplus II because it has a much better and clearer timing analysis. Quartus is free to use and you can download it at: https://www.altera.com/support/software/download/altera_design/quartus_we/dnl-quartus_we.jsp Good luck. Chris "Shahab47" <sinamdar@mail.usf.edu> wrote in message news:<f86537e648db084b4cc35407ade2e141@localhost.talkaboutelectronicequipment.com>... > hi > > I am doing a research on comparing the different design methodologies for > vhdl with altera maxplus2 and xilinx ise webpack software. > > I am trying to find out the propagation delay ie maximum delay parameter > in the synthesis report from altera maxplus2 but couldnt find it?can any > body of u help me in this regard? in the maxplus2 there is one option > > assign > global project timing requirements.. > > here we need to enter the value of the propagation time.but i thought it > is some value which is decided after the design is synthesized and is > available in the synthesis report as in xilinx ise webpack...... > > some light on this topic will be of great help to me . > > thank you > > shahabArticle: 72112
Kelvin wrote: > I will try out SP3. Thanks for your reply. > > I guess, did you write all the ultra-long lines in the xilinx warnings and > fatal errors? I have wrote a few of them but I have read many more of them, perhaps too many of them, if I am starting to talk like that ;-) Actually, I have been rewriting many of our docs lately and I guess I am just in that mode of thinking. I do have a tendency to get a little more verbose like this in a wide audience situation as I find it can save me typing time to say a little more up front than to get several follow-up questions for being unclear about something. -- Brian > For example, this line, "The problem in Map effects the hierarchy > preservation of the design but does not effect the functionality or other > aspects so it would not cause any issues until hierarchy is attempted to be > reconstructed by the netgen program which can cause the type of errors that > you saw and disallow hierarchy reconstruction."... > > Best Regards, > Kelvin > > > > > > "Brian Philofsky" <brian.philofsky@no_xilinx_spam.com> wrote in message > news:4113A90E.4080506@no_xilinx_spam.com... > >> >> >>Kelvin, >> >> I just confirmed that this is the type of error that has been >>addressed by the patch and it was included as a part of Service Pack 3 >>so I believe this has been fixed. If you want to verify whether this >>problem does still exist for you, you should re-run the design through >>the software after installing service pack 3 starting at least the Map >>phase since the fix for this resides in that portion of the flow. The >>problem in Map effects the hierarchy preservation of the design but does >>not effect the functionality or other aspects so it would not cause any >>issues until hierarchy is attempted to be reconstructed by the netgen >>program which can cause the type of errors that you saw and disallow >>hierarchy reconstruction. >> >> If for some reason you still see this problem with Service Pack 3 >>or a newer version, just contact me or the Xilinx hotline and we would >>like to get to the bottom of the problem. >> >> >>-- Brian >> >> >> >> >> >>Kelvin wrote: >> >>>Anyway, maybe it is because I didn't upgrade my software. I am using > > 6.2.02i > >>>only. >>>The error is pasted below, though my partial implementation and assembly > > had > >>>no error. >>> >>> >>>Kelvin >>> >>> >>>C:\projects\bt11a_jul28\top_bt\assemble>netgen -sim -ofmt >>>verilog -w -ism -sdf_anno true -ngm top_sdr_map.ngm top_sdr.ncd >>>Release 6.2.02i - netgen G.30 >>>Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. >>> >>>Loading device database for application netgen from file "top_sdr.ncd". >>> "top_sdr" is an NCD, version 2.38, device xc2v6000, package bf957, >>>speed -6 >>>Loading device for application netgen from file '2v6000.nph' in > > environment > >>>C:/Xilinx6.2. >>>The STEPPING level for this design is 0. >>>ERROR:Anno - Cannot correlate logic element >>>'"Mmux__n0004_inst_mux_f6_0/MUXF6" >>> (tag=32161 in view "FRAGCOVERED")' is with this component > > 'bus_left(0)' - > >>> cannot continue hierarchical correlation) >>>ERROR:Anno - >>> - >>> - This application found errors in the Ngm and/or Ncd data files >>> - KEEP_HIERARCHY was corrupted and ignored (database will be > > flattened) > >>> - >> >><snip> >> > >Article: 72113
Hi I have a Spartan FPGA, which I would like to program in VHDL. The trouble is I can't find any software for it. I own the Xilinx WebPack and the Xilinx ISE 5.2i, both of which list the FPGA but they only allow EDIF designs (not VHDL). Does anyone know where I can get the software? Thanks.Article: 72114
> From: rickman <spamgoeshere4@yahoo.com> > > Yes, you can ignore and throw away the PPC. But you can't get the part > for the same price as not having the PPC. This argumentation is getting a bit weird. So we offer higher performance at a lower price ( in Virtex-IIPro), but rickman does not want to use them as a benchmark, because they wouldhave been even cheaper without the PPC and MGT. Yes, and even cheaper without all the multipliers, and without the BlockRAM and the DCM, not to mention all the 50 different I/O options. And half the routing is never used, and who needs LUT-RAM and SRL16s ? Where should we stop in stripping things out to make you happy ? Peter AlfkeArticle: 72115
Jonas, Excellent link. Many thanks, Syms. "Jonas Floden" <jontef@home.se> wrote in message news:411726E2.9070104@home.se... > This site has some very good tutorials which got my and my colleague > started with EDK. > > http://www.eece.unm.edu/xup/ >Article: 72116
Peter Alfke wrote: > > > From: rickman <spamgoeshere4@yahoo.com> > > > > Yes, you can ignore and throw away the PPC. But you can't get the part > > for the same price as not having the PPC. > > This argumentation is getting a bit weird. So we offer higher performance at > a lower price ( in Virtex-IIPro), but rickman does not want to use them as a > benchmark, because they wouldhave been even cheaper without the PPC and MGT. > > Yes, and even cheaper without all the multipliers, and without the BlockRAM > and the DCM, not to mention all the 50 different I/O options. And half the > routing is never used, and who needs LUT-RAM and SRL16s ? > Where should we stop in stripping things out to make you happy ? Scarcasm is always a nice way to discuss a topic. I checked web pricing and the V2Pro is a bit cheaper than the V2. The last time I had checked it was not. Regardless, V2 is not "quite old technology" and it is also not the V4 which is what Pete Fraser was proposing and I was disputing the availability for comparison. Austin said that "special" customers have been given the software to evaluate. So unless we get some of the "special" customers in this discussion, we will have to use the old Xilinx technology for our comparisons. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 72117
Sandhya wrote: > > Hi, > I have read that using a single always block(synchronous) for implementing > a state machine is not a good practice. > Can somebody tell me how does the synthesis tool handle this?? Did anyone tell you *why* a "single always block" is a bad thing for FSMs? Most of the time when someone makes a general rule like this, there is a reason for it that only applies under certain conditions. If you don't know the conditions, you might as well not use the rule. I expect you were told this because it is easier to control and optimize a FSM if the signal on the input to the FFs is a separate entity to which you can apply attributes. I have done FSMs both ways and it mainly depends on how complex your FSM is and how fast you need it to run. If you have a simple machine or it is not pressed for speed, a single always block is an ok way to code it and is simpler to write and read. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 72118
hello,
anyone here got experience with nallatech ?
We're considering getting a board from them but
so far can't get past an unresponsive sales
support...
lukasz
Article: 72119Shahab, I suggest using the Altera Quartus Web Edition which free and downloadable at the Altera website. Quartus has a better timing report feature than Maxplus II. Hope that helps. Chris "Shahab47" <sinamdar@mail.usf.edu> wrote in message news:<f86537e648db084b4cc35407ade2e141@localhost.talkaboutelectronicequipment.com>... > hi > > I am doing a research on comparing the different design methodologies for > vhdl with altera maxplus2 and xilinx ise webpack software. > > I am trying to find out the propagation delay ie maximum delay parameter > in the synthesis report from altera maxplus2 but couldnt find it?can any > body of u help me in this regard? in the maxplus2 there is one option > > assign > global project timing requirements.. > > here we need to enter the value of the propagation time.but i thought it > is some value which is decided after the design is synthesized and is > available in the synthesis report as in xilinx ise webpack...... > > some light on this topic will be of great help to me . > > thank you > > shahabArticle: 72120
While brushing up on the V2Pro, I saw in the data sheet where they actually define what a Logic Cell is, "Logic Cell = (1) 4-input LUT + (1)FF + Carry Logic". When I read this I thought maybe Xilinx has finally started printing facts in their data sheets about logic cell counts rather than marketing numbers. But no, somehow Xilinx still can't count and they are saying that 3,008 slices are equal to 6,768 logic cells. If Xilinx is going to define a logic cell, it makes sense to me that they should actually start counting them! -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 72121
A good article in the latest IEEE Spectrum. Probably a ways out, but I'll ask. Any work/thoughts on this technology applied to FPGA's? -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 72122
This debate is getting long in the tooth. Just take the number of slices and divide by two. In the meantime, Altera has jumped on this bandwagon and they multiply their ALE numbers by 1.25. As long a there is Marketing, there will be "creativity" with numbers. Just grin and bear it! Peter Alfke > From: rickman <spamgoeshere4@yahoo.com> > Reply-To: john@bluepal.net > Newsgroups: comp.arch.fpga > Date: Mon, 09 Aug 2004 13:46:36 -0400 > Subject: Now I am really confused! > > While brushing up on the V2Pro, I saw in the data sheet where they > actually define what a Logic Cell is, "Logic Cell = (1) 4-input LUT + > (1)FF + Carry Logic". When I read this I thought maybe Xilinx has > finally started printing facts in their data sheets about logic cell > counts rather than marketing numbers. But no, somehow Xilinx still > can't count and they are saying that 3,008 slices are equal to 6,768 > logic cells. > > If Xilinx is going to define a logic cell, it makes sense to me that > they should actually start counting them! > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 72123
"Steven K. Knapp" <steve.knappNO#SPAM@xilinx.com> wrote in message news:<cf6enk$hvs1@cliff.xsj.xilinx.com>... > "Lawrence D. Lopez" <lopez-NOSPAM@mv.mv.com> wrote in message > news:41126496.4020808@mv.mv.com... > > There are various reference designs for the Spartan-3 Starter Kit Board > available at the following link. > http://www.xilinx.com/products/spartan3/s3boards.htm#RF > I followed the instructions for the MicroBlaze reference design carefully. All steps proceeded without errors, but the download produced an inert board. Anybody have better luck with this design? -DaveArticle: 72124
I haven't used either of these but they're the only ones I've come across so far:
http://www.nallatech.com/solutions/products/kits/pci-express_design/
http://www.nital.com/corporate/pciexbuilder-e254.html
Mark
Geoffrey Wall wrote:
> Does anyone know if there exists an FPGA development board that has
> a PCI express interface? I would also be nice if it had video i/o on board
> I need to do real time quick image processing, and eventually face detection
> algorithms...
> thanks
>
>
> Geoffrey Wall
> Masters Student in Electrical/Computer Engineering
> Florida State University, FAMU/FSU College of Engineering
> wallge@eng.fsu.edu
> Cell Phone:
> 850.339.4157
>
> ECE Machine Intelligence Lab
> http://www.eng.fsu.edu/mil
> MIL Office Phone:
> 850.410.6145
>
> Center for Applied Vision and Imaging Science (will be updated soon)
> http://cavis.fsu.edu/
> CAVIS Office Phone:
> 850.645.2257
>
>
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