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The deux chevaux were really a measure of taxation, had little to do with engineering horsepower (which has little to do with the performance of a horse). The Brits used a similar strange taxation measurement. Peter Alfke > >> Our stuff still has a way to go before it catches up with the >> real smoke and mirror artists. Did the Citroen 2CV ever have >> a two horsepower engine, even when first introduced - whenever >> that was? Actually I don't understand that one... it's as if >> X advertised "Virtex-4: more than one LUT" >> >> > Anybody old enough to remember Radio Shack's spec on the stereo amps? 150 > WATTS to > us means out put power to speakers. From Radio Shacks spec it was input > power on the AC side. > >Article: 72176
Lukasz Salwinski wrote: > hello, > anyone here got experience with nallatech ? > We're considering getting a board from them but > so far can't get past an unresponsive sales > support... > > lukasz just answering my own question - Nallatech marketing woke up after all (some problems with their email system, i was told). and they actually turned out to be pretty helpful ;o) lukaszArticle: 72177
Assuming you mean the old 5V Spartan, or the 3.3V SpartanXL, the P&R tools are freely downloadable from ISE classics page here http://www.xilinx.com/webpack/classics/spartan_4k/index.htm However you will need to use a 3rd party synthesis tool like Leonardo or Synplify. --Neeraj "Kev" <Kev@key.com> wrote in message news:cf88ns$jt6$1@newsg3.svr.pol.co.uk... > Hi > > I have a Spartan FPGA, which I would like to program in VHDL. The trouble > is I can't find any software for it. I own the Xilinx WebPack and the > Xilinx ISE 5.2i, both of which list the FPGA but they only allow EDIF > designs (not VHDL). > > Does anyone know where I can get the software? > > Thanks. > >Article: 72178
Vaughn, Peter, Others How much faster are the 90nm parts over the 130nm parts? I saw someone on this forum say that you can achieve almost 2x performance. Is this because of the move from 130 to 90 or is it because of the new architectures of Stratix-II and Spartan-3 etc ? Is the new architecture a product of the fact that you can fit more logic at 90nm than was possible at 130nm ? Thanks SumitArticle: 72179
Paul Are your 90nm parts 2x better performance because of going to 90nm process or because of the new/better architecture ? Thanks SumitArticle: 72180
"lecroy" <lecroy7200@chek.com> wrote in message news:9297c711.0408100454.3612bf68@posting.google.com... [snip] > "If we look at the incident versus reflected energy and tune the stub > (trace) for a worst case match is it possible the driver could be > damaged or the chip lock up due to the reflected energy?" > > "The circuit would be as follows: > Spartan III Output ------------------------------ Tunable Stub" > > I wonder if anyone in this group has asked this question and what was > the responce from Xilinx? [snip] > I just got this information that may be of interest to some of you. > > Apparently the problem with past parts was that the I/O was really > 2.5V so when boosting up to 3.3 already took away most of the > overshoot window. This new revision should correct this. I believe > this is preliminary info, but yes this is meant to resolve the reflected > signal issue. Apparently this issue is also in other parts, I believe the > Virtex II. Sorry I missed this one the first time around. Some of the confusion might be due to initial early Spartan-3 FPGA engineering samples that did not officially support 3.3V I/O. The Spartan-3 FPGAs available today do support 3.3V I/O. Xilinx recommends limiting overshoot/undershoot to less than 500 mV so as not to turn on the I/O protection diodes. Consequently, the recommended voltage at the I/O pad should never be lower than 0.5V or more than VCCO+0.5V. In all the HyperLynx IBIS board simulations that I've done, I've never seen a case where the output created a voltage that it could not tolerate. Certainly, the destinations may see a higher voltage depending on I/O drive strength and trace length. Consequently, you may need to terminate the signal for the voltage on the receiving end. That said, there may be some sort of pathological case that I have not seen in practical designs. --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/II/IIE FPGAs http://www.xilinx.com/spartan3 --------------------------------- Spartan-3: Make it Your ASICArticle: 72181
I just spent a little time googling, doing and debugging this. Thought I'd
try and save anyone else the bother by posting this as a starting point.
'pos' is the number to display.
'servo_count' just counts.
Cheers, Syms.
Entity extract followed by VHDL process followed by UCF extract
use ieee.numeric_std.all;
entity top is
port (
clock : in std_logic; --system clock
res_n : in std_logic; --system clock
DIGIT_ANODE : out std_logic_vector(3 downto
--system clock
SEGMENT : out std_logic_vector(7 downto
--system clock
);
end top;
led_driver : process(res_n, clock)
begin
if res_n = '0' then
digit <= 0;
input <= 0;
SEGMENT <= (others => '0');
DIGIT_ANODE <= (others => '0');
elsif rising_edge(clock) then
if servo_count mod 256 = 0 then
digit <= (servo_count / 256) mod 4;
case digit is
when 0 =>
DIGIT_ANODE <= "0111";
input <= pos mod 16;
when 1 =>
DIGIT_ANODE <= "1110";
input <= (pos / 16) mod 16;
when 2 =>
DIGIT_ANODE <= "1101";
input <= (pos / 256) mod 16;
when 3 =>
DIGIT_ANODE <= "1011";
input <= (pos / 4096) mod 16;
when others => null;
end case;
case input is
when 0 => SEGMENT <= "00000011"; -- "a b c d e f g DP"
when 1 => SEGMENT <= "10011111";
when 2 => SEGMENT <= "00100101"; -- --a--
when 3 => SEGMENT <= "00001101"; -- | |
when 4 => SEGMENT <= "10011001"; -- f b
when 5 => SEGMENT <= "01001001"; -- | |
when 6 => SEGMENT <= "01000001"; -- |--g--|
when 7 => SEGMENT <= "00011111"; -- | |
when 8 => SEGMENT <= "00000001"; -- e c
when 9 => SEGMENT <= "00011001"; -- | |
when 10 => SEGMENT <= "00010001"; -- --d--DP
when 11 => SEGMENT <= "11000001";
when 12 => SEGMENT <= "01100011";
when 13 => SEGMENT <= "10000101";
when 14 => SEGMENT <= "01100001";
when 15 => SEGMENT <= "01110001";
when others => SEGMENT <= "11111111";
end case;
end if;
end if;
end process;
#
# 7-segement display
#
NET "digit_anode(0)" LOC = "D14";
NET "digit_anode(1)" LOC = "G14";
NET "digit_anode(2)" LOC = "F14";
NET "digit_anode(3)" LOC = "E13";
NET "segment(7)" LOC = "E14";
NET "segment(6)" LOC = "G13";
NET "segment(5)" LOC = "N15";
NET "segment(4)" LOC = "P15";
NET "segment(3)" LOC = "R16";
NET "segment(2)" LOC = "F13";
NET "segment(1)" LOC = "N16";
NET "segment(0)" LOC = "P16";
Article: 72182Does anyone know where I can find an objective, third-party example of a network router and it's related "typical" specifications (in particular, the # of LUTs used for each function)? Ideally I would like to find a high-performance, multi-function router and an objective view that summarizes the following attributes/specifications (and potentially more if possible): ---------------- TBD ROUTER -------------------- MODULE LUTS SPEED THROUGHPUT OTHER? xxx xxx Many thanks! JennArticle: 72183
Hi all,
I am confused with the "Clock to Setup on destination clock " section of the
report. I am using differential clocks and the data doesn't seem right. Here
is an example:
Clock to Setup on destination clock clk_dco_N
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk_dco_N | 5.280| | | |
clk_dco_P | 5.294| | | |
---------------+---------+---------+---------+---------+
This seems to contradict to the achieved 4.7 ns clock period on the internal
clk_dco if I only understand correctly what this spec means... According to
the Xilinx Answer Database this means the Q of a flip-flop that is running
on one of the "source" clocks will reach the D of a flip-flop that is
running on the "destination" clock (in this case clk_dco_N) in no more than
"X"ns. Does this make sense at all for differential clocks?
/Mikhail
Article: 72184"Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message news:<10hgkcgas2ais1f@corp.supernews.com>... > So you have a pretty good design and you want to save it, start another my base design for 1000 series chips works, added a freecore and it works now ported to Spartan - base design works but adding the freecore causes base design not to work (not to mention freecore) looked at timing constraints no problems. ????Article: 72185
Jim Granville wrote: > Eirik Seljelid wrote: > >> mmock wrote: >> >>>> Eirik Seljelid wrote: >>>> >>>>> considered the PA7536, but I find it way easyer to get an older >>>>> version of ABEL, compile the code for 82S100 and burn the chips. >>>> >>>> >>>> >>> Eirik, >>> >>> Have you located it? I'm not familiar with the 82S100. I have an >>> ancient version of ABEL, circa 1988. Is that too ancient? >>> >>> Mike >> >> >> >> Not sure. I've found Abel 2.0 and Abel 4.0 on the net and tried to >> compile the source, but in both versions I got the message "fatal >> error: out of memory". It worked when I tried to compile only parts of >> the source. > > > Some (most?) ABEL's needed keys, this may be a security artifact ? > It is hard to believe the 82S100, which my info shows has just 1928 > fuses (smaller than a 16V8), would tax memory ? > CUPL probably also supported the 82S100. > -jg > Could be, but I suppose it would come up with an error message asking for valid keys or something like that. When I cutted down the source it would compile. I haven't really set up an old dos environment yet so I think I will try this as soon as I get the time to do it. AFAIK CUPL is a different HDL than Abel, which means I have to rewrite the source to CUPL syntax. My HDL programming experience is somewhat limited. I've written some PLD-cicuits in PALASM and another GAL-assembler called GALASM. Very basic, no high-level coding. Although I probably understand most of the code I'm really not so keen on translating it. The equipment using the FPLA also incorporates a serious amout of other PLD devices, mostly 22V10's and EP600's, all documented with Abel source code. EirikArticle: 72186
"Captain Bly" <Bobcrap@aol.com> wrote in message news:yT3Sc.53161$zc4.22664573@news4.srv.hcvlny.cv.net... > I got a tee shirt, I could only assume it's someone that works for Altera > > "Jerry" <nospam@nowhere.com> wrote in message > news:10hg4i8oulqp5af@corp.supernews.com... > > Does anyone know who won the camera from Altera on that Cyclone 2 web > > presentation? WOW, you got the tee-shirt? I didn't even get to register to win the camera after sitting through an hour of rehashed info then listening to questions that were answered by the marketerr. Yes I did complain to Altera about it but it hasn't done me any good. The big question is will this incident affect my decision to go Altera or Xilinx on the next design? No it won't. So only one person on this newsgroup got a tee-shirt? I thought the first 300 were going to receive one. ARRRRRGGGGG oh wait.................... If you are saying ARRRRRRGGGGG a lot lately you may be designing with Altera.Article: 72187
Eirik Seljelid wrote: <snip> > Could be, but I suppose it would come up with an error message asking > for valid keys or something like that. When I cutted down the source it > would compile. > I haven't really set up an old dos environment yet so I > think I will try this as soon as I get the time to do it. Sounds close - at this point I would try something trivial like 8 NAND gates in a test file ( uses every pin ), and confirm you get what looks like a valid JED file. > AFAIK CUPL is a different HDL than Abel, which means I have to rewrite the source to > CUPL syntax. My HDL programming experience is somewhat limited. I've > written some PLD-cicuits in PALASM and another GAL-assembler called > GALASM. Very basic, no high-level coding. Although I probably understand > most of the code I'm really not so keen on translating it. The equipment > using the FPLA also incorporates a serious amout of other PLD devices, > mostly 22V10's and EP600's, all documented with Abel source code. CUPL was suggested, should you hit a brick wall with ABEL, right now it sounds more like a speed-bump..... :) -jgArticle: 72188
Jenn Lee wrote:
> Does anyone know where I can find an objective, third-party example of
> a network router and it's related "typical" specifications (in
> particular, the # of LUTs used for each function)? Ideally I would
> like to find a high-performance, multi-function router and an
> objective view that summarizes the following attributes/specifications
> (and potentially more if possible):
>
> ---------------- TBD ROUTER --------------------
> MODULE LUTS SPEED THROUGHPUT OTHER?
> xxx
> xxx
Howdy Jenn,
I would be very surprised if you could find something like this, for
at least two big reasons:
1. Each high performance product, in my experience, has a unique set of
requirements - take for example your term "multi-function". What does
that really mean? How many ports do you want it to have? What speed
are they? How much blocking is allowed? How badly do you want to avoid
discards? How much can it cost? Can you share ingress/egress buffers
per port? Internal or external memory? The list is near endless.
2. Companies who design and develop such devices have no motivation or
desire to share their knowledge or ideas with their competitors.
Have fun,
Marc
Article: 72189Hi Sumit, > How much faster are the 90nm parts over the 130nm parts? I saw > someone on this forum say that you can achieve almost 2x performance. > Is this because of the move from 130 to 90 or is it because of the new > architectures of Stratix-II and Spartan-3 etc ? Is the new > architecture a product of the fact that you can fit more logic at 90nm > than was possible at 130nm ? Stratix II (90 nm) offers a 50% average performance improvement over Stratix (130 nm). In addition, some critical blocks (DSPs, memories, I/Os) were sped up significantly. This is a combination of architecture, process technology, and elbow grease in the electrical design. The main architectural enhancement is the Adaptive Logic Module (ALM) which replaces the Logic Element of Stratix. There are some additional tweaks, but I frankly can't recall which ones are user visible. And good electrical design can always help -- since some features from Stratix II were an evolution from Stratix, designers could spend more time tweaking the design rather than concentrating strictly on functional correctness. As far as process goes, it used to be that moving from one process to a smaller one would give automatic speed ups and a smaller die size to boot. The trade-offs are more complex these days. The die size savings are still there, but the speed-up is not automatic. In smaller processes, we thin the gate oxide to improve transistor speed (~linear with gate oxide thickness). But we must then shrink the core voltage (Vcc) to reduce Vgs otherwise the oxide breaks down (reliability issue); the thinner oxide also causes increased gate leakage, which is mitigated some by reduced Vgs. Reducing Vcc also reduces dynamic power (quadratically). As we scale down Vcc we need to scale down the threshold voltage (Vt) otherwise the transistor gets too slow (Ids = k(W/L)(Vgs - Vt)^2). But the lower the threshold, the less "off" the transistor is when Vgs=0V. And of course the gate length (main process feature) is shrinking, which (linearly) increases transistor speed but greatly increases sub-threshold leakage. So we have to pick-and-chose when to apply fast but leaky transistors and when to stick with low-power but slow transistors (with longer gate lengths, higher threshold voltages, thicker gate oxides, etc.). There are many other tricks that can be employed on the speed/power front, some of which cost area or increase manufacturing costs, and all make our job designing the FPGA that much more fun :-) [Disclaimer: It's 11 o'clock; hopefully I didn't garble that description!] One other process change was the move to low-k inter-metal dielectric. This reduces the capacitance of metal routes, in exchange for some additional manufacturing & materials challenges. Low-K took a while for the semiconductor industry to get right, but it's now mature enough that we feel we can produce low-k chips with no yield impact. We've been playing with low-k for a while but decided not to roll it out in our products until Stratix II. The architectural changes are somewhat independent of process, though there is always some tweaking possible, for example as the ratio of logic vs. routing delays change over process. Also, as power becomes more important, many architectural choices will need to be revisted to find the right speed/area/power/complexity trade-off. For example, the ALM offers better power than the equivalent circuit in LEs since more logic is captured into locally (vs. programmably) routed circuitry; this is more important at 90 nm where power is becoming a bigger factor. So while there is some connection to process, most architectural improvements are just the result of us having had another two years to think! Regards, Paul Leventis Altera Corp.Article: 72190
On Fri, 06 Aug 2004 10:05:26 -0700, Symon wrote: > Derek, > Hmmm, what input power do you have? Are you any good at PCB layout? How many > are you making? Why are you using Virtex-E? Have you ever been in a Turkish > prison? > Whatever, my current (ha ha) favourites are LT parts. I've got a good FAE! > LTC3728 is a dual controller can take up to 24V in and make 5V and 3.3V. I > use LTC3414s to make core voltages from these supplies. LT do demo boards > for both parts. Be environmentally friendly, ditch the evil linear > regulators, use switchers! Especially as you can get 6.3V 100uF X5R ceramic > in a 1210 package these days. And check out Panasonic's specialty polymer > electrolytics. Bloody marvellous, 5 milliohm ESR. > Cheers, Syms. > Both TI and National (maybe Intersil too, I forget) have a bunch of material geared to helping design power subsystems for xilinx FPGA parts. IMHO, LTC has nice stuff and good apps people, but the parts are just too expensive. Check out the Fairchild FAN5286 - dual switcher controller with wide input range, DDR Vtt support and its something like $1.50 on their web site. We got a fair bit better than that with a real quote through distribution. There's even an Intersil part that's close to a drop in replacement (pinout is the same, I haven't recalculated the L's, R's and C's). The only thing I don't like about it is it requires a +5V rail, it doesn't have the internal regulator like some others.Article: 72191
I' m a beginner in the FPGA world so i went to Xilinx and Altera site to download the free design software for learning the basics. I have saw that all the software downloadable is for windows. Am i wrong or is really so? If so for me is very strange or wrong. Because for a design kit that is freely distributed what platform is better than a free Operating System? Without entering in the discussion of the better quality of Linux. I hope i'm wrong and that someone tell me that i can download these software for my gentoo Linux distribution. Thanks to all.Article: 72192
Hi all. I have a project for the XilinxPlatformStudio 6.1.0.3i with a PPC in it. I generated the simulation model (structural) but the PPC component (called PPC_405) is not in the Xilinx related library (UNISIM) included with the "library" statement in its wrapper, so I can not simulate that project. I generated with the compedklib and cmpxlib the library with the simulation models for the fpga architecture that I have to use but it did not work. Does anyone there have suggestions? Thanks in advance, AndreaArticle: 72193
Hi, I'am using Virtex II chips. In my design I have multiple multipliers, for what I want use Hardware Multipliers. For Synthese use I Precision from Mentor. To force using Hardware Multipliers I use attribute DEDICATED_MULT = ON. When I Synthesis only my Sub Module I get result what I want. When I Synthesis design where my Sub module is instanced are my Hardware Multipliers gone and replaced with logic. Can anyone comment? Cheers, TPalmArticle: 72194
I use Xilinx Foundation 2.1i build 3.1,162 and I use HDL Editor build 0.42 and if I want to create macro from file (Project->Create Macro) I must specify FLEXim license? What is this that license? Anybody knows how solvethis problem? THX KubaArticle: 72195
Sumit <gupt@hotmail.com.NOSPAM> wrote in message news:<m33c2wsz9c.fsf@agni.ics.uci.edu>... > Hi > > How much of a consideration is the quality of design tools while > choosing the FPGA vendor/device for a design? I guess this comes down > to - are most of the tools out there almost of similar quality in > terms of leading to designs with similar performance, area (FPGA > usage), etc ? I know a lot of folks are partial to Xilinx and > Altera, but I am trying to consider others as well, and want to know > how carefully I have to look at tool offerings to evaluate all of > them. > > Thanks > Sumit If you try different tools you will have different results. The built-in synthesis tools in Altera and Xilinx will probably not generate as good results as Synplify for example. However third party tools are always more epensive. If you are expecting high production volumes or if you beleive it will be difficult to meet timing/area constraints you should go for Synplify or Mentor otherwise I suggest you start with the builtin ones.Article: 72196
I tried to do it, but it didn't work. David John Williams <jwilliams@itee.uq.edu.au> wrote in message news:<cf8u9c$4uo$1@bunyip.cc.uq.edu.au>... > Hi Andrew, > > Andrew Rogers wrote: > > Does anyone have impact running under wine? > > > > Can I configure my Spartan3 Starter Kit from GNU/Linux? If so, how? > > > > I have tried to run impact under wine but it fails to connect even as > > root. Perhaps this is due to some wrong configuration in my wine.conf. > > I'd be very surprised if you could run impact under Wine - it needs > direct hardware access to the parallel port. > > If you are using normal Xilinx ISE tools they can be installed native > under Linux - Impact works fine. > > Regards, > > JohnArticle: 72197
Austin "Sooooo much current" Lesea wrote: > >But really, I was offended by the silly response, talking about >applications that have 'no power' where DCI is all of the power. > Pointing out the 200mW per bank DCI overhead wasn't inane before, and it's not silly now. "Small Spartan3 design" means a design that fits in a small Spartan3, not a trivial design intended to confound Austin's Nostradamus-like powers of engineering prediction. Consulting WebPower 2.2.0, a 3S50 chock full of 50 MHz toggling flops and BRAMs with 'high' routing had an estimated total power of only 132 mW. Also from WebPower, quiescent power for a configured FPGA in the smaller S3 family members is as follows: 3S50 : 14 mW 3S200 : 40 mW 3S400 : 67 mW 3S1000 : 99 mW Compare those numbers to 200 mW for just one bank of DCI. ( And it's rather difficult to keep all DCI in one bank in, say, a VQ100 or TQ144 with only 6-15 I/O per bank. ) This DCI power hit is yet another reason the _DT differential terminators would have been useful in the S3 family. In the absence of a VRP/VRN shutdown mechanism, disconnecting the VRP/VRN resistors with a timed external analog switch after configuration may work, depends upon whether the bank control logic would be upset with the vanishing resistors in the DCIUpdateMode=Quiet mode. Earlier on in the thread, Austin wrote: > >I would appreciate it if you did detail every single omission, >distortion, or mis-representation. > Summary of errors and omissions in Austin's other post: (detailed version appended below) > >Freeze DCI has nothing to do with it. > Wrong. Using FreezeDCI in the V2 affects both the behavior and repeatability (config-config & part-part) of static DCI power consumption, both for per-bank overhead, and particularly for per-input parallel terminators. > >From the first appearance of DCI in Virtex II, it has been a > solid feature in every device since. > ROTFL'ingly wrong. If it's so bloody solid, why is Xilinx STILL patching BITGEN for Virtex2 ??? > >DCI updating is only an issue when you cross between two banks, >and even then only with the parallel interfaces where it adds >some small amount of jitter. > Wrong, incomplete, and misleading. > > Freezing the updates allowed customers who did not read that > they should not go across banks > Read where? In the two Answer Records that mention the bank-bank DC offset ? And then only if their psychic powers prompted them to search the Answer Records for an obscure invented term like "FreezeDCI" before starting a design? Brian Detailed version: ( My references to documentation omissions are based on my last thorough search in Fall 2003; if Xilinx has updated any DCI related documents since then, feel free to point them out ) > >Freeze DCI has nothing to do with it. > Wrong. Using FreezeDCI in the V2 affects both the behavior and repeatability (config-config & part-part) of static DCI power consumption, both for per-bank overhead, and particularly for per-input parallel terminators power. FreezeDCI waits long enough after configuration for each bank to have adjusted, then asynchronously halts the DCI bank logic in the midst of whatever it was doing. As each bank has its' own independent CCLK type oscillator driving the tap adjustments, you end up with a random sampling of the possible DCI adjustment states for each bank. Worst case for the per-bank overhead is when the bank adjust randomly stops at the R/2 setting, which burns the most power in the VRP/VRN circuit. Worst case for the per-input parallel terminators is when a bank update stops during the active adjustment state for the parallel termination standard in use, during a 20% low adjustment excursion of the impedance tap setting (20% for 2R, 10% for R). As the V2 control logic drags all the terminators in the bank along with it during its' bump up/bump down adjustment tests, this means that all the parallel input terminators in that bank are now 20% low, and burning 20% more power than usual. Each configuration rolls the dice for each DCI bank, and sometimes more than one will come up on the worst case setting... As I understood it, the newer devices having DCIUpdateMode were going to cleanly stop the DCI updates in all banks at a known state rather than randomly halting them as with FreezeDCI. > >From the first appearance of DCI in Virtex II, it has been a >solid feature in every device since. > ROTFL'ingly wrong. If it's so bloody solid, why is Xilinx STILL patching BITGEN for Virtex2 ??? When is Xilinx going to publish a detailed description of the DCI modulation problems, other than the passing mention in the "AM modulation" Answer Record #13012 ? ( News Flash: on August 5 2004, #13012 was updated with a brief description of the cause of the DCI modulation problem, along with two LVDS_25_DCI scope plots that look amazingly similar to the ones I sent to Xilinx way back in ~Dec 2002 ) Where is the characterization data bounding the worst case magnitude of the DCI impedance modulation for each standard ? Has the peak magnitude of this impedance modulation been reduced in the V2Pro and S3 families when DCIUpdateMode=Continuous|AsNeeded ? Where is the worst case power consumption data for V2 DCI when FreezeDCI (now automagically enabled in BITGEN 6.x) is turned on ? Where is the complete list of FreezeDCI side effects ? > >DCI updating is only an issue when you cross between two banks, >and even then only with the parallel interfaces where it adds >some small amount of jitter. > Wrong, incomplete, and misleading. AFAIK, with FreezeDCI off, the DCI control logic continuously modulates the bank impedance for both series and parallel DCI termination, be they in one or several banks, although it's certainly easier to spot for the parallel terminators because of the readily visible modulation of the DC offset voltage. It's important to note that the behavior of a random, asynchronous, high rate impedance modulation is completely different than that of a static impedance mismatch. I'd hesitate to use the series terminated DCI for anything but low rate data lines with the DCI modulation present: an asynchronous series DCI impedance change coincident with an outgoing edge on a series terminated clock/strobe line could create a non-monotonic edge as well as a timing push-out. On the other hand, with FreezeDCI on, the resulting random DC offset for the parallel terminators will probably cause problems for the single ended standards with accurate terminator VTT requirements (whether in one or multiple banks). Does the 'clean halt' of the newer parts' DCIupdateMode=Quiet setting reduce the magnitude of the bank-bank DC offsets? > > Freezing the updates allowed customers who did not read that > they should not go across banks > Read where? In the two Answer Records that mention the bank-bank DC offset ? And then only if their pyschic powers prompted them to search the Answer Records for an obscure invented term like "FreezeDCI" before starting a design? The only hint of DCI problems in the latest V2 user manual (UG002 v1.7) is this gem of understatement from page 201: "If users do not want to have the second phase enabled, they should use the FreezeDCI option in BitGen"Article: 72198
Andrea Sabatini wrote: > Hi all. > > I have a project for the XilinxPlatformStudio 6.1.0.3i with a PPC in it. I > generated the simulation model (structural) but the PPC component (called > PPC_405) is not in the Xilinx related library (UNISIM) included with the > "library" statement in its wrapper, so I can not simulate that project. > > I generated with the compedklib and cmpxlib the library with the simulation > models for the fpga architecture that I have to use but it did not work. > > Does anyone there have suggestions? > > Thanks in advance, > > Andrea > > Dear, Simulation of V2PRO hardware components (PPC405, ROCKETIO) need installation of Swift Models. See Xilinx answer records to know supported simulators and how to install and use this models with your simulator. For modelsim http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=14019 Hopping that helps you !! GillesArticle: 72199
Derek, I am currently developing dual-voltage POL specifically to power FPGA's. Reduce your time to market and use an off-the-shelf, highly-efficient, pre-engineered power supply. It is very configurable but as a maximum can supply 2 different rails of 3A each as well as a third rail of 250mA. As a bonus a Xilinx platform flash is optionally included if you want. I am targeting Spartan-3 device initially but there is no reason why it won't work with any FPGA or DSP. Email me if you want more specific information. There will be info shortly at http://www.stratforddigital.ca/. Cheers, James. On Wed, 11 Aug 2004 04:30:27 GMT, Andrew Dyer <andrew.spam.dyer@comcast.net> wrote: > On Fri, 06 Aug 2004 10:05:26 -0700, Symon wrote: > >> Derek, >> Hmmm, what input power do you have? Are you any good at PCB layout? How >> many >> are you making? Why are you using Virtex-E? Have you ever been in a >> Turkish >> prison? >> Whatever, my current (ha ha) favourites are LT parts. I've got a good >> FAE! >> LTC3728 is a dual controller can take up to 24V in and make 5V and >> 3.3V. I >> use LTC3414s to make core voltages from these supplies. LT do demo >> boards >> for both parts. Be environmentally friendly, ditch the evil linear >> regulators, use switchers! Especially as you can get 6.3V 100uF X5R >> ceramic >> in a 1210 package these days. And check out Panasonic's specialty >> polymer >> electrolytics. Bloody marvellous, 5 milliohm ESR. >> Cheers, Syms. >> > > Both TI and National (maybe Intersil too, I forget) have a bunch > of material geared to helping design power subsystems for xilinx > FPGA parts. > > IMHO, LTC has nice stuff and good apps people, but the parts are > just too expensive. > > Check out the Fairchild FAN5286 - dual switcher controller with > wide input range, DDR Vtt support and its something like $1.50 on > their web site. We got a fair bit better than that with a real quote > through distribution. There's even an Intersil part that's close to > a drop in replacement (pinout is the same, I haven't recalculated the > L's, R's and C's). > > The only thing I don't like about it is it requires a +5V > rail, it doesn't have the internal regulator like some others. > -- Using M2, Opera's revolutionary e-mail client: http://www.opera.com/m2/
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