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Messages from 72225

Article: 72225
Subject: Re: why?
From: John Williams <jwilliams@itee.uq.edu.au>
Date: Thu, 12 Aug 2004 07:59:11 +1000
Links: << >>  << T >>  << A >>
kubik wrote:
> I' m a beginner in the FPGA world so i went to Xilinx and Altera site to
> download the free design software for learning the basics. 
> I have saw that all the software downloadable is for windows.
> Am i wrong or is really so?

I don't know about the Altera tools, but my understanding is that Xilinx 
webpack is not available for linux because they would have to pay 
per-seat licensing to the developer of the cross-platform GUI that they 
use.  For giveaway software this clearly does not make sense.

I'm pretty sure people have got the free Xilinx tools (webpack) going 
under wine - google will tell you.  The only hitch there is the iMPACT 
programming tool - I doubt it will work.

Cheers,

John

Article: 72226
Subject: Request for 28 BIT ADDER maximum clock rates for Vertex II FPGAs
From: billh40@aol.com (Bill Hanna)
Date: 11 Aug 2004 15:14:14 -0700
Links: << >>  << T >>  << A >>
Has anyone tested 28 BIT ADDERS in Vertex II for maximum clock rate
thru the ripple carry chain?  I have an application That requires a
maximum clock frequency of 80 MHz.

Thanks,
Bill

Article: 72227
Subject: Re: Request for 28 BIT ADDER maximum clock rates for Virtex II FPGAs
From: "John_H" <johnhandwork@mail.com>
Date: Wed, 11 Aug 2004 22:26:53 GMT
Links: << >>  << T >>  << A >>
80 MHz is extremely slow and easily achieved in any FPGA introduced in the
last several years.  I would expect that 200 MHz is easy in the slowest
speed grade of Virtex-II but I haven't bothered to run the numbers.


"Bill Hanna" <billh40@aol.com> wrote in message
news:97d137ce.0408111414.1d4f1011@posting.google.com...
> Has anyone tested 28 BIT ADDERS in Vertex II for maximum clock rate
> thru the ripple carry chain?  I have an application That requires a
> maximum clock frequency of 80 MHz.
>
> Thanks,
> Bill



Article: 72228
Subject: Re: new XILINX 9500XL datasheets
From: Mark Ng <mark.ng@xilinx.com>
Date: Wed, 11 Aug 2004 15:48:51 -0700
Links: << >>  << T >>  << A >>
Hi Mike,

Your distributor is wrong in telling you that these 9500XL are not 
recommended for new designs.  It is perfectly fine to start a new design 
with 9500XL.

Xilinx has absolutely no intention of discontinuing the 9500XL devices. 
  We are still seeing continued interest in new product designs.

As for your technical question below --  Table 3 in the datasheet is 
incorrect.  If read and write protect are both set, then a read will be 
inhibited, and a program/erase attempt will prompt a Warning in the 
iMPACT programming software.  You can still erase/program the part.  In 
summary, this means you can still erase/reprogram the part even though 
write protect is set.

We'll fix the datasheet asap...

Thanks!
Mark



M.Randelzhofer wrote:
> hello ng,
> 
> there are new versions of the 9500xl cpld devices on the xilinx server.
> 
> See:
> http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=-18744&iLanguageID=1
> 
> My distri told me, these products are not recommended for new designs, but
> they still are PRELIMINARY !??
> 
> 
> The question about the write inhibit bit is also curious. In ds054
> 
> http://direct.xilinx.com/bvdocs/publications/ds054.pdf
> 
> on page 14 table 3 shows a state, where the cpld cannot be reprogrammed nor
> erased.
> 
> Answer database no 4288 states the opposite:
> 
> http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=4288
> 
> Maybe some stimulations for the next datasheet revisions...
> 
> 
> MIKE
> 
> 
> 

Article: 72229
Subject: Re: Primitve 3D Graphics Library
From: John Williams <jwilliams@itee.uq.edu.au>
Date: Thu, 12 Aug 2004 09:05:41 +1000
Links: << >>  << T >>  << A >>
Derek Simmons wrote:

> I'm looking for something that supports triangles (or some other
> primitives) with materials and light sources (would be nice). Or am I
> wishing for too much?

It's done in Handel-C, not VHDL/Verilog, but the Celoxica folks have a 
very pretty real-time 3D rendered demo that they take around to the 
various FPGA / reconfigurable computing conferences.  Texture maps, 
lighting, bump mapping and all that sort of thing.

Might be worth getting in touch with them to find out more.  Perhaps if 
you get a Handel-C license and/or a Celoxica board they would be willing 
to share...

Cheers,

John

Article: 72230
Subject: Re: ISE 6.2 : Place problem with V2PRO
From: "Antti Lukats" <antti@case2000.com>
Date: Wed, 11 Aug 2004 16:06:45 -0700
Links: << >>  << T >>  << A >>
"gilles" <georges@irisa.fr> wrote in message
news:cfd78b$cj2$3@amma.irisa.fr...
> Dear,
>
> I have a V2PRO design using PPC405 and several peripheral including
> plb_ddr. When i try to implement my top_level deign i got the following
> error during PAR :
>
> Phase 8.24
> ERROR:Place:17 - The current designer locked placement of the IOBs
> IMM_MASK<0> and DIMM_STROBE<0> makes this design unroutable due to a
> physical routing limitation. This device has a shared routing resource
> connecting the ICLK and OTCLK pins on pairs of IOBs.  This restriction
> means that these pairs of pins must be driven by the same signal or one
> of the signals will be unroutable. Before continuing with this design
> please unlock or move one of these IOBS to a new location.

you can constrain one single prim to be excluded from placement into IO pad,
just specify that for one of the problematic pins in your .UCF file.
That isnt so nice solution but it makes the design to finish build with no
errors.

Antti
http://xilinx.openchip.org



Article: 72231
Subject: get net name after place and route, ISE
From: Matthew E Rosenthal <mer2@andrew.cmu.edu>
Date: Wed, 11 Aug 2004 20:04:26 -0400 (EDT)
Links: << >>  << T >>  << A >>
Hi all,
I am using ISE 6.2 and after place and route static timing analysis I see 
a net in my critical path that looks like it doesn't belong.
All i have for the net name is a bit of hiearchy and a N21408.
Is there a way to map back from this N21408 to see where this is generated 
in the hdl code?

thanks

Matt

Article: 72232
Subject: Re: scheduling in run-time reconfiguration
From: supradeep@gmail.com (supradeep narayana)
Date: 11 Aug 2004 17:13:44 -0700
Links: << >>  << T >>  << A >>
refer to "on scheduling dynamic FPGA reconfigurations" proceedings of
the fifth australian conference on parallel and real-time systems,
1998.


Philip Freidin <philip@fliptronics.com> wrote in message news:<kgokh0lm8mck811ih4c4v827n9nsmvm8vf@4ax.com>...
> On 11 Aug 2004 10:32:54 -0700, supradeep@gmail.com (supradeep narayana) wrote:
> >Hello,
> >Can people help me with finding out the issues associated with
> >scheduling in run-time reconfiguration and in dynamic reconfiguration.
> >
> >all your suggestion are welcome
> >
> >thanks
> >supradeep
> 
> Can you please give us the full text of your homework assignment, so that
> we can be more amused.
> 
> Maybe also list what you have done so far, before posting your question.

Article: 72233
Subject: Re: new XILINX 9500XL datasheets
From: Jim Granville <no.spam@designtools.co.nz>
Date: Thu, 12 Aug 2004 12:22:31 +1200
Links: << >>  << T >>  << A >>
Mark Ng wrote:
> Hi Mike,
> 
> Your distributor is wrong in telling you that these 9500XL are not 
> recommended for new designs.  It is perfectly fine to start a new design 
> with 9500XL.
> 
> Xilinx has absolutely no intention of discontinuing the 9500XL devices. 
>  We are still seeing continued interest in new product designs.
> 
> As for your technical question below --  Table 3 in the datasheet is 
> incorrect.  If read and write protect are both set, then a read will be 
> inhibited, and a program/erase attempt will prompt a Warning in the 
> iMPACT programming software.  You can still erase/program the part.  In 
> summary, this means you can still erase/reprogram the part even though 
> write protect is set.
> 
> We'll fix the datasheet asap...
> 
> Thanks!
> Mark

  Not bad! - my tags show this was ~90 minutes : All questions clearly
answered, and a promise to fix the oops.
-jg


Article: 72234
Subject: Re: ISE 6.2 : Place problem with V2PRO
From: "Antti Lukats" <antti@case2000.com>
Date: Wed, 11 Aug 2004 17:50:52 -0700
Links: << >>  << T >>  << A >>
"gilles" <georges@irisa.fr> wrote in message
news:cfd78b$cj2$3@amma.irisa.fr...
> Dear,
>
> I have a V2PRO design using PPC405 and several peripheral including
> plb_ddr. When i try to implement my top_level deign i got the following
> error during PAR :
>
> Phase 8.24
> ERROR:Place:17 - The current designer locked placement of the IOBs
> IMM_MASK<0> and DIMM_STROBE<0> makes this design unroutable due to a
> physical routing limitation. This device has a shared routing resource
> connecting the ICLK and OTCLK pins on pairs of IOBs.  This restriction
> means that these pairs of pins must be driven by the same signal or one
> of the signals will be unroutable. Before continuing with this design
> please unlock or move one of these IOBS to a new location.

constraint guide ( cgd.pdf ) page 436

UCF/NCF
The basic syntax is:
INST "instance_name" IOB={TRUE|FALSE|AUTO};

set IOB to FALSE for one of the problem IOS the last flip flop will not be
pushed to IOB and design will map

Antti



Article: 72235
Subject: Re: new XILINX 9500XL datasheets
From: hmurray@suespammers.org (Hal Murray)
Date: Wed, 11 Aug 2004 19:53:35 -0500
Links: << >>  << T >>  << A >>
>  Not bad! - my tags show this was ~90 minutes : All questions clearly
>answered, and a promise to fix the oops.

No marketing BS either.

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 72236
Subject: Re: How important are software tools while choosing FPGA
From: "Subroto Datta" <sdatta@altera.com>
Date: Thu, 12 Aug 2004 01:33:41 GMT
Links: << >>  << T >>  << A >>
"General Schvantzkoph" <schvantzkoph@yahoo.com> wrote in message
news:pan.2004.08.11.16.54.45.997863@yahoo.com...
> Software tools are very important. The Xilinx tools give you more control
then the Altera tools and they are much easier to script. If you do
> everything from the GUIs they are fairly similar but once you get
proficient you'll want to start doing everything with scripts and
> constraint files, that's when Xilinx pulls ahead.

Hello General Schvantzkoph,

While your comparison on scripting may have been true in the past itdoes not
reflect the current state of the Altera Quartus II software's
scripting capabilities.

Quartus supports two scripting methodologies:
a) Command line scripting for use with shell scripts and makefiles, similar
to the abilities available in competitive tools.
b) Tcl scripting or procedural scripting which is very powerful and allows
manipulation of design processes through a programming language which goes
beyond what is available in competitive tools.

The Quartus II software was re-architected starting with version 3.0 (June
2003) to fully support command line scripting operation and to
include a new simplified tool command language (tcl) scripting API similar
in format to the popular Synopsys SDC format. "Tcl scripting is a
defacto EDA industry standard supported by tools from Altera, Mentor
Graphics, Synplicity, Synopsys and others."

The following Quartus II software scripting resources are available to make
you familiar with the powerful scripting capabilities in Quartus II 4.1 :

Quartus II handook chapters:
Command Line Scripting Chapter:
http://www.altera.com/literature/hb/qts/qts_qii52002.pdf
Tcl Scripting Chapter:
http://www.altera.com/literature/hb/qts/qts_qii52003.pdf
Assignment Editor chapter (see Tcl interface section):
http://www.altera.com/literature/hb/qts/qts_qii52001.pdf

Tcl Design Examples:
Tcl Design Examples Page
http://www.altera.com/support/examples/tcl/tcl.html
Design Space Explorer custom exploration space example:
http://www.altera.com/support/examples/quartus/space.html

If you wish to learn more using an online format the following resources
will be available in the very near future:
Tech Online WebCast:
Enhance Your FPGA Design Flow Using Scripting, Sept. 16, 11:00 am PST
(further details to follow)

Recorded Online Training Classes: Coming Soon

Hope this helps.
- Subroto Datta
Altera Corp.



Article: 72237
Subject: How big is LEON on Virtex2?
From: zhao0043@infoeng.flinders.edu.au (tigtag04@yahoo.com.au)
Date: 11 Aug 2004 19:02:37 -0700
Links: << >>  << T >>  << A >>
I want to implement Leon on xc2v1000. But only one Leon core (only IU,
Icache and Dcache) occupies 99% SLICE. Can I put 2 LEONs on one fpga
(xc2v1000)? How can I minimize LEON?

Article: 72238
Subject: Re: How important are software tools while choosing FPGA
From: jhallen@TheWorld.com (Joseph H Allen)
Date: Thu, 12 Aug 2004 02:28:58 +0000 (UTC)
Links: << >>  << T >>  << A >>
I've been comparing the tools recently:

Altera: the built in synthesis tool is quite good, almost on par with
Synplicity (xst is nowhere near as good).  This makes Altera's tools a much
better value.  Also, the time to get going with SOCP is less than with
Xilinx EDK.  SOCP is more integrated with Quartus-II.

On the other hand, Altera does not have fpga_editor: the low level chip
editing tool.  It has a tool (chip editor), but you can not modify the
routing with it.  Instead to make a change you have to basically rerun the
place and route.  Of course if you are substantially changing your design
with fpga_editor, you have other problems...  Keep in mind that you can make
macros with fixed routing by hand with fpga_editor (useful for delay lines).

If you like scripting and hate GUIs, you will not like Altera.  Sure, you
can start with the GUI and then generate a script to recompile everything,
but you can't start a new design with all scripts.  For example, to use chip
features (like PLL) you run a wizard to generate or modify "megafunction"
macros which you then instantiate in your HDL design files.  Also you need
the GUI to enter timing and placement constraints (theoretically you could
do it with text, but there's no documentation).  For complex functions, the
wizard is probably better, but scripting people will still not like it.

Also, it's all one monolithic tool: the different functions are not really
exposed and the database is very closed.  You do not get to see the output
from one function and the input to another, or where one ends and another
begins.  Instead there is an integrated database which each tool accesses. 
This makes a 'makefile' somewhat meaningless.

Xilinx is definitely much better for scripting: each tool in the flow
documents its input files, output files and command line options.  I run
each tool in a separate directory so that I can clearly see what each one
does.

You can do an entire design with just a text editor.  For simple chip
features you can usually get by looking at the black box definition in the
Synplicity "virtex2.v" file (or whichever).

You really need to get Synplify.  Unfortunately the EDK does not work well
with a Synplicity flow.  (IMHO, Xilinx should just buy Synplify). An example
of the scripting nature of the Xilinx tools is this: for Altera SOCP, the
merge of your program's .elf file with the bitstream happens magically (it's
buried in the tools, it works, so don't worry about it).

With Xilinx, it doesn't work right away (because Synplicity and EDK and
ProjNav are not integrated), but by the time you get it working you
understand how ngdbuild takes a .bmm file as input, and bitgen creates a new
.bmm file on output and you are ready to make a script, understand the .bmm
file syntax and are thinking about how to load other non-program data into
block RAMs, now that you understand how it works.

On the other hand, Xilinx's GUI is not as clear as Altera's and there is
definitely a big learning curve to master the tools.

Anyway to summarize: Altera is more like Borland-C and Xilinx is more like
Microsoft C (if you were a C programmer in 1989 you would understand :-).

-- 
/*  jhallen@world.std.com (192.74.137.5) */               /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}

Article: 72239
Subject: Re: How important are software tools while choosing FPGA
From: Ken McElvain <ken@synplicity.com>
Date: Wed, 11 Aug 2004 21:26:55 -0700
Links: << >>  << T >>  << A >>

Joseph H Allen wrote:

> 
> You really need to get Synplify.  Unfortunately the EDK does not work well
> with a Synplicity flow.  (IMHO, Xilinx should just buy Synplify). An example
> of the scripting nature of the Xilinx tools is this: for Altera SOCP, the
> merge of your program's .elf file with the bitstream happens magically (it's
> buried in the tools, it works, so don't worry about it).

There is a nice appnote on using Synplify with the EDK.

http://www.synplicity.com/literature/syndicated/pdf/v4_i2/platform_studio_v4_i2.pdf
It was written by Milan Saini from Xilinx.

> 
> With Xilinx, it doesn't work right away (because Synplicity and EDK and
> ProjNav are not integrated), but by the time you get it working you
> understand how ngdbuild takes a .bmm file as input, and bitgen creates a new
> .bmm file on output and you are ready to make a script, understand the .bmm
> file syntax and are thinking about how to load other non-program data into
> block RAMs, now that you understand how it works.
> 
> On the other hand, Xilinx's GUI is not as clear as Altera's and there is
> definitely a big learning curve to master the tools.
> 
> Anyway to summarize: Altera is more like Borland-C and Xilinx is more like
> Microsoft C (if you were a C programmer in 1989 you would understand :-).
> 


Article: 72240
Subject: CLOCK_SIGNAL Constraint.
From: chandu_419@yahoo.com (Chandrasekhar)
Date: 11 Aug 2004 21:28:19 -0700
Links: << >>  << T >>  << A >>
Hi everybody...

    I m deriving 4 clocks in my module, are all gated with respect to
a synchronous individual clock enable signals. I m using this module
as a sub module for my toplevel design. While running PAR for the sub
module i m not getting any messages regarding CLOCK_SIGNAL constraint,
but if i run PAR for the toplevel in ISE 6.2.03i, it is displaying
"Please use CLOCK_SIGNAL constraint....".
 
    I tried and tired applying the constraints several ways, but there
is no change. All these clocks are of different frequency and have
different clock enable signals. Please help me to find a solution for
this problem.

Thanks in advance.

Regards...
Chandu

Article: 72241
Subject: Re: CLOCK_SIGNAL Constraint.
From: hmurray@suespammers.org (Hal Murray)
Date: Wed, 11 Aug 2004 23:57:01 -0500
Links: << >>  << T >>  << A >>
>    I m deriving 4 clocks in my module, are all gated with respect to
>a synchronous individual clock enable signals.

Using gated clocks in FPGAs is generally a bad idea.  Besically,
the hardware doesn't support it.  (neither does the software)

Try using the gating term as an enable on the FFs instead.

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 72242
Subject: Attention Xilinx: command line tools would be useful [Was: Re:
From: Adam Megacz <megacz@cs.berkeley.edu>
Date: Thu, 12 Aug 2004 01:14:07 -0700
Links: << >>  << T >>  << A >>

John Williams <jwilliams@itee.uq.edu.au> writes:
> I don't know about the Altera tools, but my understanding is that
> Xilinx webpack is not available for linux because they would have to
> pay per-seat licensing to the developer of the cross-platform GUI that
> they use.

Hey Xilinx, if you're listening, there are a *lot* of us who would
rejoice if you released the command line tools for Linux for free.
ESPECIALLY bitgen.  We can do without the gui.

  - a

Article: 72243
Subject: How to ? 2.1i to ISE6.2 SCHEMATIC converter!!
From: "buke2" <cubah@tlen.pl>
Date: Thu, 12 Aug 2004 10:17:30 +0200
Links: << >>  << T >>  << A >>
Anybody knows how convert schemtic from Xilinx 2.1 to ISE6.2 Webpack?
It is very strange that ISE6.2 cannot convert earlier version of schematic
(the same company).

THX



Article: 72244
Subject: Different capabilities
From: "Thomas Nilsen" <nospam@nospam.nospam>
Date: Thu, 12 Aug 2004 11:39:41 +0200
Links: << >>  << T >>  << A >>
Hello.
Im a new masters degree student and i want to have a kit at home.
I need help on selecting the right development kit for me.
What are the difference in capabilities for the Spartan 3, Spartan 2,
Spartan 2E. These three types seems like the boards that have a reasonable
price for me.

-
Thomas



Article: 72245
Subject: Looking for suggestions/recommendations on 64-bit Linux machine
From: Jim Wu <NOSPAM@NOSPAM.COM>
Date: Thu, 12 Aug 2004 09:42:36 GMT
Links: << >>  << T >>  << A >>
Sorry this is a little bit OT, but would appreciate any 
suggestions/recommendations on 64-bit Linux machine (processor, Linux 
distribution, vendor, etc) for FPGA development.

Thanks,
Jim
Jim (jimwu88NOOOSPAM@yahoo.com remove NOOOSPAM)
http://www.geocities.com/jimwu88/chips

Article: 72246
Subject: Re: ISE 6.2 : Place problem with V2PRO
From: gilles <georges@irisa.fr>
Date: Thu, 12 Aug 2004 11:45:35 +0200
Links: << >>  << T >>  << A >>
Bret Wade wrote:
> gilles wrote:
> 
>> Dear,
>>
>> I have a V2PRO design using PPC405 and several peripheral including 
>> plb_ddr. When i try to implement my top_level deign i got the 
>> following error during PAR :
>>
>> Phase 8.24
>> ERROR:Place:17 - The current designer locked placement of the IOBs 
>> IMM_MASK<0> and DIMM_STROBE<0> makes this design unroutable due to a 
>> physical routing limitation. This device has a shared routing resource 
>> connecting the ICLK and OTCLK pins on pairs of IOBs.  This restriction 
>> means that these pairs of pins must be driven by the same signal or 
>> one of the signals will be unroutable. Before continuing with this 
>> design please unlock or move one of these IOBS to a new location.
>>
>>
>> I can't move then i use a AVNET Dev board so schematic is fixed !!
>>
>> I use ISE / EDK 6.2 with latest Service Pack on Linux.
>>
>> I found a answer record on xilinx website (N 18780) reporting this 
>> problem for ise 6.1 fixed with 6.1 SP3, and they say that il will be 
>> fixed in 6.2.
>> But, it's still here !!!
> 
> 
> Hello Gilles,
> 
> The problem described in Answer 18780 is indeed fixed in version 6.2i 
> but you still need to set the environment variable mentioned there.
> 
> It's also possible that the problem you are seeing is unrelated to 
> problem described in Answer 18780. The same errors can occur for other 
> reasons. If you are seeing the 18780 problem, the IOB sites involved 
> will be located next to DCMs. Check this in FPGA Editor for 
> confirmation. If that is not the case, consider the possibility that the 
> error messages are valid and that you have a design issue.
> 
> If you do have a design issue, It may be possible to correct the problem 
> by controlling the FF BEL usage (BEL = IFF1|IFF2|OFF1|OFF2) or by 
> disabling a FF pack in the IOB (IOB = FALSE). If you are in fact needing 
> to get more than two input or two output clocks into a single IOB pair 
> then you are running into a hardware limitation with the routing 
> resources (Answer 11747) and there is no solution.
> 
> Regards,
> Bret Wade
> Xilinx Product Applications
> 
>>
>> 2 questions :
>> - Did anyone get this kind of problem with 6.2, and what the solution ?
>> - It is a good idea to install ISE 6.1 SP3 on my PC ?
>>
>> Thanks for your suggestions
>>
>> Gilles
> 
> 


Hello,

Thanks all for your help.

Given your suggestions, i found the source of my problem.
It's not the problem report in Answer 18780 (sorry Xilinx :) ), but 
effectivly a design issue.
I use the ddr clock module reference design (included in EDK) to 
generate my design clk signals as mentionned in the opb ddr controller 
doc (i use opb ddr and not plb not a s i write in my first post).
With this module i provide clk, clk90_in and ddr_clk90_in differential 
clocks to the DDR core. The problem is that STROBE signals are generate 
fron clk90_in and MASK fron clk => Hardware limitation.

Regarding Duane solution, how can i use the same clock for both signals 
when use opb ddr core : sould i modify the core design itself ??

Gilles

Article: 72247
Subject: Re: How important are software tools while choosing FPGA
From: david@fpgaworld.com (David Kallberg)
Date: 12 Aug 2004 05:17:40 -0700
Links: << >>  << T >>  << A >>
So to summarize if you were NOT a C programmer in 1989:)

If you use scripts you would prefer Xilinx and if you like GUI based
you would prefer Altera. My personal experience is that the Quartus
GUI is far better than the Xilinx ISE GUI. I have used scripts on both
and I beleive they work fine. Never tried EDK/SOCP!

David
www.FPGAworld.com

jhallen@TheWorld.com (Joseph H Allen) wrote in message news:<cfekla$a9r$1@pcls4.std.com>...
> I've been comparing the tools recently:
> 
> Altera: the built in synthesis tool is quite good, almost on par with
> Synplicity (xst is nowhere near as good).  This makes Altera's tools a much
> better value.  Also, the time to get going with SOCP is less than with
> Xilinx EDK.  SOCP is more integrated with Quartus-II.
> 
> On the other hand, Altera does not have fpga_editor: the low level chip
> editing tool.  It has a tool (chip editor), but you can not modify the
> routing with it.  Instead to make a change you have to basically rerun the
> place and route.  Of course if you are substantially changing your design
> with fpga_editor, you have other problems...  Keep in mind that you can make
> macros with fixed routing by hand with fpga_editor (useful for delay lines).
> 
> If you like scripting and hate GUIs, you will not like Altera.  Sure, you
> can start with the GUI and then generate a script to recompile everything,
> but you can't start a new design with all scripts.  For example, to use chip
> features (like PLL) you run a wizard to generate or modify "megafunction"
> macros which you then instantiate in your HDL design files.  Also you need
> the GUI to enter timing and placement constraints (theoretically you could
> do it with text, but there's no documentation).  For complex functions, the
> wizard is probably better, but scripting people will still not like it.
> 
> Also, it's all one monolithic tool: the different functions are not really
> exposed and the database is very closed.  You do not get to see the output
> from one function and the input to another, or where one ends and another
> begins.  Instead there is an integrated database which each tool accesses. 
> This makes a 'makefile' somewhat meaningless.
> 
> Xilinx is definitely much better for scripting: each tool in the flow
> documents its input files, output files and command line options.  I run
> each tool in a separate directory so that I can clearly see what each one
> does.
> 
> You can do an entire design with just a text editor.  For simple chip
> features you can usually get by looking at the black box definition in the
> Synplicity "virtex2.v" file (or whichever).
> 
> You really need to get Synplify.  Unfortunately the EDK does not work well
> with a Synplicity flow.  (IMHO, Xilinx should just buy Synplify). An example
> of the scripting nature of the Xilinx tools is this: for Altera SOCP, the
> merge of your program's .elf file with the bitstream happens magically (it's
> buried in the tools, it works, so don't worry about it).
> 
> With Xilinx, it doesn't work right away (because Synplicity and EDK and
> ProjNav are not integrated), but by the time you get it working you
> understand how ngdbuild takes a .bmm file as input, and bitgen creates a new
> .bmm file on output and you are ready to make a script, understand the .bmm
> file syntax and are thinking about how to load other non-program data into
> block RAMs, now that you understand how it works.
> 
> On the other hand, Xilinx's GUI is not as clear as Altera's and there is
> definitely a big learning curve to master the tools.
> 
> Anyway to summarize: Altera is more like Borland-C and Xilinx is more like
> Microsoft C (if you were a C programmer in 1989 you would understand :-).

Article: 72248
Subject: Re: Impact running on wine?
From: david@fpgaworld.com (David Kallberg)
Date: 12 Aug 2004 05:27:28 -0700
Links: << >>  << T >>  << A >>
Duane Clark <junkmail@junkmail.com> wrote in message news:<cfdjq701m7n@news2.newsguy.com>...
> David Kallberg wrote:
> > I tried to do it, but it didn't work. 
> > David
> 
> What did you try? The native version of Impact does work, but unless you 
> are running the officially supported version of RH8, there are a few 
> steps you need to follow. Mainly, you need to recompile the driver 
> against the source for whatever kernel you are using. Not exactly 
> trivial, but it does work. The instructions and source code are 
> available from Xilinx:
> 
> http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=18612
> 
> 
> > 
> > John Williams <jwilliams@itee.uq.edu.au> wrote in message news:<cf8u9c$4uo$1@bunyip.cc.uq.edu.au>...
> > 
> >>...
> >>If you are using normal Xilinx ISE tools they can be installed native 
> >>under Linux - Impact works fine.
> >>
> >>Regards,
> >>
> >>John

Thanks for the tips John!
I ran RH7.3... I will try this the next time...

Article: 72249
Subject: 95108 doesnt program
From: dvgadre@gmail.com (FPGANewbie)
Date: 12 Aug 2004 05:36:03 -0700
Links: << >>  << T >>  << A >>
I have a few XC95108 (-20 speed grade), PC84 package. One of them
programs OK using a self designed test board and xilinx published
parallel port JTAG circuit. The rest of these CPLDs dont program.
Impact s/w erases them properly, but while programming, it just doesnt
seem to be doing nothing. Probing the JTAG signals on the CPLD does
show some activity, but the programming doesnt finish. Any tips? I
have tried various cable lengths between the Dongle and the CPLD board
and it doesnt help.

Thanks,

FPGANewbie



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