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Symon, Checking..... Austin Symon wrote: > Austin, > Are the blocks of code misplaced in Table 2? I'd say the code on the left > had two levels of pipeline. > Cheers, Syms. > "Austin Lesea" <austin@xilinx.com> wrote in message > news:cp4k3n$puu1@cliff.xsj.xilinx.com... > >>All, >> >>http://www.xilinx.com/bvdocs/whitepapers/wp218.pdf >> >>For anyone interested in how V4 really stacks up. >> >>Austin > > >Article: 76626
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Article: 76627Hello, I read the XAPP 290 which provides guidelines for partial reconfiguration. I have a couple of questions with regard to some of the constraints imposed by xilinx. 1. Can I not divide the FPGA into a set of rectangles and say that each of these rectangles are reconfigurable. If so how do I define the area constraints of the module? 2.Why is it that you cannot define a reconfigurable module to be a rectangular region? I am aware of the fact that Xilinx is a column based device, however if I can tolerate the overhead involved in reading the frames for all those columns and modifying just the rectangular region. Can this not be done? To be more clear if we consider 4 CLB columns and asume that there are 3 reconfigurable modules present in those columns. Each of these modules extend three column width but the height of it are different. (imagine the modules are stacked one upon another). Now if I want to reconfigure one of the three modules then can I not read the bit stream from all the 4 columns modify the particular data in the frames corresponding to the module that I want to replace with another module and write back all the frames. Can this not be done? 3. Why are the reconfigurable modules are to be constrained to just the horizontal boundary of 0,4,8 etc? 4. The area group constraint says that you can constrain the area of the module within the particular region of the FPGA. However it does not ensure that the routing resources will be within the specified area. If we define a bounding box as the set of all routing and CLB resources then in the worst case how much more area can we expect that the routing resource will be extended to? For example I define a rectangular region of fixed length and width is there a safe assumption we can make that the design will not exceed this much percentage of width and this much percentage of length Can anyone please clarify my doubts? ThanksArticle: 76628
Al, Also note that Verilog /= VHDL If you are interested in VHDL, I like: A VHDL Primer by J Bhasker. Cheers, Jim > I want to learn Verilog for small FPGA degigns. I don't have a background > in VHDL but I am an experienced designer. For simple designs, I have used > the schematic capture method. > > What do you guys recommend? > > -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Director of Training mailto:Jim@SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787 Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~Article: 76629
Yes, Code is swapped in the table. Will be fixed shortly. Thank you to all who caught it. It is not supposed to be a test! Austin steven derrien wrote: > Hi Austin, > > I just had a quick look, and there seems to be a mistake in table 2, p.5 > (Verilog descriptions should be swapped for one stage vs two stage > pipeline). > > Regards, > > Steven > > > Austin Lesea wrote: > >> All, >> >> http://www.xilinx.com/bvdocs/whitepapers/wp218.pdf >> >> For anyone interested in how V4 really stacks up. >> >> Austin > >Article: 76630
Jim Lewis <Jim@SynthWorks.com> wrote in news:10rbv4f18pammbb@corp.supernews.com: > Al, > Also note that Verilog /= VHDL > > If you are interested in VHDL, I like: > A VHDL Primer by J Bhasker. > > Cheers, > Jim Thanks Jim, I know that Verilog is not VHDL. I was just trying to point out that I don't have that background either. I am using Verilog because a portion of my project was already written in Verilog by someone else. Al >> I want to learn Verilog for small FPGA degigns. I don't have a >> background in VHDL but I am an experienced designer. For simple >> designs, I have used the schematic capture method. >> >> What do you guys recommend? >> >> > > -- Al Clark Danville Signal Processing, Inc. -------------------------------------------------------------------- Purveyors of Fine DSP Hardware and other Cool Stuff Available at http://www.danvillesignal.comArticle: 76631
Harish wrote: > > Hello, > > I read the XAPP 290 which provides guidelines for partial > reconfiguration. I have a couple of questions with regard to some of > the constraints imposed by xilinx. > > 1. Can I not divide the FPGA into a set of rectangles and say that each > of these rectangles are reconfigurable. If so how do I define the area > constraints of the module? > > 2.Why is it that you cannot define a reconfigurable module to be a > rectangular region? I am aware of the fact that Xilinx is a column > based device, however if I can tolerate the overhead involved in > reading the frames for all those columns and modifying just the > rectangular region. Can this not be done? Sure, anything can be done. But Xilinx does not provide software to do it. You will have to do that yourself. The hard part is constraining *BOTH* your module logic and routing to that rectangle. > To be more clear if we consider 4 CLB columns and asume that there are > 3 reconfigurable modules present in those columns. Each of these > modules extend three column width but the height of it are different. > (imagine the modules are stacked one upon another). Now if I want to > reconfigure one of the three modules then can I not read the bit stream > from all the 4 columns modify the particular data in the frames > corresponding to the module that I want to replace with another module > and write back all the frames. Can this not be done? Sure. How do you plan to implement this though? Are you going to write your own software? > 3. Why are the reconfigurable modules are to be constrained to just the > horizontal boundary of 0,4,8 etc? Because the CLBs span that width, IIRC. > 4. The area group constraint says that you can constrain the area of > the module within the particular region of the FPGA. However it does > not ensure that the routing resources will be within the specified > area. If we define a bounding box as the set of all routing and CLB > resources then in the worst case how much more area can we expect that > the routing resource will be extended to? For example I define a > rectangular region of fixed length and width is there a safe assumption > we can make that the design will not exceed this much percentage of > width and this much percentage of length > Can anyone please clarify my doubts? You are correct about the typical LOC constraints. I have not dug deeply enough into it to know how they contrain the routing to column boundaries, but they must have a special way of doing this to allow this to work at all. I also have no idea if you can use the same method to constrain routing to vertical regions which you would need to work with rectangles. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 76632
Al Clark wrote: > > Jim Lewis <Jim@SynthWorks.com> wrote in > news:10rbv4f18pammbb@corp.supernews.com: > > > Al, > > Also note that Verilog /= VHDL > > > > If you are interested in VHDL, I like: > > A VHDL Primer by J Bhasker. > > > > Cheers, > > Jim > > Thanks Jim, > > I know that Verilog is not VHDL. I was just trying to point out that I > don't have that background either. > > I am using Verilog because a portion of my project was already written in > Verilog by someone else. One suggestion, always write your synthesizable code from the examples given by the tool vendors. Both VHDL and Verilog will compile and simulate code that can no be synthesized. So design your hardware first, as a block diagram or in any other form that lets you see the registers and blocks of logic. Then write your code using the examples the vendors provide for the various blocks in your diagram. When used to build hardware, HDLs are not programming languages. They are hardware description languages, hence HDL, not HPL. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 76633
> Is it possible to "cheat" and reduce this complexity, if I know that I > will > literally only ever have exactly zero one specific device connected? I'm investigating options for something quite similar. Please keep in touch, to exchange experiences! Now I'm doing the peripheral side, but sooner or later I will have no more excuses to delay the difficult part :-). I did my best to avoid having doing this, but finally I was persuaded was the only reasonable way, given marketing / commercial constraints. Reducing options to just your custom device, without any hub, seems much more easier. In my case, I can and surely will. Absolutely. The host stack itself is way easier, if you do not have to handle all hub stuff, also. I'll use an FPGA together with a softcore (Mblaze) for stack handling. Data will come as an isochronous HS stream, so I'll try to route them inside the FPGA directly to the logic that needs them, avoiding the softcore. Decision left is whether to use an external embedded HS host (not so many, here, for true HS. Philips ? TransDimensions ?) or a HS host core inside the FPGA. I'd prefer the second, of course, but usually this kind of cores costs an arm and a leg. Check www.asics.ws, they are quite experienced, and as you see Rudolf Usselman reads and follows this newsgroup. I think Antti Lukats can help you, also, it's rather knowledgeable in USB + fpga. In any case, please share your experiences with this group. I'll surely will (if going okay... otherwise, i'll be too busy searching for a new job :-) Standard disclaimer applies, here: I have no connection to them. Just thinking to calling them for help, given that they seems the best option, in my opinion (as today).Article: 76634
Might want to check out "HDL Chip Design" by Douglas H. Smith. Teaches Verilog, VHDL, and shows the schematic equivalent next to the code. -- Pete Al Clark wrote: > I want to learn Verilog for small FPGA degigns. I don't have a background > in VHDL but I am an experienced designer. For simple designs, I have used > the schematic capture method. > > What do you guys recommend? > > > -- > Al Clark > Danville Signal Processing, Inc. > -------------------------------------------------------------------- > Purveyors of Fine DSP Hardware and other Cool Stuff > Available at http://www.danvillesignal.comArticle: 76635
"John_H" <johnhandwork@mail.com> schrieb im Newsbeitrag news:yB5td.10$a61.633@news-west.eli.net... > The difference between 906,238,099/2^32 and 906,238,099.456/2^32 is about > 5.03e-10 at which point small amounts of jitter are lost. If the jitter at > that tiny offset is large, you will experience phase jumps when that beat > frequency is felt. There's no way to filter those with analog filters. I guess the trick is noise shaping. Adding a (pseudo)random phase error to distribute the jitter energy over a wider band and also move it to higher frequencies. Sigma-Delta Style. Regards FalkArticle: 76636
"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:31mt3nF3d9asiU1@individual.net... > > "John_H" <johnhandwork@mail.com> schrieb im Newsbeitrag > news:yB5td.10$a61.633@news-west.eli.net... > > > The difference between 906,238,099/2^32 and 906,238,099.456/2^32 is > about > > 5.03e-10 at which point small amounts of jitter are lost. If the jitter > at > > that tiny offset is large, you will experience phase jumps when that beat > > frequency is felt. There's no way to filter those with analog filters. > > I guess the trick is noise shaping. Adding a (pseudo)random phase error to > distribute the jitter energy over a wider band and also move it to higher > frequencies. Sigma-Delta Style. > > Regards > Falk Noise shaping is the right way to go for a superb quality synthesizer, but the correction phase error - the output from the noise shaper - needs to be applied based on the synchronous edge position relative to the "ideal" edge position - the input to the noise shaper. (Pseudo)Random doesn't do it. All this assumes, of course, that there's an analog PLL driven by the single bit, noise-shaped NCO output. Without the PLL to filter out the high frequency phase noise of a Sigma-Delta style NCO, the jitter is still around 1 reference clock period peak-to-peak, maybe worse. (NCOs are used by many folks in the comp.arch.fpga newsgroup who have no reason to visit comp.dsp.)Article: 76637
I just got my Spartan3 board from Digilent, and I noticed it didn't come with any software on CD. I have installed Xilinx ISE 6.3 and want to try something (anything) out on it. What is the FPGA equivalent of the "Hello world" program? Also, what is the best way, in terms of functionality, for a beginner to program this FPGA (and several peripherals I got for it)? It must be free, because at this stage, I don't know exactly what features I will want. cheersArticle: 76638
>I went to look through >some answer records and was offered Viagra instead. >Make it your ASIC indeed! > Looks like some sort of FIRMWARE offering eh?Article: 76639
On Wed, 8 Dec 2004 11:55:00 +1100, "C3" <_> wrote: >I just got my Spartan3 board from Digilent, and I noticed it didn't come >with any software on CD. I have installed Xilinx ISE 6.3 and want to try >something (anything) out on it. What is the FPGA equivalent of the "Hello >world" program? Flash an LED at a rate of roughly once per second. This makes sure that: 1) the power is at least close to correct.1 2) the bits can be loaded correctly. 3) the clock is running, and is roughly the correct frequency. 4) at least a few pins are located at the right place. Once you get that done, try each of the peripherals in as simple of way as you can. Phil Hays -- Phil Hays Phil-hays at posting domain should work for emailArticle: 76640
> What is the FPGA equivalent of the "Hello > world" program? Blink the LEDs. That needs a counter or such to slow it down enough to see. If you have a scope, you can bypass that compliction. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 76641
There are a handful of designs that you can download from the Spartan-3 Starter Kit web page. www.xilinx.com/s3boards For a real simple HDL Hello world equivalent I would recommend 'Digital Clock using Multiplexed 7-Segment Display' Cheers, Shalin- C3 wrote: > I just got my Spartan3 board from Digilent, and I noticed it didn't come > with any software on CD. I have installed Xilinx ISE 6.3 and want to try > something (anything) out on it. What is the FPGA equivalent of the "Hello > world" program? > > Also, what is the best way, in terms of functionality, for a beginner to > program this FPGA (and several peripherals I got for it)? It must be free, > because at this stage, I don't know exactly what features I will want. > > > cheers > >Article: 76642
A 2-input AND gate would be a good one. Make 2 of the switches on your board as the inputs. Connect the output to one of the LED. HendraArticle: 76643
There should already be Digilent's test program loaded onto the board. On the pegasus board (S2) it increments the 7 segment display and connects each of the switches to the LED's. Plug it in and try it out. Digilent's website also has instructional videos for using Xilinx Webpak. I would start by modifying Digilent's program. Then perhaps make a switch debouncer and make the led flash. Then perhaps play with the seven segment display - like an incrementer that increments the display each time a button is pushed. I would save the digital clock for later unless you have prior HDL experience. A digital clock is alot to do before testing at least once. Cheers, Jim > I just got my Spartan3 board from Digilent, and I noticed it didn't come > with any software on CD. I have installed Xilinx ISE 6.3 and want to try > something (anything) out on it. What is the FPGA equivalent of the "Hello > world" program? > > Also, what is the best way, in terms of functionality, for a beginner to > program this FPGA (and several peripherals I got for it)? It must be free, > because at this stage, I don't know exactly what features I will want. > > > cheers > > -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Director of Training mailto:Jim@SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787 Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~Article: 76644
This is a symptom that I think was introduced in edk 6.2 sp2 and apparently is also present in edk 6.3 The problem is that as the main system clock (generated by a DPLL and constrained) is being passed through modules such as lmb_cntlr which is taking the system clock and puts out a BRAM clock (purely pass through). The BRAM clock will be unconstrained and break our system timing. The timing report under "Requested" shows "N/A". I can manually edit the system.v and change the input clock to the BRAM to be my system clock - that will fix that particular clk net, but push the problem to some other net. Before EDK 6.2 sp2, I was able to meet timing with only 5 minutes of compile time. Now I can't meet timing anymore after running for more than 30 minutes. Is there a fix for this ? Thanks ! rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and SynthesisArticle: 76645
Hi, I use V2P70 to control DDR SDRAM (HY5DU561622CT-J) in the clock of 166MHZ. The row address of this chip if [12:0]. The strange thing is that sometimes one of ddr chip will regardless parital row address[12:9]. Then this chip size is become from 16Mb * 16 to 1Mb * 16. What kind of wrong operation will make ddr chip become this error. since the error will recover after power off-on. BTW, reconfiguation FPGA or reinit DDR SDRAM can not help DDR chip leave from this error. sincerely, seyorArticle: 76646
Jacob Bower wrote: > Rudi, > >> It's doable in hardware, but extremely complex. The enumeration >> process needs quite a bit of decisions making. > > Is it possible to "cheat" and reduce this complexity, if I know that I > will literally only ever have exactly zero one specific device connected? Jake, Yes, thats definitely possible. You could skip a lot of the steps if you know the device that will be attached. > Are there any free/commercial IP cores around that could help with this? We only have commercial host controller IP Cores. Check our web site for more info. >> Not sure what your interpretation of "high bandwidth" is, but >> USB 2.0 only goes to 480 Mbits/sec, or about 60Mbyes/sec. So >> it should be quite trivial to do this in FPGA. However you >> will need a High Speed USB PHY. > > It doesn't matter if it can be done completely in hardware. The only > reason I wanted to mention high-bandwidth was for the case where I would > have to use a soft-core processor as the complexity of driving the USB > host controller is too great to be feasible in anything but software. Then > of course I would have the consideration that the processor would need to > be fast enough to handle passing through the data. Well, the control path and data path can be separate. You can have a small low end MCU doing the enumeration, and a pure hardware based data pipe for the endpoints. It all depends on how robust you rimplementation has to be ... > Thanks for the suggestions, > - Jake Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and SynthesisArticle: 76647
Hi Colin, Below I try to give some insight into how to make a hot design, though I do question the motivation of doing so. A simple FF chain comes no where close to achieving a high (or even average) core power. All of the phenomena I describe below are modeled in the recently released Quartus II 4.2 software via its PowerPlay Power Analyzer. Target Stratix II or Max II and you'll get very accurate estimates of how all these factors affect your power consumption. You can try out the Power Analyzer in the Quartus II 4.2 Web Edition software available from www.altera.com. If you're trying to figure out if a given design will work on your board after it's been made, the best bet is to try the chip out in the lab using stimulus (vectors) that reflect the worst-case operating conditions for the chip. I can make you a design that will burn many many Watts of power, but that doesn't mean your design will. A dynamic power measurement from the lab is the most accurate estimate possible -- just remember to use the manufacturer's spec for worst-case static power (at worst-case temperature) since the unit you have on your board is likely NOT worst-case. > The estimator is just that, but is there a more accurate way of > writing some code so that a particular clock input will generate a > particular amount of heat. A 2000 D type serial chain where every flip > flop is toggling every clock which blinks an LED is obviously one way > but doesn't seem very ellegant. There are many factors that affect overall dynamic power consumption of an FPGA design. I will highlight a few critical ones below, and make suggestions along the way to build a design to turn your FPGA into the hot-plate you desire. It is *not* as simple as making one big shift-register... (0) Transition Density. You want to toggle as much every cycle as possible. Toggle FF/shift register achieve this, as do XOR functions (if you want to utilize the LUT too). (1) Routing Utilization. The routing buffers, multiplexers, and wiring in an FPGA can add up to a large amount of switching capacitance and short-circuit (crowbar) current. To maximize dynamic power, you must use a lot of routing. A simple FF chain will actually use very little routing, unless you purposely make the placement very bad by using region constraints such as LogicLock regions. You could, for example, constrain the even bits of your chain to one-half the chip and the odd bits to the other half, and this will greatly increase routing utilization. Or use something other than FFs to increase the number and fanout of the routed wires. Of course, you'll need to experiment a little to find the right balance between high utilization and still being able to route! (2) LUT Configuration. A LUT configured as an AND gate does not burn nearly as much power as one configured as an XOR. This difference is due to the number of internal nodes in the circuit that toggle states upon the toggle of in input signal. On top of this, the output of an XOR will toggle upon the toggle of any input -- so chaining together XORs will result in a cascade of glitching (if there are no pipeline registers), which can further increase your power. To get the most accurate estimate of LUT power, you must consider the functionality of the LUT -- Quartus II can do this for you. (3) Clock Network. The vast majority of power on a high-fanout clock will be burned *inside* the LABs (on the LAB-wide clock), not on the global clock network. If you distribute a clock such that it fans out to one FF (out of 16) in every LAB of the device, this will maximize this internal LAB clock network power. You can achieve this through location constraints applied to these FFs. And the more clocks you use, the more you will burn. You can use the PLLs to step up the clock frequency to help increase the toggle rate. (4) RAMs. A RAM can burn significant power if you perform reads & writes every cycle (keep the clock enable asserted). Just hook up all the RAMs in the device to be in dual-port mode writing & reading random data every cycle, and you've got some more power. (5) I/Os. You can burn an arbitrary amount of power with your I/Os, depending on external termination resistance, contention, I/O standard, drive strength, load capacitance, etc. Let's just pretend you don't have I/Os to make life easier. Hopefully that gives you some ideas of where to go to burn some power. If your using a Xilinx chip, I'm sure similar techniques will apply, though their tools may not be able to fully predict the results you will see. Regards, Paul Leventis Altera Corp.Article: 76648
How about dual port BRAM? My understanding is that both the ports have access to the same BRAM. So if in through one port you want to read the data and through the other port you want to write the data to same memory location what will happen? ThanksArticle: 76649
Hi All, I m facing some problems with clock gating in Virtex II FPGA using BUFGMUX, The Xilinx ISE 6.2.03i is saying the design is not completely routable. I know that clock gating in an FPGA is not advisable, but my requirement is like that. I have total 15 clocks of 5 diffterent frequencies. All these 15 clocks are gated with gate enable before going to the individual modules. The gating must be done in my clock tree module only. Can anyone please give some inputs on this... Any help will be greatly appreciated. Thanks... Chandrasekhar.
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