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>You need a testcase, fixing a bug where the description is "it crashes >sometimes" is impossible. Nonsense. Mostly you need somebody smart who is intersted in fixing the problem and has enough time to tackle it. If a system only crashes once every 100 days people can live with it. If it crashes once per day you can (usually) work out a test case. The intermediate cases get more "interesting". In hindsight, the ones I've been involved with are pretty obvious. At least after you know where to look. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 76751
On Fri, 10 Dec 2004 17:58:47 +1100, Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> wrote: >The AD9901 is basically an XOR gate with an added frequency >discriminator. ... and T flip flops on the XOR inputs to ensure 50% duty cycle. AllanArticle: 76752
"Artenz" <usenet+5@ladybug.xs4all.nl> wrote in message
news:80a355e0.0412091330.49973f14@posting.google.com...
> I am trying to combine a 4 bit logic function and a 4-1 mux on the
> result. For example:
>
> wire [3:0] a;
> wire [3:0] b;
> wire f;
> wire [1:0] s;
> wire out;
> wire [3:0] t;
>
> assign t = f ? (a | b) : (a & b);
> assign out = t[s];
>
> Where a and b are 4 bit inputs, f selects a function on them, and t[s]
> selects one of the 4 result bits.
>
> Looking at the CLB diagram, I was thinking this would fit in 4 LUTs
> for the logic, followed by a MUXF5 and a MUXF6 for the selection.
>
> Somehow, I end up with 6 LUTs and a MUXF5 (using XST 6.2). Now, I've
> tried using manual instantiations of the MUXF5/MUXF6. This way I end
> up with the proper muxes, but they are fed by 1-input LUTs, and the
> logic is calculated somewhere else.
>
> Does anybody know a way to convince XST to fit this in 4
> LUTs/MUXF5/MUXF6 ?
one word! think!
see below
---------------------
module lut_test(a,b,c,f);
input f;
input [3:0] a;
input [3:0] b;
output [3:0] c;
wire [3:0] a;
wire [3:0] b;
wire f;
wire [1:0] s;
wire out;
wire [3:0] t;
//assign t = f ? (a | b) : (a & b);
//assign c = t[s];
assign c[0] = (f & (a[0] | b[0])) | (!f & (a[0] & b[0]));
assign c[1] = (f & (a[1] | b[1])) | (!f & (a[1] & b[1]));
assign c[2] = (f & (a[2] | b[2])) | (!f & (a[2] & b[2]));
assign c[3] = (f & (a[3] | b[3])) | (!f & (a[3] & b[3]));
endmodule
-----------------------
Cell Usage :
# BELS : 4
# LUT3 : 4
# IO Buffers : 13
# IBUF : 9
# OBUF : 4
=========================================================================
Device utilization summary:
---------------------------
Selected Device : 3s1000ft256-4
Number of Slices: 2 out of 7680 0%
Number of 4 input LUTs: 4 out of 15360 0%
Number of bonded IOBs: 13 out of 173 7%
=========================================================================
Article: 76753Prentice Hall released Xilinx 6.3i Student Edition today. vig.prenhall.com/catalog/academic/product/0,1144,0131858394,00.html What is the different between it and Webpack or BaseX? Anybody from Xilinx can answer my question? HendraArticle: 76754
rickman wrote: > Kolja Sulimma wrote: > >>rickman wrote: >> >> >>> This has been discussed >>>many, many times here and I still don't see any open source tools that >>>are worth using. >> >>You probably use a lot of open source tools allready >>- spice >>- espresso (which is part of ISE, IIRC) >>- gcc (which is part of EDK) >>- tcl (which is part of allmos every EDA tool around that does not use a >>lisp dialect instead) > > > I find that I have to pay a lot of money for most of my tools and they > don't provide any source. In fact, they expressly forbid me from > reverse engineering the tools. > > Are those the tools that you meant? Yes, and actually there is a tcl license notice in the ISE distribution for example. However, I there also is a license note in the parant directory, that states that "BY USING THIS SOFTWARE" you have certain implications and are granted only a limited license. I really think that this is misleading because it is not made cleare that "THIS SOFTWARE" only applies to some of the software in the subdirectories. Someone who reads the xilinx license note surely does not expect to find additional license notes hidden in subdirectories that grant additional rights to part of the software. I do not know much about US law, but my copy was distributed in germany, and here both the TCL authors and competitors of Xilinx could sue Xilinx to have this clarified. Other license notes in the ISE distribution are *a Java license three directoriy levels lower. *an IEEE VHDL copyright notice But the distribution also contains perllib which is under GPL and I can not find any GPL notice in the distribution. (Competitors and the FSF could use this fact to stop distribution of the CDs and to call back all copies) Also, I can not find the BSD license for Espresso. SCO tries to make the world believe, that the open source community does not honor copyright, but this is another case were a proprietary software vendor does not honor the copyright of open source authors. Please fix this. The missing license notes should be contained in the next service pack. Kolja SulimmaArticle: 76755
Hello. I am using Xilinx ISE Foundation 6.3i. I am trying to implement a sine lookup table (targeted at either SpartanIII or VirtexII) but I am getting a strange result when running functional simulation (testbench bellow) with Modelsim: instead of showing the first element from the array on the output after the first rising edge it shows the 12th. Everithing happens as if I had initialized the address counter with 11 instead of 0. I know I am making a basic mistake but I cannot figure out where or why. -------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity sintab20 is Port ( i_Clk : in std_logic; i_En : in std_logic; i_Addr : in integer range 0 to 19; o_DataOut : out std_logic_vector(17 downto 0) ); end sintab20; architecture Behavioral of sintab20 is subtype t_ROM_DATA is std_logic_vector(17 downto 0); type t_ROM_TYPE is array (natural range <>) of t_ROM_DATA; constant k_SinTab20x1: t_ROM_TYPE(19 downto 0) := ( "000000000000000000", "001001111000110111", "010010110011110010", "011001111000110111", "011110011011110000", "011111111111111111", "011110011011110000", "011001111000110111", "010010110011110010", "001001111000110111", "000000000000000000", "110110000111001001", "101101001100001110", "100110000111001001", "100001100100010000", "100000000000000001", "100001100100010000", "100110000111001001", "101101001100001110", "110110000111001001" ); begin process (i_Clk) begin if rising_edge(i_Clk) then if (i_En = '1') then o_DataOut <= k_SinTab20x1(i_Addr); end if; end if; end process; end Behavioral; ------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY sintab20_tb IS END sintab20_tb; ARCHITECTURE behavior OF sintab20_tb IS COMPONENT sintab20 PORT( i_Clk : IN std_logic; i_En : IN std_logic; i_Addr : IN integer range 0 to 19; o_DataOut : OUT std_logic_vector(17 downto 0) ); END COMPONENT; SIGNAL i_Clk : std_logic; SIGNAL i_En : std_logic; SIGNAL i_Addr : integer range 0 to 19; SIGNAL o_DataOut : std_logic_vector(17 downto 0); constant k_PERIOD : time := 20 ns; BEGIN uut: sintab20 PORT MAP( i_Clk => i_Clk, i_En => i_En, i_Addr => i_Addr, o_DataOut => o_DataOut ); -- *** Test Bench - User Defined Section *** i_En <= '1'; -- clock process begin for i in 0 to 40 loop i_Clk <= '0'; wait for k_PERIOD/2; i_Clk <= '1'; wait for k_PERIOD/2; end loop; wait; end process; -- address counter process begin i_Addr <= 0; wait for k_PERIOD*2; for i in 0 to 40 loop if i_Addr < 19 then i_Addr <= i_Addr + 1; else i_Addr <= 0; end if; wait for k_PERIOD; end loop; wait; end process; -- *** End Test Bench - User Defined Section *** END; -------------- TIA for your comments. Elder.Article: 76756
Roy-be wrote: > > I recently joined a large company, and my first assignment while > familiarizing myself with our imaging algorithm entails drawing a very > rough floorplan of a design that ultimately will consist 3 modules of > code (code will also be designed by two other companies). The PCB will > then be re-laid out around the FPGA (definitely a board spin at this > point). > > I have only received projected estimates on resource usage from the two > other companies. I could probably convince them to shoot over more > info, but I am certain they aren't close to finished with the coding. > My team's code should eat approx. 30% of the resources on a Virtex-II > XC2V-6000. I can easily obtain the HDL for this section. > To be frank, it's been a while since I worked with FPGAs and from > toying around with ISE, I feel like I can only manipulate a floorplan > after place and route. However, this doesn't make any sense to me b/c I > feel floorplanning ideally should be performed during development. > > Would someone point me in the direction floorplanning w/o code? > Any feedback is appreciated. By floorplanning, do you mean picking a pinout? That should be relatively easy - in fact, using a Virtex-II or newer device, I'll bet there is a decent chance you could live with your current pinout(your first paragraph seems to imply that there is an existing PCB with the device in question on it), due to the incredible routing resources in the Virtex-II and newer devices. This is especially true if all three teams do a good job of pipelining their designs. Or... were you actually referring to making an educated guess where individual LUTs and FFs will go? Perhaps others would have a different take on it, but it seems to me that this would be quite a challenge without a high percent of the code completed, and I'm not sure what the quality of the floorplan would really be (ie, how close it would match what ends up going to production). Have fun, MarcArticle: 76757
Hi @ newsgroup, I have the following problem: Using a Cypress VHDL template for a 30bit adder I face the problem that I have to activate an internal pipeline stage within the template to get the performance I need. Using this pipeline stage the output of the adder is only valid every two clock cycles. So my question: Is it possible to split the addition into two adders and to combine the results that way so that I get a valid sum every clock cycle ? Any suggestion is highly appreciated. Thanks in advance. Rgds AndréArticle: 76758
On 9 Dec 2004 13:34:23 -0800, "Roy-be" <rplimpi@gmail.com> wrote: >I posted the jist of this on the Xilinx forums, but thought I might get >a quicker response through here... >________________________________ > >I recently joined a large company, and my first assignment while >familiarizing myself with our imaging algorithm entails drawing a very >rough floorplan of a design that ultimately will consist 3 modules of >code (code will also be designed by two other companies). Area constraints maybe? Allocate a suitably large (from best known information) rectangle to each module, and make "the module will fit within this allotted area, n * m slices" part of the module specification. If single rectangles don't work for you, then multiple rectangles may be used, BUT the tools seem best equipped to fit one rectangle per module, so allocate each new rectangle to one sub-module if oyu have tobreak up a module in this way. >I have only received projected estimates on resource usage from the two >other companies. I could probably convince them to shoot over more >info, but I am certain they aren't close to finished with the coding. >My team's code should eat approx. 30% of the resources on a Virtex-II >XC2V-6000. I can easily obtain the HDL for this section. Then you can try the area constraint approach with this section and see if it fits well within the estimated area and meets timing. >To be frank, it's been a while since I worked with FPGAs and from >toying around with ISE, I feel like I can only manipulate a floorplan >after place and route. However, this doesn't make any sense to me b/c I >feel floorplanning ideally should be performed during development. Floorplanning certainly works better after P&R, but you can draw area constraints and save them (as an UCF) earlier in the design. - BrianArticle: 76759
All Is it just me or does the whole world hate it when the defaults on a new release changes. ISE 6.3 now defaults all IO to lvcmos_25. I now have a whole host of vhdl that I maintain that will not just compile. If I need to make a trivial change then I have to check carefully. I can live with this today because I know that I need to do this. Next time though I may or may not remember this new setting and I will not remember whether the code has been modified to give me lvcmos33 (the old default). On a somewhat related subject I have fiddled with setting the iostandard in VHDL. There are examples of instantiating an IOB and then setting the IOB to whatever standard but what about a simple net out of the top level entity with IOB created by synthesis. I presume that this is trivial but I haven't been successfull. Can someone please help? ColinArticle: 76760
Hi, I've read that many of you have realized PCI card using FPGAs... I have to do something similar, but I hope simpler, for my thesis (I'm an university student): I have to realize a PCI core (but it should work as a target only device) that should transfer some data that is collected by the FPGA to an embedded processor, via the PCI bus... I "just" have to realize the PCI component for the FPGA as all the other stuff have already been done (and maybe connect the component to data acquisition logic) and the processor already has its own PCI controller (that acts as master and arbiter), so my question is: where should I start from? I've read part of the PCI Local Bus Specification but I have some doubts about the addressing differences..Article: 76761
"kender" <DL.kender@gmail.com> wrote in message news:7f3f5794.0412100621.5cddee46@posting.google.com... > Hi, I've read that many of you have realized PCI card using FPGAs... > I have to do something similar, but I hope simpler, for my thesis (I'm > an university student): I have to realize a PCI core (but it should > work as a target only device) that should transfer some data that is > collected by the FPGA to an embedded processor, via the PCI bus... > I "just" have to realize the PCI component for the FPGA as all the > other stuff have already been done (and maybe connect the component to > data acquisition logic) and the processor already has its own PCI > controller (that acts as master and arbiter), so my question is: where > should I start from? www.gaisler.com GRLIB there is vhdl PCI core that can be used for your purpose anttiArticle: 76762
i attended gospl forum recently. It was mentioned that Complete software toolset is open along with h/w architecture. All device information required for different software subsystems will be available. Architecture discussed resembles current FPGA architectural trend (4 input LUT based, symmetrical etc etc). It makes sense to start with familiar architecture as it will invite/benefit more people in open source. As architecture too is open to community for innovations, it will certainly make room for ideas which died in the lack of an opportunity. I think this is first of its kind and will finally give us an opportunity to work on fpga development. PantArticle: 76763
Antti Lukats wrote: > > I am trying to combine a 4 bit logic function and a 4-1 mux on the > > result. For example: > > > one word! think! > see below > > --------------------- > module lut_test(a,b,c,f); > input f; > input [3:0] a; > input [3:0] b; > output [3:0] c; > > wire [3:0] a; > wire [3:0] b; > wire f; > wire [1:0] s; > wire out; > wire [3:0] t; > > //assign t = f ? (a | b) : (a & b); > //assign c = t[s]; > assign c[0] = (f & (a[0] | b[0])) | (!f & (a[0] & b[0])); > assign c[1] = (f & (a[1] | b[1])) | (!f & (a[1] & b[1])); > assign c[2] = (f & (a[2] | b[2])) | (!f & (a[2] & b[2])); > assign c[3] = (f & (a[3] | b[3])) | (!f & (a[3] & b[3])); > > endmodule Your code doesn't include the 4-1 mux on the result. Without the mux, even my original code will fit in 4 LUT3's. The problem is XST doesn't see that the mux can be implemented using MUXF5/MUXF6 elements, and instead uses more LUTs.Article: 76764
Your main test process executes in zero sim time. Consider synchronizing the process as shown below. -- Mike Treseler --_______________________________________ library IEEE; use IEEE.STD_LOGIC_1164.all; entity sintab20 is port ( i_Clk : in std_logic; i_En : in std_logic; i_Addr : in integer range 0 to 19; o_DataOut : out std_logic_vector(17 downto 0) ); end sintab20; architecture Behavioral of sintab20 is subtype t_ROM_DATA is std_logic_vector(17 downto 0); type t_ROM_TYPE is array (natural range <>) of t_ROM_DATA; constant k_SinTab20x1 : t_ROM_TYPE(19 downto 0) := ( "000000000000000000", "001001111000110111", "010010110011110010", "011001111000110111", "011110011011110000", "011111111111111111", "011110011011110000", "011001111000110111", "010010110011110010", "001001111000110111", "000000000000000000", "110110000111001001", "101101001100001110", "100110000111001001", "100001100100010000", "100000000000000001", "100001100100010000", "100110000111001001", "101101001100001110", "110110000111001001" ); begin process (i_Clk) begin if rising_edge(i_Clk) then if (i_En = '1') then o_DataOut <= k_SinTab20x1(i_Addr); end if; end if; end process; end Behavioral; ---------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.all; entity sintab20_tb is end entity sintab20_tb; architecture sim of sintab20_tb is -- Fri Dec 10 10:34:08 2004 Mike -- component ports signal i_Clk_s : std_logic; -- [in] signal i_En_s : std_logic; -- [in] signal i_Addr_s : integer range 0 to 19; -- [in] signal o_DataOut_s : std_logic_vector(17 downto 0); -- [out] -- run with waves: -- vsim sintab20_tb -do "add wave -r /*;run -all;" signal done_s : boolean; signal clk_s : std_ulogic; signal rst_s : std_ulogic; begin -- architecture sim -- component instantiation DUT : entity work.sintab20 port map (i_Clk => i_Clk_s, -- [in] i_En => i_En_s, -- [in] i_Addr => i_Addr_s, -- [in] o_DataOut => o_DataOut_s); -- [out] i_clk_s <= clk_s; -- clock generation tb_clk : process is constant clk_cy : time := 20 ns; begin clk_s <= '0'; -- clk low during rst if now < clk_cy then rst_s <= '1'; -- rst high once else rst_s <= '0'; -- then low forever wait for clk_cy/2; -- clk low phase clk_s <= '1'; end if; if done_s then wait; end if; wait for clk_cy/2; -- clk or rst high phase end process tb_clk; main : process (clk_s, rst_s) is constant last_step_v : natural := 19; variable step_v : natural; begin clked : if rst_s = '1' then step_v := 1; elsif rising_edge(clk_s) then done_s <= step_v > last_step_v; i_Addr_s <= 0; enable : if not done_s then i_En_s <= '1'; i_Addr_s <= step_v - 1; step_v := step_v + 1; -- step counter end if enable; end if clked; end process main; end architecture sim;Article: 76765
<usenet+5@ladybug.xs4all.nl> wrote in message
news:1102703845.265774.254200@f14g2000cwb.googlegroups.com...
> Antti Lukats wrote:
>
> > > I am trying to combine a 4 bit logic function and a 4-1 mux on the
> > > result. For example:
> > >
>
> > one word! think!
> > see below
[]
> Your code doesn't include the 4-1 mux on the result. Without the mux,
> even my original code will fit in 4 LUT3's. The problem is XST doesn't
> see that the mux can be implemented using MUXF5/MUXF6 elements, and
> instead uses more LUTs.
uups! you right I simplified your code and removed the mux :(
well your code as posted does get
Cell Usage :
# BELS : 7
# LUT3 : 6
# MUXF5 : 1
hmm.. but this is what I would expect it to be?
enterig think mode again...
-----------------------------------------------
module lut_test2(a,b,c,f,s);
input f;
input [1:0] s;
input [3:0] a;
input [3:0] b;
output c;
wire [3:0] a;
wire [3:0] b;
wire f;
wire [1:0] s;
wire [1:0] x;
wire out;
wire [3:0] t;
//assign t = f ? (a | b) : (a & b);
//assign c = t[s];
assign t[0] = ((f & (a[0] | b[0])) | (!f & (a[0] & b[0]))) & s[0];
assign t[1] = ((f & (a[1] | b[1])) | (!f & (a[1] & b[1]))) & !s[0];
assign t[2] = ((f & (a[2] | b[2])) | (!f & (a[2] & b[2]))) & s[0];
assign t[3] = ((f & (a[3] | b[3])) | (!f & (a[3] & b[3]))) & !s[0];
assign c = s[1] ? (t[3] | t[2]) : (t[1] | t[0]);
endmodule
-------------------------------------
the above is functionally same as yours?
Cell Usage :
# BELS : 6
# LUT4 : 5
# MUXF5 : 1
5 LUTs and 1 MUXF5 is better already :)
antti
Article: 76766ALuPin wrote: > Using a Cypress VHDL template for a 30bit adder I face the problem > that I have to activate an internal pipeline stage within the template > to get the performance I need. > Using this pipeline stage the output of the adder is only valid > every two clock cycles. > Is it possible to split the addition into two adders and to > combine the results that way so that I get a valid sum every > clock cycle ? You mean the carry delay is too long? Split it into two adders, maybe 16 and 14 or 15 and 15, and pipeline the carry between them. The two will then be one pipeline stage apart, which may complicate the rest of the pipeline. Not knowing what the rest of your logic looks like, you might look into carry save adders. When adding more than two numbers, a carry save adder pipeline saves the carry propagation until the last step. Though I would expect a pipelined template adder to be fully pipelined, such that you would get a new result out every cycle, though delayed the appropriate number of cycles. At each clock cycle you put in A(t) and B(t) and get out sum(t-2) or sum(t-3). -- glenArticle: 76767
Elder Costa wrote: > I am using Xilinx ISE Foundation 6.3i. I am trying to implement a sine > lookup table (targeted at either SpartanIII or VirtexII) but I am > getting a strange result when running functional simulation (testbench > bellow) with Modelsim: instead of showing the first element from the > array on the output after the first rising edge it shows the 12th. > Everithing happens as if I had initialized the address counter with 11 > instead of 0. I know I am making a basic mistake but I cannot figure > out where or why. I don't see anything, but maybe someone else will. It would be more usual to make the number of table entries a power of two, such that mod 360 degrees could be done by ignoring high order bits. You might see if that works better in your case. Display both the address and table value. That should help track down the problem. -- glenArticle: 76768
"Artenz" <usenet+5@ladybug.xs4all.nl> wrote in message
news:80a355e0.0412091330.49973f14@posting.google.com...
> I am trying to combine a 4 bit logic function and a 4-1 mux on the
> result. For example:
>
> wire [3:0] a;
> wire [3:0] b;
> wire f;
> wire [1:0] s;
> wire out;
> wire [3:0] t;
>
> assign t = f ? (a | b) : (a & b);
> assign out = t[s];
>
> Where a and b are 4 bit inputs, f selects a function on them, and t[s]
> selects one of the 4 result bits.
>
> Looking at the CLB diagram, I was thinking this would fit in 4 LUTs
> for the logic, followed by a MUXF5 and a MUXF6 for the selection.
it does, see below:
----------------
module lut_mux(a,b,c,f,s);
input f;
input [1:0] s;
input [3:0] a;
input [3:0] b;
output c;
wire [3:0] a;
wire [3:0] b;
wire f;
wire [1:0] s;
wire [1:0] x;
wire out;
wire [3:0] t;
assign t[0] = (f & (a[0] | b[0])) | (!f & (a[0] & b[0]));
assign t[1] = (f & (a[1] | b[1])) | (!f & (a[1] & b[1]));
assign t[2] = (f & (a[2] | b[2])) | (!f & (a[2] & b[2]));
assign t[3] = (f & (a[3] | b[3])) | (!f & (a[3] & b[3]));
MUXF5 XLXI_1a (.I0(t[0]), .I1(t[1]), .S(s[0]), .O(x[0]));
MUXF5 XLXI_1b (.I0(t[3]), .I1(t[2]), .S(s[0]), .O(x[1]));
MUXF6 XLXI_2 (.I0(x[0]), .I1(x[1]), .S(s[1]), .O(c));
endmodule
----------------
Cell Usage :
# BELS : 7
# LUT3 : 4
# MUXF5 : 2
# MUXF6 : 1
=========================================================================
Device utilization summary:
---------------------------
Selected Device : 3s1000ft256-4
Number of Slices: 2 out of 7680 0%
:)
hm.. the F5/F6 muxed versions seems to be both smaller and faster, but no
matter the synthesis options XST refuses to use that solution, unless the
F5/F6 muxes are directly instantiated!
good thing to know!
Antti
Article: 76769Kim Enkovaara wrote: > > rickman wrote: > > > Mentor, are you *ever* going to fix the bug where Modelsim crashes > > randomly for no special reason???) I dont' see open source tools fixing > > any of this. The current open source front end tools are still far > > You need a testcase, fixing a bug where the description is "it crashes > sometimes" is impossible. Yes, Modelsim has bugs, but every one of the > ones I have found have been fixed in a reasonable time (usually > optimisation bugs). They have even added some optimisations for new classes > of structures just by asking and providing a good testcase. > > It should not be impossible to do a testcase. I have done some testcases > even from 5+M gate designs where something is wrong in the SDF timing > model. Those are really hard bugs to debug. For example no testbench is > needed for a testcase, just use "vcd dumpports" functionality. There > are also engineering builds of Modelsim that can be used to debug the > crashes. > > I have not seen any random crashes and I use Modelsim in quite a big > cluster for regression runs etc. And have been using M for many years. > One place where modelsim at least had problems was restart command. > After many restarts when the design structure changes enough it at least > crashed in the past. Also if wave window was used heavily during > simulation in versions <5.7 it quite often crashed. > > But I have had similiar experiences with other simulators. Some of them are > even more crash prone. But they usually crash during the compilation > already :) Nothing is perfect. You make a number of assumptions. As I said in one of my other posts, my experience is that it has no correlation to anything, including the files, the machine, the operator, the version of the software, the time of day... EXCEPT that it crashes when I start a simulation run following a recompile of some of the files I am working with. If Mentor wants to put me on their payroll to debug their software, I would be happy to work on it all day. But please don't tell me that *I* need to give them a test case. I would be willing to bet it is a memory leak in the GUI or the Tcl scripter. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 76770
On Fri, 10 Dec 2004 21:47:44 +0100, Antti Lukats wrote:
>
> "Artenz" <usenet+5@ladybug.xs4all.nl> wrote in message
> news:80a355e0.0412091330.49973f14@posting.google.com...
>> I am trying to combine a 4 bit logic function and a 4-1 mux on the
>> result. For example:
> it does, see below:
> ----------------
> module lut_mux(a,b,c,f,s);
> input f;
> input [1:0] s;
> input [3:0] a;
> input [3:0] b;
> output c;
>
> wire [3:0] a;
> wire [3:0] b;
> wire f;
> wire [1:0] s;
> wire [1:0] x;
>
> wire out;
> wire [3:0] t;
>
> assign t[0] = (f & (a[0] | b[0])) | (!f & (a[0] & b[0]));
> assign t[1] = (f & (a[1] | b[1])) | (!f & (a[1] & b[1]));
> assign t[2] = (f & (a[2] | b[2])) | (!f & (a[2] & b[2]));
> assign t[3] = (f & (a[3] | b[3])) | (!f & (a[3] & b[3]));
>
> MUXF5 XLXI_1a (.I0(t[0]), .I1(t[1]), .S(s[0]), .O(x[0]));
> MUXF5 XLXI_1b (.I0(t[3]), .I1(t[2]), .S(s[0]), .O(x[1]));
> MUXF6 XLXI_2 (.I0(x[0]), .I1(x[1]), .S(s[1]), .O(c));
>
> endmodule
> ----------------
> Cell Usage :
> # BELS : 7
> # LUT3 : 4
> # MUXF5 : 2
> # MUXF6 : 1
> hm.. the F5/F6 muxed versions seems to be both smaller and faster, but
> no matter the synthesis options XST refuses to use that solution, unless
> the F5/F6 muxes are directly instantiated!
Thanks!
You can also do even more complicated things and have it fit in the
same 4 LUTs, and even make it a little bit more readable.
module lut_test( a, b, c, f, s );
input [3:0] a, b;
input [1:0] s;
input [1:0] f;
output c;
wire [3:0] t;
wire x0, x1;
wire [3:0] m0 = (f == 0) ? ~0 : 0;
wire [3:0] m1 = (f == 1) ? ~0 : 0;
wire [3:0] m2 = (f == 2) ? ~0 : 0;
wire [3:0] m3 = (f == 3) ? ~0 : 0;
assign t = (m0 & (a & b)) |
(m1 & (a | b)) |
(m2 & (a ^ b)) |
(m3 & (a & ~b));
MUXF5 m_1a( .I0(t[0]), .I1(t[1]), .S(s[0]), .O(x0) );
MUXF5 m_1b( .I0(t[2]), .I1(t[3]), .S(s[0]), .O(x1) );
MUXF6 m_2 ( .I0(x0), .I1(x1), .S(s[1]), .O(c) );
endmodule
However, if you try to write vector 't' above with a case or if-else
(which I had tried before), then you get 4 more LUT1s. Apparently you
have to spell things out really carefully for XST to have it find the
optimal solution, especially if you want the MUXF6 in there. Which is too
bad, because it tends to make the code much harder to read.
Article: 76771glen herrmannsfeldt wrote: > I don't see anything, but maybe someone else will. It turned out it *was* a basic mistake. I should have declared constant k_SinTab20x1: t_ROM_TYPE(0 to 19) instead of constant k_SinTab20x1: t_ROM_TYPE(19 downto 0) So I was starting with 20th element, not 12th. > > It would be more usual to make the number of table entries a power > of two, such that mod 360 degrees could be done by ignoring high > order bits. You might see if that works better in your case. It is not possible in my application, a lock in demodulator at 2.5Msps using a 125KHz carrier. Thanks and regards.Article: 76772
Mike Treseler wrote: > Your main test process executes in zero sim time. > Consider synchronizing the process as shown below. I figured out the problem as I pointed in another message. I will save your message though as reference as it does contain some stuff I think will help me. Thanks and regads. Elder.Article: 76773
Annti,
Your correct this can be done. But your coding style isn't exactly conducive
to the synthesis of a mux. Case statements are the preferred coding style if
you want the MUXF5/MUXF6/MUXF# resources to be used. The dedicated
muxes also roughly correlate to a particular width MUXF5 == 4:1,
MUXF6 == 8:1. etc.
So if you want to get a MUXF6, at three bit case statement is appropriate:
module lut_test2(a,b,c,f,s);
input f;
input [1:0] s;
input [3:0] a;
input [3:0] b;
output c;
//Implicit wires exist
//wire [3:0] a;
//wire [3:0] b;
//wire f;
//wire [1:0] s;
reg caseout;
//wire [2:0] sel = {s,f};
always @(s or f or a or b)
case ({s,f})
//f is 0
3'b000 : caseout = (a[0] & b[0]);
3'b010 : caseout = (a[1] & b[1]);
3'b100 : caseout = (a[2] & b[2]);
3'b110 : caseout = (a[3] & b[3]);
//f is 1
3'b001 : caseout = (a[0] | b[0]);
3'b011 : caseout = (a[1] | b[1]);
3'b101 : caseout = (a[2] | b[2]);
3'b111 : caseout = (a[3] | b[3]);
endcase
assign c = caseout;
endmodule
Note: This was targeted to V-II, but that shouldn't affect the results.
=========================================================================
Macro Statistics :
# Multiplexers : 1
# 1-bit 8-to-1 multiplexer : 1
Cell Usage :
# BELS : 7
# LUT3 : 4
# MUXF5 : 2
# MUXF6 : 1
# IO Buffers : 12
# IBUF : 11
# OBUF : 1
=========================================================================
Because the particular configuration you are looking for requires
that the f input be a "select" in the fist stage (LUT) as opposed to
a MUXF5/MUXF6 select, the order of the select bits in the
case statement does matter.
Additionally, there are some connectivity restrictions for MUXF#,
but I see you already worked that out.
Chris
Antti Lukats wrote:
> "Artenz" <usenet+5@ladybug.xs4all.nl> wrote in message
> news:80a355e0.0412091330.49973f14@posting.google.com...
> > I am trying to combine a 4 bit logic function and a 4-1 mux on the
> > result. For example:
> >
> > wire [3:0] a;
> > wire [3:0] b;
> > wire f;
> > wire [1:0] s;
> > wire out;
> > wire [3:0] t;
> >
> > assign t = f ? (a | b) : (a & b);
> > assign out = t[s];
> >
> > Where a and b are 4 bit inputs, f selects a function on them, and t[s]
> > selects one of the 4 result bits.
> >
> > Looking at the CLB diagram, I was thinking this would fit in 4 LUTs
> > for the logic, followed by a MUXF5 and a MUXF6 for the selection.
> it does, see below:
> ----------------
> module lut_mux(a,b,c,f,s);
> input f;
> input [1:0] s;
> input [3:0] a;
> input [3:0] b;
> output c;
>
> wire [3:0] a;
> wire [3:0] b;
> wire f;
> wire [1:0] s;
> wire [1:0] x;
>
> wire out;
> wire [3:0] t;
>
> assign t[0] = (f & (a[0] | b[0])) | (!f & (a[0] & b[0]));
> assign t[1] = (f & (a[1] | b[1])) | (!f & (a[1] & b[1]));
> assign t[2] = (f & (a[2] | b[2])) | (!f & (a[2] & b[2]));
> assign t[3] = (f & (a[3] | b[3])) | (!f & (a[3] & b[3]));
>
> MUXF5 XLXI_1a (.I0(t[0]), .I1(t[1]), .S(s[0]), .O(x[0]));
> MUXF5 XLXI_1b (.I0(t[3]), .I1(t[2]), .S(s[0]), .O(x[1]));
> MUXF6 XLXI_2 (.I0(x[0]), .I1(x[1]), .S(s[1]), .O(c));
>
> endmodule
> ----------------
> Cell Usage :
> # BELS : 7
> # LUT3 : 4
> # MUXF5 : 2
> # MUXF6 : 1
> =========================================================================
> Device utilization summary:
> ---------------------------
> Selected Device : 3s1000ft256-4
> Number of Slices: 2 out of 7680 0%
> :)
>
> hm.. the F5/F6 muxed versions seems to be both smaller and faster, but no
> matter the synthesis options XST refuses to use that solution, unless the
> F5/F6 muxes are directly instantiated!
>
> good thing to know!
>
> Antti
Article: 76774On 9 Dec 2004 16:18:39 -0800, "Kevin Brown" <kbrown_home@hotmail.com> wrote: >In the extreme DSP slice there are two registers before the >multiplication on each of the A and B inputs. Does anyone know why you >would need 2 registers before the multiplication? > >At first I thought it may be a register similar to the one in a >MULT18x18s, but changing the number of registers on A and B from 1 to 2 >had no effect on timing. Also it wouldn't make sense since A and B are >individually selectable to have 0,1, or 2 registers. > >-Kevin If you are doing larger multiplies (36x18, 36x36) you may need to delay partial operands so that all the pieces arrive at the destination at the same time. For IIR filters, you may not be able to tollerate multiple pipe stages, so that may be a use for the "0 registers" Philip Freidin Fliptronics
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