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Daniel wrote:
> I compile it with a slight change the something else does not work
> properly. Conseqently I have no faith in AHDL file at all. The
> schematic still works fine without the uart. Has anybody else come
> accross this and do they have any solutions for the problem.
Yes. Synchronous design and simulation before synthesis.
> Is it a
> common consencuse that schematic is not the method that should be used
> and AHDL or VHDl is the only reliable way to program these? I are
> using quartus 4.2 sp2 WE and flex6000 device.
The schematic is not the main problem,
it is logical and synchronization errors.
You can fix unsynchronized inputs manually.
From a schematic/AHDL source, Quartus can make a .vho netlist.
You can then write a VHDL simulation testbench using modelsim,
to find and fix the logical errors.
-- Mike Treseler
>
> Daniel
Article: 76801Jim George wrote: > Hello, > I wanted to know how you instruct MAP to place an LUT and a MUXF5 > into the same slice. Looking at the V2 Datasheet, it seems to be an > allowed combination. However, I get a MAP error stating that the LUT and > MUXF5 cannot share the same slice. I'm specifiying the constraints > within the VHDL (again, inspired by Ray Andraka). > Thanks! > -Jim Hi Jim, Without knowing what the error is, it's difficult to comment. It sounds as if you've successfully specified the constraints, but the packer is rejecting the constraints for some reason. If the MAP error begins with "ERROR:Pack:679" then that's the case. The first line in the error message identifies the failing constraint. This is followed by a list of symbols involved. The last line indicates the reason for the failure and this is what you should focus on. Some times there is a connectivity restriction involved that is not obvious until you become very familiar with the possible slice configurations. Try using the Logic Block Editor inside FPGA Editor to assemble a slice equivalent to your logic. The restriction should become apparent then. Another possibility is that it is possible to pack the logic into one slice, but the packer isn't getting it right. In that case, it might help to use BEL constraints to be more specific about how the slice should be assembled. Possible values are F, G, CYMUXF, CYMUXG, XORF, XORG, FFX, FFY. BretArticle: 76802
Adam wrote: > I'm trying to build an SPDIF receiver and am wondering if its possible to > directly connect the input signal(after analog level adjustment) to an FPGA > and read the level at the 90 and 270 degree phases. SPDIF is only 48kHz * 32 bits * 2 channels * 2 for biphase = 6MHz Any modern FPGA will do 100MHz easy. So just oversample the signal and decode it like a UART would. To build a transmitter locked to the receiver would be more difficult. Alan Nishioka alann@accom.comArticle: 76803
Bret Wade wrote:
> Jim George wrote:
>
>> Hello,
>> I wanted to know how you instruct MAP to place an LUT and a MUXF5
>> into the same slice. Looking at the V2 Datasheet, it seems to be an
>> allowed combination. However, I get a MAP error stating that the LUT
>> and MUXF5 cannot share the same slice. I'm specifiying the constraints
>> within the VHDL (again, inspired by Ray Andraka).
>> Thanks!
>> -Jim
>
>
> Hi Jim,
>
> Without knowing what the error is, it's difficult to comment. It sounds
> as if you've successfully specified the constraints, but the packer is
> rejecting the constraints for some reason. If the MAP error begins with
> "ERROR:Pack:679" then that's the case. The first line in the error
> message identifies the failing constraint. This is followed by a list of
> symbols involved. The last line indicates the reason for the failure and
> this is what you should focus on.
>
> Some times there is a connectivity restriction involved that is not
> obvious until you become very familiar with the possible slice
> configurations. Try using the Logic Block Editor inside FPGA Editor to
> assemble a slice equivalent to your logic. The restriction should become
> apparent then.
>
> Another possibility is that it is possible to pack the logic into one
> slice, but the packer isn't getting it right. In that case, it might
> help to use BEL constraints to be more specific about how the slice
> should be assembled. Possible values are F, G, CYMUXF, CYMUXG, XORF,
> XORG, FFX, FFY.
>
> Bret
>
Thanks for the quick reply. OK, I was in the tearing-out-hair stage when
I last posted, here's what it should have said: I'm trying to pack in an
SRL16 and a LUT into the same slice, then use a MUXF5 on the output of
the two. Is this allowed? I've written some example code similar to the
one which caused the problem:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity example is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
clk : in std_logic;
sel : in std_logic;
y : out std_logic);
end example;
architecture Behavioral of example is
attribute RLOC: string;
attribute U_SET: string;
signal internal_1, internal_2 : std_logic;
signal len : std_logic_vector(3 downto 0);
attribute RLOC of the_lut: label is "X0" & "Y0";
attribute U_SET of the_lut: label is "set";
attribute RLOC of the_srl: label is "X0" & "Y0";
attribute U_SET of the_srl: label is "set";
attribute RLOC of the_muxf5: label is "X0" & "Y0";
attribute U_SET of the_muxf5: label is "set";
begin
len <= "1110";
the_lut: lut2_l
generic map (init => X"8")
port map (
i0 => a,
i1 => b,
lo => internal_1
);
the_srl: SRL16
port map (
q => internal_2,
a0 => len(0),
a1 => len(1),
a2 => len(2),
a3 => len(3),
clk => clk,
d => c
);
the_muxf5: MUXF5
port map (
i0 => internal_1,
i1 => internal_2,
o => y,
s => sel
);
end Behavioral;
The exact error from MAP is:
ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=set,
RLOC=X0Y0) which require the combination of the following symbols into a
single SLICE component:
Shift symbol "the_srl/SRL16E" (Output Signal = internal_2)
LUT symbol "the_lut" (Output Signal = the_lut/O)
MUXF5 symbol "the_muxf5" (Output Signal = y_OBUF)
The function generator the_srl/SRL16E is unable to be placed in the
G position because the output signal doesn't match other symbols' use of
the G signal. The signal the_lut/O already uses G. Please correct the
design constraints accordingly.
I'm sure I'm doing something really dumb here... but will using BEL
help fix this? Oh, and I'm using WebPack, so I dont have FPGA Editor.
Thank you.
-Jim
Article: 76804HI, I think I have found the problem. The board supports dynamic config FPGA via PCI I/F. Since software set FPGA's user reset to active before re-config FPGA, the DDR chip will not become error again. reset it, before re-config it. is this a rule for XILINX? regards, seyiorArticle: 76805
Jim George wrote:
> Thanks for the quick reply. OK, I was in the tearing-out-hair stage when
> I last posted, here's what it should have said: I'm trying to pack in an
> SRL16 and a LUT into the same slice, then use a MUXF5 on the output of
> the two. Is this allowed? I've written some example code similar to the
> one which caused the problem:
>
> library IEEE;
> use IEEE.STD_LOGIC_1164.ALL;
> use IEEE.STD_LOGIC_ARITH.ALL;
> use IEEE.STD_LOGIC_UNSIGNED.ALL;
> library UNISIM;
> use UNISIM.VComponents.all;
> entity example is
> Port ( a : in std_logic;
> b : in std_logic;
> c : in std_logic;
> clk : in std_logic;
> sel : in std_logic;
> y : out std_logic);
> end example;
> architecture Behavioral of example is
> attribute RLOC: string;
> attribute U_SET: string;
> signal internal_1, internal_2 : std_logic;
> signal len : std_logic_vector(3 downto 0);
> attribute RLOC of the_lut: label is "X0" & "Y0";
> attribute U_SET of the_lut: label is "set";
> attribute RLOC of the_srl: label is "X0" & "Y0";
> attribute U_SET of the_srl: label is "set";
> attribute RLOC of the_muxf5: label is "X0" & "Y0";
> attribute U_SET of the_muxf5: label is "set";
> begin
> len <= "1110";
> the_lut: lut2_l
> generic map (init => X"8")
> port map (
> i0 => a,
> i1 => b,
> lo => internal_1
> );
> the_srl: SRL16
> port map (
> q => internal_2,
> a0 => len(0),
> a1 => len(1),
> a2 => len(2),
> a3 => len(3),
> clk => clk,
> d => c
> );
> the_muxf5: MUXF5
> port map (
> i0 => internal_1,
> i1 => internal_2,
> o => y,
> s => sel
> );
> end Behavioral;
>
> The exact error from MAP is:
>
> ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=set,
> RLOC=X0Y0) which require the combination of the following symbols into a
> single SLICE component:
> Shift symbol "the_srl/SRL16E" (Output Signal = internal_2)
> LUT symbol "the_lut" (Output Signal = the_lut/O)
> MUXF5 symbol "the_muxf5" (Output Signal = y_OBUF)
> The function generator the_srl/SRL16E is unable to be placed in the G
> position because the output signal doesn't match other symbols' use of
> the G signal. The signal the_lut/O already uses G. Please correct the
> design constraints accordingly.
>
> I'm sure I'm doing something really dumb here... but will using BEL
> help fix this? Oh, and I'm using WebPack, so I dont have FPGA Editor.
> Thank you.
> -Jim
Hi Jim,
There is a connectivity problem that can be easily corrected. The SRL16
needs to be in the G-LUT. Since the connection from the G-LUT to the
MUXF5 uses the I0 input in the hardware, your code needs to do the same,
but you have the SRL16 driving the I1 input of the MUXF5. The code works
okay if I swap the MUXF5 inputs to match the hardware:
the_muxf5: MUXF5
port map (
i0 => internal_2,
i1 => internal_1,
o => y,
s => sel
);
Number of occupied Slices: 1 out of 256 1%
Regards,
Bret
Article: 76806Hello: If you inferr a ram from a synthesis tool it always be done using slices configured as RAM, to use block RAM in a Xilinx FPGA you must generate it using Coregen and adding the .xco file to your project in ISE. Regards Javier Castillo jcastillo@opensocdesign.com www.opensocdesign.com Elder Costa <elder.costa@terra.com.br> wrote in news:31umvgF3h46qjU1 @individual.net: > Hello folks. > > I have implemented the entity bellow by instantciating a dual ported > block RAM with different bus widths (RAMB16_S18_S36 - I am developing > for Virtex II or Spartan 3). Whereas it is relatively simple to do it by > instantiacing the component from Xilinx library, I wonder if there is a > way to code the module so that Xst infers the block RAM. I tried in one > or two ways but it used logic in slices instead of BRAM and it required > a lot of logic for a 1kib RAM. Could somebody give a hint on this? I > looked at Xilinx documentation and couldn't find an example for this > particular problem. > > entity gaintab is > Port ( > -- ports de acesso do processador > i_ProcAddr : in std_logic_vector(9 downto 0); > i_ProcDataIn : in std_logic_vector(15 downto 0); > i_ProcWr : in std_logic; > i_ProcEn : in std_logic; > i_ProcClk : in std_logic; > o_ProcDataOut : out std_logic_vector(15 downto 0); > -- ports de acesso interno (fpga) > i_FpgaAddr : in std_logic_vector(6 downto 0); > i_FpgaClk : in std_logic; > o_FpgaDataOut : out std_logic_vector(31 downto 0) > ); > end gaintab; > > > TIA. > > Elder. >Article: 76807
Hello: At www.opencores.org you can find many uarts, for a very simple UART I recommend you to use the miniUART project, if you need a complete 16650 UART use UART16550 project. Best Regards Javier Castillo jcastillo@opensocdesign.com www.opensocdesign.com "Konstantin Dols" <Konstantin.Dols@rwth-aachen.de> wrote in news:opsiv94toznxvpac@pc113: > > > Greetings ! > > I'm looking for a simple RS232 UART16550 receiver for my tiny cyclone > board for different baudrates, 8databits, 1stop&startbit and no(!) > partity and handshake stuff. > > I found several free VHDL implementations in the net but compared to > what I need > they are to complicated and appear like shooting with missiles on > birds ;-) > > > > The entity might have a simple structure like this: > > entity receiver is > generic( frequency : integer := 10000000; -- e.g. for > 10MHz > baudrate : integer := 9600 -- e.g. for > 9600bps > ); > > port( clk : in std_logic; -- clockspeed is > 'frequency' > reset : in std_logic; -- resets the receiver > receiver : in std_logic; -- input from receive pin > from RS232 connector > > char_avail : out std_logic; -- indicated that a > valid char has beed > received > char : out std_logic_vector(7 downto 0) -- received > char, only > available for one clock > ); > end receiver; > > The 'reciever' values are 'active high'... > > This structure gives the responsibility for catching received data in > time to the user > but surely allowes adding a FIFO. > > > Probably this question has been asked about 47283407239 times in this > group so please just send me a usefull link or code snippet... > > > Konstantin >Article: 76808
Quite a simple question: how to simulate the DDR-SDRAM core from Altera in NCSim. I just can 't figure it out though Altera *claims* to support NCSim. To me it looks like their development chain is realy ModelSim/Quartus only... The things I've tried: * simulate netlist from core (yes I've got a license) : doesnt' work due to errors when trying to compile the thing. * dump a "functional description" of the core: works but I'm missing some important functionality like burst length settings and so on. The IP generation tool doesn't seem to work in Linux so it's switching back and forth to Windows when I want to change something in the core. Anyone a sollution? To Altera: lovely FPGA's but quite crapy software (did I mention how many times Quartus crashes in Windows?). Sorry to say that. JanArticle: 76809
Hi Jan,
We are sorry to hear that the Quartus software crashed on Windows for
you. We are definitely interested in understanding this fully and resolving
the matter for you. The stability of the Quartus software on all supported
platforms is very good, based on customer feedback which we monitor very
closely. If there are specific Internal Error messages or sequences of steps
that causedQuartusto crash, do email them to me and I will follow up with
you by mail.
I will send you a separate reply on the DDR core simulation and Linux
questions.
Hope this helps.
- Subroto Datta
Altera Corp.
"Jan De Ceuster" <jandc@elis.ugent.be> wrote in message
news:cpk2a2$6ns$1@gaudi2.UGent.be...
> Quite a simple question: how to simulate the DDR-SDRAM core from Altera in
> NCSim. I just can 't figure it out though Altera *claims* to support
> NCSim. To me it looks like their development chain is realy
> ModelSim/Quartus only...
>
> The things I've tried:
> * simulate netlist from core (yes I've got a license) : doesnt' work due
> to errors when trying to compile the thing.
> * dump a "functional description" of the core: works but I'm missing some
> important functionality like burst length settings and so on. The IP
> generation tool doesn't seem to work in Linux so it's switching back and
> forth to Windows when I want to change something in the core.
>
> Anyone a sollution?
> To Altera: lovely FPGA's but quite crapy software (did I mention how many
> times Quartus crashes in Windows?). Sorry to say that.
>
> Jan
Article: 76810
Javier Castillo wrote:
> If you inferr a ram from a synthesis tool it always be done using
> slices configured as RAM, to use block RAM in a Xilinx FPGA you must
> generate it using Coregen and adding the .xco file to your project in
> ISE.
Block RAM can be inferred by synthesis tools.
Dual port ram with one read and one write port
can be inferred by synthesis tools.
True dual port RAM with two read/write ports
requires a device-specific instance.
-- Mike Treseler
Article: 76811
Jan De Ceuster wrote:
> * simulate netlist from core (yes I've got a license) : doesnt' work due
> to errors when trying to compile the thing.
Consider posting the first few error messages.
-- Mike Treseler
Article: 76812
>> * simulate netlist from core (yes I've got a license) : doesnt' work
>> due to errors when trying to compile the thing.
>
>
> Consider posting the first few error messages.
Yeah I know, I should give more information though no workarounds possbile
(besides of editing the code) I think.
here it is:
ncvhdl: 05.00-p001: (c) Copyright 1995-2003 Cadence Design Systems, Inc.
SIGNAL ww_\g_local_buffered_if:wdata_fifo\_data : std_logic_vector(29 DOWNTO 0);
|
ncvhdl_p: *E,NOTRUS (ddr_test.vho,16316|9): illegal trailing underline [13.3].
SIGNAL ww_\g_local_buffered_if:wdata_fifo\_data : std_logic_vector(29 DOWNTO 0);
|
ncvhdl_p: *E,MISCOL (ddr_test.vho,16316|10): expecting a colon (':') 93[4.3.1.2].
SIGNAL ww_\g_local_buffered_if:wdata_fifo\_data : std_logic_vector(29 DOWNTO 0);
|
ncvhdl_p: *E,NOLDUS (ddr_test.vho,16316|42): illegal leading underline [13.3].
SIGNAL ww_\g_local_buffered_if:wdata_fifo\_q : std_logic_vector(29 DOWNTO 0);
Synopsys DC gives the same error (mind that the 'arrow' points at the first
backslash):
SIGNAL ww_\g_local_buffered_if:wdata_fifo\_data : std_logic_vector(29 DOWNTO 0);
^
**Error: /home/jandc/test/test_netlist/ddr_test.vho line 16316
Invalid delimiter character: `\'. (VSS-965)
I think that the _\ construction is illegal but to be honnest: I've no desire to
dig in the vhdl reference to see who is right, Cadence and Synopsys versus Altera.
Article: 76813Konstantin Dols wrote: > > > Greetings ! > > I'm looking for a simple RS232 UART16550 receiver for my tiny cyclone board > for different baudrates, 8databits, 1stop&startbit and no(!) partity > and handshake stuff. > > I found several free VHDL implementations in the net but compared to > what I need > they are to complicated and appear like shooting with missiles on birds ;-) > > > Konstantin > I am currently working on an implementation of such a controller for my semester project. So I will let you have a look to my code when I have finished it. Greetz :) Grégory Mermoud gregory.mermoud@epfl.ch Swiss Federal Institute of Technology - Lausanne Computer Science DepartementArticle: 76814
Hi,
in the attachement you'll find something you could use. I've used it on a
cyclone to do some ASCII communication (giving commands and sending/receiving
data to/from the system). I'm just in the middle of updating the things so it's
possible you have to mess around with some libs (or change the libs to 'work').
I've added some functions to convert a 4 bit hex 'string' into a 7 bit char 'string.
kind regards,
Jan
Konstantin Dols wrote:
>
>
> Greetings !
>
> I'm looking for a simple RS232 UART16550 receiver for my tiny cyclone board
> for different baudrates, 8databits, 1stop&startbit and no(!) partity
> and handshake stuff.
>
> I found several free VHDL implementations in the net but compared to
> what I need
> they are to complicated and appear like shooting with missiles on birds ;-)
>
>
>
> The entity might have a simple structure like this:
>
> entity receiver is
> generic( frequency : integer := 10000000; -- e.g. for 10MHz
> baudrate : integer := 9600 -- e.g. for 9600bps
> );
>
> port( clk : in std_logic; -- clockspeed is 'frequency'
> reset : in std_logic; -- resets the receiver
> receiver : in std_logic; -- input from receive pin from
> RS232 connector
>
> char_avail : out std_logic; -- indicated that a valid char
> has beed received
> char : out std_logic_vector(7 downto 0) -- received char,
> only available for one clock
> );
> end receiver;
>
> The 'reciever' values are 'active high'...
>
> This structure gives the responsibility for catching received data in
> time to the user
> but surely allowes adding a FIFO.
>
>
> Probably this question has been asked about 47283407239 times in this group
> so please just send me a usefull link or code snippet...
>
>
> Konstantin
>
>>>>>>>>>>>>>>>>>>>>>>>>>>>>> filename="Buffer_procedures.vhd"
--
-- ***Author***
-- Jan De Ceuster
--
-- *** File ***
-- Buffer_procedures.vhd
--
-- *** Procedures ***
--
-- *** Functions ***
--
-- *** Description ***
--
-- *** History ***
-- 001 initial
library ieee;
use ieee.std_logic_1164.all;
package Buffer_procedures is
procedure ShiftL2H_p(input : in std_logic;
shiftvector_in : in std_logic_vector;
signal shiftvector_out : out std_logic_vector);
procedure ShiftL2H_p(input : in std_logic;
signal shiftvector : inout std_logic_vector);
function ShiftL2H_f(input : in std_logic;
shiftvector_in : in std_logic_vector)
return std_logic_vector;
end package;
package body Buffer_procedures is
procedure ShiftL2H_p(input : in std_logic;
shiftvector_in : in std_logic_vector;
signal shiftvector_out : out std_logic_vector) is
begin
shiftvector_out(shiftvector_out'low) <= input;
-- always shift from low towards high
if shiftvector_out'high = shiftvector_out'right then
shiftvector_out(shiftvector_out'low+1 to shiftvector_out'high)
<= shiftvector_in(shiftvector_in'low to shiftvector_in'high-1);
else
shiftvector_out(shiftvector_out'high downto shiftvector_out'low+1)
<= shiftvector_in(shiftvector_in'high-1 downto shiftvector_in'low);
end if;
end procedure;
procedure ShiftL2H_p(input : in std_logic;
signal shiftvector : inout std_logic_vector) is
begin
shiftvector(shiftvector'low) <= input;
if shiftvector'high = shiftvector'right then
shiftvector(shiftvector'low+1 to shiftvector'high)
<= shiftvector(shiftvector'low to shiftvector'high-1);
else
shiftvector(shiftvector'high downto shiftvector'low+1)
<= shiftvector(shiftvector'high-1 downto shiftvector'low);
end if;
end procedure;
function ShiftL2H_f(input : in std_logic;
shiftvector_in : in std_logic_vector)
return std_logic_vector is
variable shiftvector_out : std_logic_vector(shiftvector_in'range);
begin
shiftvector_out(shiftvector_in'low) := input;
-- always shift from low towards high
if shiftvector_in'high = shiftvector_in'right then
shiftvector_out(shiftvector_in'low+1 to shiftvector_in'high)
:= shiftvector_in(shiftvector_in'low to shiftvector_in'high-1);
else
shiftvector_out(shiftvector_in'high downto shiftvector_in'low+1)
:= shiftvector_in(shiftvector_in'high-1 downto shiftvector_in'low);
end if;
return shiftvector_out;
end function;
end Buffer_procedures;
>>>>>>>>>>>>>>>>>>>>>>>>>>>>> filename="ASCII_functions.vhd"
--
-- ***Author***
-- Jan De Ceuster
--
-- *** File ***
-- ASCII_functions.vhd
--
-- *** Functions ***
-- ASCII2HEX_f
-- input : std_logic_vector of size n*7
-- return : std_logic_vector of size n*4 (n*4-1 downto 0)
--
-- HEX2ASCII_f
-- input : std_logic_vector of size n*4
-- return : std_logic_vector of size n*7 (n*7-1 downto 0)
--
-- HEX2ASCII_f
-- input : std_logic_vector of size n*4
-- return : string of size n (1 to n)
--
-- *** Description ***
--
-- *** History ***
-- 001 initial
library ieee;
use ieee.std_logic_1164.all;
library nicethings;
use nicethings.ASCII_constants.all;
package ASCII_functions is
function ASCII2HEX_f(ASCII : std_logic_vector)
return std_logic_vector;
function ASCII2HEX_f(ASCII : std_logic_vector; size : integer)
return std_logic_vector;
function HEX2ASCII_f(HEX : std_logic_vector)
return std_logic_vector;
function HEX2ASCII_f(HEX : std_logic_vector; size : integer)
return std_logic_vector;
function HEX2ASCII_f(HEX : std_logic_vector)
return string;
end package;
package body ASCII_functions is
function ASCII2HEX_f(ASCII : std_logic_vector)
return std_logic_vector is
begin
return ASCII2HEX_f(ASCII,7);
end function;
function ASCII2HEX_f(ASCII : std_logic_vector; size : integer)
return std_logic_vector is
constant length : integer := (ASCII'high - ASCII'low + 1)/7;
variable HEXoffset, ASCIIoffset : integer;
variable HEX : std_logic_vector(length*4-1 downto 0);
variable temp : std_logic_vector(4 downto 0);
begin
for count in length-1 downto 0 loop
HEXoffset := count*4;
ASCIIoffset := count*size;
temp := ASCII(ASCIIoffset+4+ASCII'low downto ASCIIoffset+ASCII'low);
case temp is
when C_ASCII_0x0 => HEX(HEXoffset+3 downto HEXoffset) := "0000";
when C_ASCII_0x1 => HEX(HEXoffset+3 downto HEXoffset) := "0001";
when C_ASCII_0x2 => HEX(HEXoffset+3 downto HEXoffset) := "0010";
when C_ASCII_0x3 => HEX(HEXoffset+3 downto HEXoffset) := "0011";
when C_ASCII_0x4 => HEX(HEXoffset+3 downto HEXoffset) := "0100";
when C_ASCII_0x5 => HEX(HEXoffset+3 downto HEXoffset) := "0101";
when C_ASCII_0x6 => HEX(HEXoffset+3 downto HEXoffset) := "0110";
when C_ASCII_0x7 => HEX(HEXoffset+3 downto HEXoffset) := "0111";
when C_ASCII_0x8 => HEX(HEXoffset+3 downto HEXoffset) := "1000";
when C_ASCII_0x9 => HEX(HEXoffset+3 downto HEXoffset) := "1001";
when C_ASCII_0xA => HEX(HEXoffset+3 downto HEXoffset) := "1010";
when C_ASCII_0xB => HEX(HEXoffset+3 downto HEXoffset) := "1011";
when C_ASCII_0xC => HEX(HEXoffset+3 downto HEXoffset) := "1100";
when C_ASCII_0xD => HEX(HEXoffset+3 downto HEXoffset) := "1101";
when C_ASCII_0xE => HEX(HEXoffset+3 downto HEXoffset) := "1110";
when C_ASCII_0xF => HEX(HEXoffset+3 downto HEXoffset) := "1111";
when others => HEX(HEXoffset+3 downto HEXoffset) := "----";
end case;
end loop;
return HEX;
end function;
function HEX2ASCII_f(HEX : std_logic_vector)
return std_logic_vector is
begin
return HEX2ASCII_f(HEX,7);
end function;
function HEX2ASCII_f(HEX : std_logic_vector; size : integer)
return std_logic_vector is
constant length : integer := (HEX'high - HEX'low + 1)/4;
variable ASCII : std_logic_vector(length*7-1 downto 0) := (others => '0');
variable ASCIIoffset, HEXoffset : integer;
variable temp : std_logic_vector(3 downto 0);
begin
for count in length-1 downto 0 loop
ASCIIoffset := count*size;
HEXoffset := count*4;
temp := HEX(HEXoffset+3+HEX'low downto HEXoffset+HEX'low);
case temp is
when "0000" => ASCII(ASCIIoffset+6 downto ASCIIoffset) := C_ASCII_0;
when "0001" => ASCII(ASCIIoffset+6 downto ASCIIoffset) := C_ASCII_1;
when "0010" => ASCII(ASCIIoffset+6 downto ASCIIoffset) := C_ASCII_2;
when "0011" => ASCII(ASCIIoffset+6 downto ASCIIoffset) := C_ASCII_3;
when "0100" => ASCII(ASCIIoffset+6 downto ASCIIoffset) := C_ASCII_4;
when "0101" => ASCII(ASCIIoffset+6 downto ASCIIoffset) := C_ASCII_5;
when "0110" => ASCII(ASCIIoffset+6 downto ASCIIoffset) := C_ASCII_6;
when "0111" => ASCII(ASCIIoffset+6 downto ASCIIoffset) := C_ASCII_7;
when "1000" => ASCII(ASCIIoffset+6 downto ASCIIoffset) := C_ASCII_8;
when "1001" => ASCII(ASCIIoffset+6 downto ASCIIoffset) := C_ASCII_9;
when "1010" => ASCII(ASCIIoffset+6 downto ASCIIoffset) := C_ASCII_CAPITAL_A;
when "1011" => ASCII(ASCIIoffset+6 downto ASCIIoffset) := C_ASCII_CAPITAL_B;
when "1100" => ASCII(ASCIIoffset+6 downto ASCIIoffset) := C_ASCII_CAPITAL_C;
when "1101" => ASCII(ASCIIoffset+6 downto ASCIIoffset) := C_ASCII_CAPITAL_D;
when "1110" => ASCII(ASCIIoffset+6 downto ASCIIoffset) := C_ASCII_CAPITAL_E;
when "1111" => ASCII(ASCIIoffset+6 downto ASCIIoffset) := C_ASCII_CAPITAL_F;
when others => ASCII(ASCIIoffset+6 downto ASCIIoffset) := "-------";
end case;
end loop;
return ASCII;
end function;
function HEX2ASCII_f(HEX : std_logic_vector)
return string is
constant size : integer := HEX'high - HEX'low + 1;
variable ASCII : string(1 to size/4);
variable offset,offset2 : integer;
variable temp : std_logic_vector(3 downto 0);
begin
for count in size/4-1 downto 0 loop
offset := size/4-count;
offset2 := count*4;
temp := HEX(offset2+3+HEX'low downto offset2+HEX'low);
case temp is
when "0000" => ASCII(offset) := '0';
when "0001" => ASCII(offset) := '1';
when "0010" => ASCII(offset) := '2';
when "0011" => ASCII(offset) := '3';
when "0100" => ASCII(offset) := '4';
when "0101" => ASCII(offset) := '5';
when "0110" => ASCII(offset) := '6';
when "0111" => ASCII(offset) := '7';
when "1000" => ASCII(offset) := '8';
when "1001" => ASCII(offset) := '9';
when "1010" => ASCII(offset) := 'A';
when "1011" => ASCII(offset) := 'B';
when "1100" => ASCII(offset) := 'C';
when "1101" => ASCII(offset) := 'D';
when "1110" => ASCII(offset) := 'E';
when "1111" => ASCII(offset) := 'F';
when others => ASCII(offset) := '?';
end case;
end loop;
return ASCII;
end function;
end ASCII_functions;
>>>>>>>>>>>>>>>>>>>>>>>>>>>>> filename="ASCII_constants.vhd"
--
-- ***Author***
-- Jan De Ceuster
--
-- *** File ***
-- ASCII_constants.vhd
--
-- *** Entity ***
--
-- *** Port list ***
--
-- *** Description ***
--
-- *** History ***
--
library ieee;
use ieee.std_logic_1164.all;
package ASCII_constants is
-- TAPState constants, used for synthesis purposes
constant C_ASCII_nul : std_logic_vector(6 downto 0) := "0000000";
constant C_ASCII_soh : std_logic_vector(6 downto 0) := "0000001";
constant C_ASCII_stx : std_logic_vector(6 downto 0) := "0000010";
constant C_ASCII_etx : std_logic_vector(6 downto 0) := "0000011";
constant C_ASCII_eot : std_logic_vector(6 downto 0) := "0000100";
constant C_ASCII_enq : std_logic_vector(6 downto 0) := "0000101";
constant C_ASCII_ack : std_logic_vector(6 downto 0) := "0000110";
constant C_ASCII_bel : std_logic_vector(6 downto 0) := "0000111";
constant C_ASCII_bs : std_logic_vector(6 downto 0) := "0001000";
constant C_ASCII_ht : std_logic_vector(6 downto 0) := "0001001";
constant C_ASCII_lf : std_logic_vector(6 downto 0) := "0001010";
constant C_ASCII_vt : std_logic_vector(6 downto 0) := "0001011";
constant C_ASCII_np : std_logic_vector(6 downto 0) := "0001100";
constant C_ASCII_cr : std_logic_vector(6 downto 0) := "0001101";
constant C_ASCII_so : std_logic_vector(6 downto 0) := "0001110";
constant C_ASCII_si : std_logic_vector(6 downto 0) := "0001111";
constant C_ASCII_dle : std_logic_vector(6 downto 0) := "0010000";
constant C_ASCII_dc1 : std_logic_vector(6 downto 0) := "0010001";
constant C_ASCII_dc2 : std_logic_vector(6 downto 0) := "0010010";
constant C_ASCII_dc3 : std_logic_vector(6 downto 0) := "0010011";
constant C_ASCII_dc4 : std_logic_vector(6 downto 0) := "0010100";
constant C_ASCII_nak : std_logic_vector(6 downto 0) := "0010101";
constant C_ASCII_syn : std_logic_vector(6 downto 0) := "0010110";
constant C_ASCII_etb : std_logic_vector(6 downto 0) := "0010111";
constant C_ASCII_can : std_logic_vector(6 downto 0) := "0011000";
constant C_ASCII_em : std_logic_vector(6 downto 0) := "0011001";
constant C_ASCII_sub : std_logic_vector(6 downto 0) := "0011010";
constant C_ASCII_esc : std_logic_vector(6 downto 0) := "0011011";
constant C_ASCII_fs : std_logic_vector(6 downto 0) := "0011100";
constant C_ASCII_gs : std_logic_vector(6 downto 0) := "0011101";
constant C_ASCII_rs : std_logic_vector(6 downto 0) := "0011110";
constant C_ASCII_us : std_logic_vector(6 downto 0) := "0011111";
constant C_ASCII_sp : std_logic_vector(6 downto 0) := "0100000";
constant C_ASCII_exclamationmark : std_logic_vector(6 downto 0) := "0100001";
constant C_ASCII_quotationmark : std_logic_vector(6 downto 0) := "0100010";
constant C_ASCII_number : std_logic_vector(6 downto 0) := "0100011";
constant C_ASCII_dollar : std_logic_vector(6 downto 0) := "0100100";
constant C_ASCII_percent : std_logic_vector(6 downto 0) := "0100101";
constant C_ASCII_ampersand : std_logic_vector(6 downto 0) := "0100110";
constant C_ASCII_apstrophe : std_logic_vector(6 downto 0) := "0100111";
constant C_ASCII_lparenthesis : std_logic_vector(6 downto 0) := "0101000";
constant C_ASCII_rparenthesis : std_logic_vector(6 downto 0) := "0101001";
constant C_ASCII_astrix : std_logic_vector(6 downto 0) := "0101010";
constant C_ASCII_plus : std_logic_vector(6 downto 0) := "0101011";
constant C_ASCII_comma : std_logic_vector(6 downto 0) := "0101100";
constant C_ASCII_minus : std_logic_vector(6 downto 0) := "0101101";
constant C_ASCII_fullstop : std_logic_vector(6 downto 0) := "0101110";
constant C_ASCII_slash : std_logic_vector(6 downto 0) := "0101111";
constant C_ASCII_0 : std_logic_vector(6 downto 0) := "0110000";
constant C_ASCII_1 : std_logic_vector(6 downto 0) := "0110001";
constant C_ASCII_2 : std_logic_vector(6 downto 0) := "0110010";
constant C_ASCII_3 : std_logic_vector(6 downto 0) := "0110011";
constant C_ASCII_4 : std_logic_vector(6 downto 0) := "0110100";
constant C_ASCII_5 : std_logic_vector(6 downto 0) := "0110101";
constant C_ASCII_6 : std_logic_vector(6 downto 0) := "0110110";
constant C_ASCII_7 : std_logic_vector(6 downto 0) := "0110111";
constant C_ASCII_8 : std_logic_vector(6 downto 0) := "0111000";
constant C_ASCII_9 : std_logic_vector(6 downto 0) := "0111001";
constant C_ASCII_colon : std_logic_vector(6 downto 0) := "0111010";
constant C_ASCII_semicolon : std_logic_vector(6 downto 0) := "0111011";
constant C_ASCII_lessthan : std_logic_vector(6 downto 0) := "0111100";
constant C_ASCII_equal : std_logic_vector(6 downto 0) := "0111101";
constant C_ASCII_greaterthan : std_logic_vector(6 downto 0) := "0111110";
constant C_ASCII_questionmark : std_logic_vector(6 downto 0) := "0111111";
constant C_ASCII_at : std_logic_vector(6 downto 0) := "1000000";
constant C_ASCII_CAPITAL_A : std_logic_vector(6 downto 0) := "1000001";
constant C_ASCII_CAPITAL_B : std_logic_vector(6 downto 0) := "1000010";
constant C_ASCII_CAPITAL_C : std_logic_vector(6 downto 0) := "1000011";
constant C_ASCII_CAPITAL_D : std_logic_vector(6 downto 0) := "1000100";
constant C_ASCII_CAPITAL_E : std_logic_vector(6 downto 0) := "1000101";
constant C_ASCII_CAPITAL_F : std_logic_vector(6 downto 0) := "1000110";
constant C_ASCII_CAPITAL_G : std_logic_vector(6 downto 0) := "1000111";
constant C_ASCII_CAPITAL_H : std_logic_vector(6 downto 0) := "1001000";
constant C_ASCII_CAPITAL_I : std_logic_vector(6 downto 0) := "1001001";
constant C_ASCII_CAPITAL_J : std_logic_vector(6 downto 0) := "1001010";
constant C_ASCII_CAPITAL_K : std_logic_vector(6 downto 0) := "1001011";
constant C_ASCII_CAPITAL_L : std_logic_vector(6 downto 0) := "1001100";
constant C_ASCII_CAPITAL_M : std_logic_vector(6 downto 0) := "1001101";
constant C_ASCII_CAPITAL_N : std_logic_vector(6 downto 0) := "1001110";
constant C_ASCII_CAPITAL_O : std_logic_vector(6 downto 0) := "1001111";
constant C_ASCII_CAPITAL_P : std_logic_vector(6 downto 0) := "1010000";
constant C_ASCII_CAPITAL_Q : std_logic_vector(6 downto 0) := "1010001";
constant C_ASCII_CAPITAL_R : std_logic_vector(6 downto 0) := "1010010";
constant C_ASCII_CAPITAL_S : std_logic_vector(6 downto 0) := "1010011";
constant C_ASCII_CAPITAL_T : std_logic_vector(6 downto 0) := "1010100";
constant C_ASCII_CAPITAL_U : std_logic_vector(6 downto 0) := "1010101";
constant C_ASCII_CAPITAL_V : std_logic_vector(6 downto 0) := "1010110";
constant C_ASCII_CAPITAL_W : std_logic_vector(6 downto 0) := "1010111";
constant C_ASCII_CAPITAL_X : std_logic_vector(6 downto 0) := "1011000";
constant C_ASCII_CAPITAL_Y : std_logic_vector(6 downto 0) := "1011001";
constant C_ASCII_CAPITAL_Z : std_logic_vector(6 downto 0) := "1011010";
constant C_ASCII_lsquarebracket : std_logic_vector(6 downto 0) := "1011011";
constant C_ASCII_backslash : std_logic_vector(6 downto 0) := "1011100";
constant C_ASCII_rsquarebracket : std_logic_vector(6 downto 0) := "1011101";
constant C_ASCII_circumflex : std_logic_vector(6 downto 0) := "1011110";
constant C_ASCII_underscore : std_logic_vector(6 downto 0) := "1011111";
constant C_ASCII_grave : std_logic_vector(6 downto 0) := "1100000";
constant C_ASCII_a : std_logic_vector(6 downto 0) := "1100001";
constant C_ASCII_b : std_logic_vector(6 downto 0) := "1100010";
constant C_ASCII_c : std_logic_vector(6 downto 0) := "1100011";
constant C_ASCII_d : std_logic_vector(6 downto 0) := "1100100";
constant C_ASCII_e : std_logic_vector(6 downto 0) := "1100101";
constant C_ASCII_f : std_logic_vector(6 downto 0) := "1100110";
constant C_ASCII_g : std_logic_vector(6 downto 0) := "1100111";
constant C_ASCII_h : std_logic_vector(6 downto 0) := "1101000";
constant C_ASCII_i : std_logic_vector(6 downto 0) := "1101001";
constant C_ASCII_j : std_logic_vector(6 downto 0) := "1101010";
constant C_ASCII_k : std_logic_vector(6 downto 0) := "1101011";
constant C_ASCII_l : std_logic_vector(6 downto 0) := "1101100";
constant C_ASCII_m : std_logic_vector(6 downto 0) := "1101101";
constant C_ASCII_n : std_logic_vector(6 downto 0) := "1101110";
constant C_ASCII_o : std_logic_vector(6 downto 0) := "1101111";
constant C_ASCII_p : std_logic_vector(6 downto 0) := "1110000";
constant C_ASCII_q : std_logic_vector(6 downto 0) := "1110001";
constant C_ASCII_r : std_logic_vector(6 downto 0) := "1110010";
constant C_ASCII_s : std_logic_vector(6 downto 0) := "1110011";
constant C_ASCII_t : std_logic_vector(6 downto 0) := "1110100";
constant C_ASCII_u : std_logic_vector(6 downto 0) := "1110101";
constant C_ASCII_v : std_logic_vector(6 downto 0) := "1110110";
constant C_ASCII_w : std_logic_vector(6 downto 0) := "1110111";
constant C_ASCII_x : std_logic_vector(6 downto 0) := "1111000";
constant C_ASCII_y : std_logic_vector(6 downto 0) := "1111001";
constant C_ASCII_z : std_logic_vector(6 downto 0) := "1111010";
constant C_ASCII_lcurlybracket : std_logic_vector(6 downto 0) := "1111011";
constant C_ASCII_verticalbar : std_logic_vector(6 downto 0) := "1111100";
constant C_ASCII_rcurlybracket : std_logic_vector(6 downto 0) := "1111101";
constant C_ASCII_tilde : std_logic_vector(6 downto 0) := "1111110";
constant C_ASCII_del : std_logic_vector(6 downto 0) := "1111111";
constant C_ASCII_0x0 : std_logic_vector(4 downto 0) := "10000";
constant C_ASCII_0x1 : std_logic_vector(4 downto 0) := "10001";
constant C_ASCII_0x2 : std_logic_vector(4 downto 0) := "10010";
constant C_ASCII_0x3 : std_logic_vector(4 downto 0) := "10011";
constant C_ASCII_0x4 : std_logic_vector(4 downto 0) := "10100";
constant C_ASCII_0x5 : std_logic_vector(4 downto 0) := "10101";
constant C_ASCII_0x6 : std_logic_vector(4 downto 0) := "10110";
constant C_ASCII_0x7 : std_logic_vector(4 downto 0) := "10111";
constant C_ASCII_0x8 : std_logic_vector(4 downto 0) := "11000";
constant C_ASCII_0x9 : std_logic_vector(4 downto 0) := "11001";
constant C_ASCII_0xA : std_logic_vector(4 downto 0) := "00001";
constant C_ASCII_0xB : std_logic_vector(4 downto 0) := "00010";
constant C_ASCII_0xC : std_logic_vector(4 downto 0) := "00011";
constant C_ASCII_0xD : std_logic_vector(4 downto 0) := "00100";
constant C_ASCII_0xE : std_logic_vector(4 downto 0) := "00101";
constant C_ASCII_0xF : std_logic_vector(4 downto 0) := "00110";
end ASCII_constants;
package body ASCII_constants is
end ASCII_constants;
>>>>>>>>>>>>>>>>>>>>>>>>>>>>> filename="EIA232_RX_bridge.vhd"
--
-- ***Author***
-- Jan De Ceuster
--
-- *** File ***
-- EIA232_RX_bridge.vhd
--
-- *** Entity ***
-- EIA232_RX_bridge
--
-- *** Port list ***
-- nrst (in, 1) Active low reset
-- clk (in, 1) System Clock
--
-- EIA232_RXD (out, 1) EIA232 Transmit Serial Data to PC
-- EIA232_RTS (in, 1) EIA232 Stop Sending
--
-- ParallelOUT_Data (in, 8) ParallelOUT sends the data to EIA232 interface.
-- ParallelOUT_Ack (out, 1) protocol: synchronous Full Handshake, device is slave
-- ParallelOUT_Req (in, 1)
--
-- *** Description ***
-- This block will translate the parallel data from a generic interface to
-- a serial output according the EIA232 standard with RXD and RTS.
-- The size of the parallel data (generic paramter DATA_SIZE) can be anything
-- from 5 to 8. This is also as specified in the EIA232 standard.
-- One start and stopbit is provided.
-- The generic parameter CLK_DIV is used to set the correct baudrate:
-- baudrate = inputfreq/CLK_DIV
--
-- *** History ***
-- 001 27-06-2003 Initial version
-- Fully tested and optimized
library ieee;
use ieee.std_logic_1164.all, ieee.std_logic_arith.all;
library buffers;
use buffers.shift_registers.all;
entity EIA232_RX_bridge is
generic (
DATA_SIZE : in integer := 8; -- size can be anything from 5 to 8
CLK_FREQ : in integer := 33000000; -- clock frequency in Hz
BAUDRATE : in integer := 115200
);
port (
nrst : in std_logic;
clk : in std_logic;
EIA232_RXD : out std_logic;
EIA232_RTS : in std_logic;
ParallelOUT_Data : in std_logic_vector(DATA_SIZE-1 downto 0);
ParallelOUT_Req : in std_logic;
ParallelOUT_Ack : out std_logic
);
end EIA232_RX_bridge;
architecture RTL of EIA232_RX_bridge is
constant TIMECOUNTER_SIZE : integer := CLKFREQ/BAUDRATE-1;
signal timecounter : integer range 0 to TIMECOUNTER_SIZE;
signal bitcounter : integer range 0 to DATA_SIZE;
signal EIA232ShiftRegister : std_logic_vector(1 to DATA_SIZE);
signal EIA232State, nextEIA232State : EIA232State_type;
signal StartSending : std_logic;
signal timecounter_pulse : std_logic;
signal sync_EIA232_RTS : std_logic_vector(3 downto 1);
begin
-- The EIA232State statemachine controls the correct flow for the start, data
-- and stop bit(s).
process (EIA232State, StartSending, bitcounter)
begin
nextEIA232State <= EIA232State;
case EIA232State is
when E_EIA232State_Waiting =>
-- Req for sending data received.
if StartSending = '1' then
nextEIA232State <= E_EIA232State_Start;
end if;
when E_EIA232State_Start =>
nextEIA232State <= E_EIA232State_Data;
when E_EIA232State_Data =>
-- Last databit send.
if bitcounter = DATA_SIZE and StartSending = '0' then
nextEIA232State <= E_EIA232State_Waiting;
end if;
when others =>
nextEIA232State <= (others => '-');
end case;
end process;
-- Generate a pulse when timecounter is 0.
timecounter_pulse <= '1' when timecounter = 0 else '0';
-- Sample the inputsignal from physical EIA232 interface into a flipflop.
process (clk)
begin
if rising_edge(clk) then
ShiftL2H_p(EIA232_RTS,sync_EIA232_RTS);
end if;
end process;
process (clk,nrst)
begin
if nrst = '0' then
timecounter <= TIMECOUNTER_SIZE;
ParallelOUT_Ack <= '0';
StartSending <= '0';
EIA232ShiftRegister <= (others => '1');
elsif rising_edge(clk) then
ParallelOUT_Ack <= '0';
-- Counter to devide the clk input.
if timecounter_pulse = '1' then
timecounter <= TIMECOUNTER_SIZE;
else
timecounter <= timecounter - 1;
end if;
case EIA232State is
when E_EIA232State_Waiting =>
-- Req received and ready to transmit data.
if StartSending = '0' and ParallelOUT_Req = '1'
and sync_EIA232_RTS(sync_EIA232_RTS'high) = '0' then
-- Load the shiftregister
EIA232ShiftRegister(1 to DATA_SIZE) <= ParallelOUT_Data;
ParallelOUT_Ack <= '1';
StartSending <= '1';
end if;
when E_EIA232State_Start | E_EIA232State_Data =>
StartSending <= '0';
-- The shiftregister can shift every timecounter_pulse.
-- This register runs on clk because it must be possible to load
-- external data assynchronous to timecounter_pulse.
if timecounter_pulse = '1' then
ShiftL2H_p('1',EIA232ShiftRegister);
end if;
when others =>
StartSending <= '0';
end case;
end if;
end process;
process (clk,nrst)
begin
if nrst = '0' then
EIA232_RXD <= '1';
EIA232State <= E_EIA232State_Waiting;
bitcounter <= 0;
elsif rising_edge(clk) then
if timecounter_pulse = '1' then
EIA232State <= nextEIA232State;
case nextEIA232State is
when E_EIA232State_Waiting =>
EIA232_RXD <= '1';
when E_EIA232State_Start =>
EIA232_RXD <= '0';
when E_EIA232State_Data =>
EIA232_RXD <= EIA232ShiftRegister(DATA_SIZE);
if bitcounter = DATA_SIZE then
bitcounter <= 0;
else
bitcounter <= bitcounter + 1;
end if;
when others =>
end case;
end if;
end if;
end process;
end RTL;
>>>>>>>>>>>>>>>>>>>>>>>>>>>>> filename="EIA232_TX_bridge.vhd"
--
-- ***Author***
-- Jan De Ceuster
--
-- *** File ***
-- EIA232_TX_bridge.vhd
--
-- *** Entity ***
-- EIA232_TX_bridge
--
-- *** Port list ***
-- nrst (in, 1) Active low reset
-- clk (in, 1) System Clock
--
-- EIA232_TXD (in, 1) EIA232 Receive Serial Data from PC
-- EIA232_CTS (out, 1) EIA232 Stop Receiving
--
-- ParallelIN_Data (out, 8) ParallelIN sends the data from EIA232 interface.
-- ParallelIN_Ack (out, 1) protocol: synchronous Full Handshake, device
-- ParallelIN_Req (in, 1) is slave.
library ieee;
use ieee.std_logic_1164.all, ieee.std_logic_arith.all;
library buffers;
use buffers.shift_registers.all;
entity EIA232_TX_bridge is
generic (
DATA_SIZE : in integer := 8;
CLK_FREQ : in integer := 33000000; -- clock frequency in Hz
BAUDRATE : in integer := 115200
);
port (
nrst : in std_logic;
clk : in std_logic;
EIA232_TXD : in std_logic;
EIA232_CTS : out std_logic;
ParallelIN_Data : out std_logic_vector(DATA_SIZE-1 downto 0);
ParallelIN_Req : in std_logic;
ParallelIN_Ack : out std_logic
);
end EIA232_TX_bridge;
architecture RTL of EIA232_TX_bridge is
constant BITCOUNTER_SIZE : integer := DATA_SIZE - 1;
constant TIMECOUNTER_SIZE : integer := CLKFREQ/BAUDRATE-1;
constant HALF_TIMECOUNTER_SIZE : integer := TIMECOUNTER_SIZE/2 - 1;
signal timecounter : integer range 0 to TIMECOUNTER_SIZE;
signal bitcounter : integer range 0 to DATA_SIZE-1;
signal ParallelIN_Data_reg : std_logic_vector(1 to DATA_SIZE);
signal EIA232State, nextEIA232State : EIA232State_type;
signal timecounter_pulse : std_logic;
signal StartReceive : std_logic;
signal sync_EIA232_TXD : std_logic_vector(2 downto 1);
signal faling_edge_EIA232_TXD : boolean;
signal buffer_empty : boolean;
begin
process (EIA232State, StartReceive, bitcounter)
begin
nextEIA232State <= EIA232State;
case EIA232State is
when E_EIA232State_Waiting =>
if StartReceive = '1' then
nextEIA232State <= E_EIA232State_Start;
end if;
when E_EIA232State_Start =>
nextEIA232State <= E_EIA232State_Data;
when E_EIA232State_Data =>
if bitcounter = 0 then
nextEIA232State <= E_EIA232State_Stop;
end if;
when E_EIA232State_Stop =>
nextEIA232State <= E_EIA232State_Waiting;
when others =>
nextEIA232State <= (others => '-');
end case;
end process;
-- sample signal into flipflops
process (clk)
begin
if rising_edge(clk) then
ShiftL2H_p(EIA232_TXD,sync_EIA232_TXD);
end if;
end process;
faling_edge_EIA232_TXD <= sync_EIA232_TXD(sync_EIA232_TXD'high-1) = '0'
and sync_EIA232_TXD(sync_EIA232_TXD'high) = '1';
timecounter_pulse <= '1' when timecounter = 0 else '0';
process (clk, nrst)
begin
if nrst = '0' then
timecounter <= TIMECOUNTER_SIZE;
StartReceive <= '0';
elsif rising_edge(clk) then
-- endless timer with conditional preload (when detecting a startbit)
-- StartReceive indicates the detection of the startbit
if faling_edge_EIA232_TXD -- faling edge TXD,
and nextEIA232State = E_EIA232State_Waiting then -- detect start bit
timecounter <= HALF_TIMECOUNTER_SIZE;
StartReceive <= '1';
elsif timecounter = 0 then -- counter reset
timecounter <= TIMECOUNTER_SIZE;
StartReceive <= '0';
else
timecounter <= timecounter - 1; -- count down
end if;
end if;
end process;
process (clk, nrst)
begin
if nrst = '0' then
EIA232State <= E_EIA232State_Waiting;
ParallelIN_Data_reg <= (others => '-');
bitcounter <= BITCOUNTER_SIZE;
elsif rising_edge(clk) then
if timecounter_pulse = '1' then
EIA232State <= nextEIA232State;
bitcounter <= BITCOUNTER_SIZE;
-- shift register
ShiftL2H_p(sync_EIA232_TXD(sync_EIA232_TXD'high),ParallelIN_Data_reg);
if EIA232State = E_EIA232State_Start
or EIA232State = E_EIA232State_Data then
-- counter for the shiftregister
if bitcounter = 0 then
bitcounter <= BITCOUNTER_SIZE;
else
bitcounter <= bitcounter - 1;
end if;
end if;
end if;
end if;
end process;
process (clk, nrst)
begin
if nrst = '0' then
buffer_empty <= TRUE;
EIA232_CTS <= '1';
ParallelIN_Ack <= '0';
elsif rising_edge(clk) then
if buffer_empty then
EIA232_CTS <= '0';
else
EIA232_CTS <= '1';
end if;
if EIA232State = E_EIA232State_Data then
buffer_empty <= FALSE;
end if;
-- Output the shiftregister directly.
if timecounter_pulse = '1' and EIA232State = E_EIA232State_Stop then
ParallelIN_Data <= ParallelIN_Data_reg;
end if;
-- The shiftregister now contains the received byte.
-- => give an ack for 1 clock cycle (done with timecounter_pulse)
if ParallelIN_REQ = '1' and not buffer_empty and EIA232State = E_EIA232State_Waiting then
ParallelIN_Ack <= '1';
buffer_empty <= TRUE;
else
ParallelIN_Ack <= '0';
end if;
end if;
end process;
end RTL;
>>>>>>>>>>>>>>>>>>>>>>>>>>>>> filename="EIA232_package.vhd"
--
-- ***Author***
-- Jan De Ceuster
--
-- *** File ***
-- EIA232_constants.vhd
--
-- *** Entity ***
--
-- *** Port list ***
--
-- *** Description ***
--
-- *** History ***
--
library ieee;
use ieee.std_logic_1164.all;
package EIA232 is
-- constants
-- enumerations
type EIA232State_type is (E_EIA232State_Waiting, E_EIA232State_Start,
E_EIA232State_Data, E_EIA232State_Stop);
-- functions
-- procedures
-- components
component EIA232_TX_bridge
-- receive data via a FullHndshk protocol
-- bridge is master on EIA232 lines
generic (
DATA_SIZE : in integer := 8; -- size can be anything from 5 to 8
CLK_FREQ : in integer := 33000000; -- clock frequency in Hz
BAUDRATE : in integer := 115200
);
port (
nrst : in std_logic;
clk : in std_logic;
EIA232_TXD : in std_logic;
EIA232_CTS : out std_logic;
ParallelIN_Data : out std_logic_vector(DATA_SIZE-1 downto 0);
ParallelIN_Req : in std_logic;
ParallelIN_Ack : out std_logic
);
end component;
component EIA232_RX_bridge
-- send data via a FullHndshk protocol
-- bridge is master on EIA232 lines
generic (
DATA_SIZE : in integer := 8; -- size can be anything from 5 to 8
CLK_FREQ : in integer := 33000000; -- clock frequency in Hz
BAUDRATE : in integer := 115200
);
port (
nrst : in std_logic;
clk : in std_logic;
EIA232_RXD : out std_logic;
EIA232_RTS : in std_logic;
ParallelOUT_Data : in std_logic_vector(DATA_SIZE-1 downto 0);
ParallelOUT_Req : in std_logic;
ParallelOUT_Ack : out std_logic
);
end component;
end EIA232;
package body EIA232 is
end EIA232;
Article: 76815damn, posted on the newsgroups instead of private message... oh well, it's free anyway but these versions are quite buggy. There goes my reputation... :D >>>>>>>>>>> 900 lines redactedArticle: 76816
Adam wrote: > Hello all, > > Will an FPGA PLL lock onto a biphase mark(Manchester ??) encoded signal? > I'm trying to build an SPDIF receiver and am wondering if its possible to > directly connect the input signal(after analog level adjustment) to an FPGA > ... A Manhester decoder can be implemented in less than one Virtex-II CLB. You need an 8x oversampling clock, but the tolerances are quite generous: The clock frequency must be between 5 and 12 times the incoming bit rate. Send me an e-mail if you need the code. I described the concept years ago in our XCell magazine. http://query.xilinx.com/ui/jsp/xilinx_template.jsp?field=%2Fcompany%2Fsearch. Peter Alfke, Xilinx Applications ( peter@xilinx.com)Article: 76817
Hello Xilinx folks, I have an issue recently developed when changing an oscillator input from a oscillator package to a clock generated from a Cypress FX2 chip, both running at the same frequency. With the oscillator package I was having no trouble at all but the Cypress chips has to enumerate and renumerate and the oscillator signal arrives at the Xilinx DCM much later, causing the Xilinx S3 to lock out. A pushbutton reset to the DCM reset pin or a JTAG reload of the Xilinx S3 will bring the S3 back to life, however, the power up sequence does not work. This brings up a number of questions that a proper reset for the DCM requires: First, it states in XAPP462, that a failed lock situation should reset the DCM. Do you do this by simply inverting the LOCKED signal and putting it into the DCM RESET pin? Or do you need some sort of external circuit to detect the lock signal and do a hard pin reset? Second, XAPP462 suggest a SLR16 in the reset of the DCM. I assume this is only necessary if you are using the external feedback path. Yes? Third, XAPP462 mentions a STARTUP_WAIT attribute (pg.15). Where is this setting in the newer 6.2 Project Navigator release? Forth, there is an FPGA Startup Clock option with CCLK, User Clock, or JTAG Clk option. What is the CCLK? And if you select User Clk, how do you indicate which pin or which VHDL signal you intend to use with it? Thanks, Brad Smallridge b r a d @ a i v i s i o n . c o mArticle: 76818
> Artenz
If you want a specific implementation, there are usually things about how
you code a given function that can help the guide the tools to your intended
solution.
In this case, without the specific coding style the results are not optimal
from an area (resource) standpoint. I will take this up the the synthesis
folks.
Back to how do I get MUXF5/MUXF6.
This implies eight to one multiplexing, so use a three bit select in the
case statement.
This following will produce the LUT4/MUXF5/MUXF6 logic:
module lut_test8( a, b, c, f, s );
input [3:0] a, b;
input [1:0] s;
input [1:0] f;
output c;
reg c;
always @(a or b or f or s)
case({s, f[1]})
4'b000: c = !f[0]? (a[0] & b[0]) : (a[0] | b[0]);
4'b010: c = !f[0]? (a[1] & b[1]) : (a[1] | b[1]);
4'b100: c = !f[0]? (a[2] & b[2]) : (a[2] | b[2]);
4'b110: c = !f[0]? (a[3] & b[3]) : (a[3] | b[3]);
// 4'b0001: c = a[0] | b[0];
// 4'b0101: c = a[1] | b[1];
// 4'b1001: c = a[2] | b[2];
// 4'b1101: c = a[3] | b[3];
4'b001: c = !f[0]? (a[0] ^ b[0]) : (a[0] & ~b[0]);
4'b011: c = !f[0]? (a[1] ^ b[1]) : (a[1] & ~b[1]);
4'b101: c = !f[0]? (a[2] ^ b[2]) : (a[2] & ~b[2]);
4'b111: c = !f[0]? (a[3] ^ b[3]) : (a[3] & ~b[3]);
// 4'b0011: c = a[0] & ~b[0];
// 4'b0111: c = a[1] & ~b[1];
// 4'b1011: c = a[2] & ~b[2];
// 4'b1111: c = a[3] & ~b[3];
endcase
endmodule
Article: 76819
Hello,
i'm trying to stop a running executable on the ppc405 placed on a
virtex2-pro.
Currently i'm trying to do this by pulling the clock-input
(CPM405CLOCK) to the ppc to 1 (simple by using a multiplexed bufg
switching between normal clock( ppc_clk_), and net_vcc0), thus
imitating kind of power management as i read in the
ppc405-block-reference-guide.
This approach won't work, the ppc is not responding when normal clock
operation continues.
My next intention was to suspend the ppc in software, though there is
no halt-instruction.
In further threads i read setting the msr[13]-bit will put the ppc to
sleep and certain interrupts will awaken it again.
So, if anyone has done this before or has further suggestions how to
do this any help would be very useful.
Thanks.
Best regards,
Patrick Siegel
Article: 76820Philip is correct but there are tons of other applications. In Systolic Filters(Direct Form with extra pipelining), Direct Form Filters, Complex Multiplies etc. - the second A and B Register is extremely useful. Its also useful if you are building Larger adders and multipliers out of multiple DSP48's. In fact using the internal cascades and the dual registers - you can place an N-tap Systolic filter running at Max Speed in a column of N DSP48's and only need to enter with your input data at the bottom most DSP48 and exit with your output from the top most DSP48! - Vic Philip Freidin wrote: > On 9 Dec 2004 16:18:39 -0800, "Kevin Brown" <kbrown_home@hotmail.com> wrote: > >In the extreme DSP slice there are two registers before the > >multiplication on each of the A and B inputs. Does anyone know why you > >would need 2 registers before the multiplication? > > > >At first I thought it may be a register similar to the one in a > >MULT18x18s, but changing the number of registers on A and B from 1 to 2 > >had no effect on timing. Also it wouldn't make sense since A and B are > >individually selectable to have 0,1, or 2 registers. > > > >-Kevin > > If you are doing larger multiplies (36x18, 36x36) you may need to > delay partial operands so that all the pieces arrive at the destination > at the same time. > > For IIR filters, you may not be able to tollerate multiple pipe stages, > so that may be a use for the "0 registers" > > Philip Freidin > FliptronicsArticle: 76821
Vic Vadi wrote: > Philip is correct but there are tons of other applications. > > In Systolic Filters(Direct Form with extra pipelining), > Direct Form Filters, Complex Multiplies etc. - the > second A and B Register is extremely useful. Its also > useful if you are building Larger adders and multipliers > out of multiple DSP48's. Correction - I meant to say Larger input adders such as adding more than three numbers together in multiple DSP48's. - VicArticle: 76822
> Hi Jim, > > There is a connectivity problem that can be easily corrected. The SRL16 > needs to be in the G-LUT. Since the connection from the G-LUT to the > MUXF5 uses the I0 input in the hardware, your code needs to do the same, > but you have the SRL16 driving the I1 input of the MUXF5. The code works > okay if I swap the MUXF5 inputs to match the hardware: > > the_muxf5: MUXF5 > port map ( > i0 => internal_2, > i1 => internal_1, > o => y, > s => sel > ); > > Number of occupied Slices: 1 out of 256 1% > > Regards, > Bret Thanks, it works fine now!Article: 76823
Depending on what you are trying to do you can use the DBGC405DEBUGHALT pin on the processor block to stop the processor. See the PowerPC 405 Processor Block Guide for more information (http://direct.xilinx.com/bvdocs/userguides/ug018.pdf). - Peter Patrick wrote: > Hello, > > i'm trying to stop a running executable on the ppc405 placed on a > virtex2-pro. > Currently i'm trying to do this by pulling the clock-input > (CPM405CLOCK) to the ppc to 1 (simple by using a multiplexed bufg > switching between normal clock( ppc_clk_), and net_vcc0), thus > imitating kind of power management as i read in the > ppc405-block-reference-guide. > This approach won't work, the ppc is not responding when normal clock > operation continues. > My next intention was to suspend the ppc in software, though there is > no halt-instruction. > In further threads i read setting the msr[13]-bit will put the ppc to > sleep and certain interrupts will awaken it again. > So, if anyone has done this before or has further suggestions how to > do this any help would be very useful. > Thanks. > > Best regards, > Patrick SiegelArticle: 76824
Elder Costa wrote: > Hello folks. > > I have implemented the entity bellow by instantciating a dual ported > block RAM with different bus widths (RAMB16_S18_S36 - I am developing > for Virtex II or Spartan 3). Whereas it is relatively simple to do it by > instantiacing the component from Xilinx library, I wonder if there is a > way to code the module so that Xst infers the block RAM. I tried in one > or two ways but it used logic in slices instead of BRAM and it required > a lot of logic for a 1kib RAM. Could somebody give a hint on this? I > looked at Xilinx documentation and couldn't find an example for this > particular problem. > > entity gaintab is > Port ( > -- ports de acesso do processador > i_ProcAddr : in std_logic_vector(9 downto 0); > i_ProcDataIn : in std_logic_vector(15 downto 0); > i_ProcWr : in std_logic; > i_ProcEn : in std_logic; > i_ProcClk : in std_logic; > o_ProcDataOut : out std_logic_vector(15 downto 0); > -- ports de acesso interno (fpga) > i_FpgaAddr : in std_logic_vector(6 downto 0); > i_FpgaClk : in std_logic; > o_FpgaDataOut : out std_logic_vector(31 downto 0) > ); > end gaintab; > > > TIA. > > Elder. > I've been able to make the synthesizer to infer the RAM as above but I had to create an entity similar to the above but with the same bus width in every data port and then by instanciating it twice. Somewhat tricky though. Regards. Elder.
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