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Richard Iachetta <iachetta@us.ibm.com> wrote in message news:<MPG.19f0c726fe699c2b98982b@ausnews.austin.ibm.com>... > In article <3F85E01C.A0E99EFA@xilinx.com>, eric.crabill@xilinx.com says... > > you will need to put in some design > > effort. > > That's an understatement! Hi Richard, Can you be so kind and share some details over the effort of the Xilinx PCI-X core solution of this problem. I have a similiar problem - only all ports are PCI-X. ThankX, NAHUM.Article: 61801
Hi, Using QuartusII 3.0, I have a VHDL file with a package declaration. From a VHDL file in a project I can see the declarations in the pacakage by using use work.<package name>.all; But from another VHDL file in the same project, the same 'use' line gives the following error: Error: VHDL Use Clause error at <filename>.vhd(<nn>): design library work does not contain primary unit <package name> The help system says that you do not need to have 'library work;' line, but adding that does not help either. In general, I am having lots of problem making package to work with QuartusII. Even in the one file where the use declartion works, it was not working at first, started working after deleting the file from the project and re-inserting it. It is driving me crazy. Please help. Thanks.Article: 61802
The order of the VHDL files being processed is important. Go to the Assignment->Settings->Files & Directories->Add/Remove command and order the VHDL files in the project, such that the files which contain the package definition are at the top of the list. Use the Buttons on the side of the dialog to select a file and move it up or down in the list. Did you try clicking on the error message in the message window and then hitting F1 for help? Hope this helps. - Subroto Datta Altera Corp. "Pratip Mukherjee" <pratipm_delafterul@hotmail.com> wrote in message news:Xns941281BF7FF59pratipmhotmailcom@204.127.199.17... > Hi, > Using QuartusII 3.0, I have a VHDL file with a package declaration. From a > VHDL file in a project I can see the declarations in the pacakage by using > use work.<package name>.all; > But from another VHDL file in the same project, the same 'use' line gives > the following error: > Error: VHDL Use Clause error at <filename>.vhd(<nn>): design library work > does not contain primary unit <package name> > The help system says that you do not need to have 'library work;' line, but > adding that does not help either. > In general, I am having lots of problem making package to work with > QuartusII. Even in the one file where the use declartion works, it was not > working at first, started working after deleting the file from the project > and re-inserting it. It is driving me crazy. Please help. > > Thanks.Article: 61803
Greetings, here is an interesting problem: ISE 4.2i, ISE 5.2i SP3 - same result, Slave Serial configuation of Spartan-IIE 300 results in un-intended (erroneous) functionality, while JTAG configuation based on the same .ncd file results in proper functionality. The FPGA gets "properly" configured in either case (PROGRAM, INIT and DONE lines do what they supposed to) - DONE goes high. For JTAG configuration a .bit file is generated using JTAG startup clock option, while for Slave Serial - CCLK startup clock option is used in BITGEN command line. When JTAG port is used to verify the contents of the FPGA (against .bit file that results in proper functionality) after is was configured using slave serial approach (resulting in erroneous functionality) - the verification is reported as a success!!! Anyone have seen anything like that? Any suggestions? Thanks for any help. -- YWSArticle: 61804
On Thu, 9 Oct 2003 23:07:39 +1000, "Stephen Lohning" <stephen.lohning@oxnee.com> wrote:
>I wish to create a rom for Virtex2 xilinix part.
>Which is better/ works using attributes INIT_00 etc in the code
>or puting them in the configuration file.
>The code will be written in vhdl.
>Any body seen any examples of this being done?
>Thanks
>
Try
http://www.fpga-faq.com/FAQ_Pages/0031_How_to_initialize_Block_RAM.htm
===================
Philip Freidin
philip@fliptronics.com
Host for WWW.FPGA-FAQ.COM
Article: 61805Philip Freidin wrote: > On Thu, 9 Oct 2003 23:07:39 +1000, "Stephen Lohning" <stephen.lohning@oxnee.com> wrote: > >>I wish to create a rom for Virtex2 xilinix part. >>Which is better/ works using attributes INIT_00 etc in the code >>or puting them in the configuration file. >>The code will be written in vhdl. >>Any body seen any examples of this being done? >>Thanks >> > > > Try > > http://www.fpga-faq.com/FAQ_Pages/0031_How_to_initialize_Block_RAM.htm > Many designers are including the INIT values in the HDL to support RTL simulation and to have these values visible to designers who are viewing the code. A small correction to the article above. If you are using Synplify Pro, the 7.3.3 release now supports passing the INIT values using generics or defparams. This allows the INIT values and other component attributes to be entered only once for synthesis and simulation as a generic or defparam. It should be less error prone than remembering to change both the attribute for synthesis and the generic/defparam for simulation. Bob Synplicity FAE - Colorado/UtahArticle: 61806
Hi, I am using ISE5.1i...XST synthesis tool. At the end of synthesis, XST generates defualt timing report for 1 or 2 paths. How can i generate a timing report after synthesis for more than 100 paths? ie., as like .twr after Place and route. And How can i measure the time dealy between 2 specific points... Points could be FF,mux or any logic Thanks in advance. Regards, MuthuArticle: 61807
Hi How can I find path delay in Xilinx timing analyzer? AnjanArticle: 61808
hi,Jon I am working on ML300. Now i have generated the configuration file(top.bit) and tested some app in BRAM. I have maken the linux image from MontaVista 2.4.18.I don't know how to download the OS image into sdram and debug the OS. Can it be downloaded to sdram with the Parallel Cable IV through JTAG interface? I hear someone says the OS will be combined with .bit into .ace file. Counld you give me some hints?Article: 61809
Hi, I'm looking for a PCMCIA FPGA card to implement my design. One company I found has this kind of product, called Wildcard. (www.annapmicro.com) Has anyone used this before? How's the card and the development environment? Does anyone know anyother companies that has pcmcia fpga cards? And do they work on Windows CE devices? thanx a lot StanleyArticle: 61810
Hi, I've almost finished the RTL for the design. The question I have is how do I know how large my design is before selecting a FPGA? thank you StanleyArticle: 61812
Floorplanner pops-up a message which states it does not support RPM_GRID. What does this mean? 1- Any RPM using RPM_GRID will not be displayed with true placement? 2- It cannot extract and store RPM's with RPM_GRID? (from, say, a flat design from which logic is selected in order to extract RPM placement data. 3- What is the purpose of showing this message other than the obvious? ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 61813
So...if you try to create anything other than the trivial sample RPM's floating about you very quickly discover that your logic can jump all over the place. This is particularly true of non-slice resources. So... you read a little blurb about RPM_GRID. Which isn't documented very well at all. So... you try it. And... all sorts of things begin to break. Naturally, after burning many hours, questions arise: If you use RPM_GRID at a given hierarchical level, must every RPM'd submodule instantiated in the lower hierarchies of the module in question also use RPM_GRID? Can you mix RPM_GRID and non-RPM_GRID coordinates within a module? A recommendation I found states that RPM_GRID might be better for heterogeneous RPM's that include such things as multipliers and that non-RPM_GRID is more appropriate for RPM's that are limited to slice logic. True? If you wanted to RPM something like this: [LUT][FF] [LUT][FF] [LUT] [MULT] [LUT][FF] [LUT][FF] [LUT] [LUT][FF] [LUT][FF] [LUT] [LUT][FF] [LUT][FF] [LUT] Before RPM_GRID you might set the RLOC's something like this: (simplified notation just to put the idea across) X0Y3 X1Y3 X2Y3 X0Y0 X0Y2 X1Y2 X2Y2 X0Y1 X1Y1 X2Y1 X0Y0 X1Y0 X2Y0 Now, if you instantiate this RPM several times most primitives will do OK, but it seems that the multiplier RLOC is distorted because the tools apply the same math as they do to other components. So, everything stops and you have to figure it out. How does one deal with this without resorting to RPM_GRID, which does not seem ready for prime time (see Floorplanner message). -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 61814
by trial and error.. Just place it and see.. start with a 150 and then go up or down as required. <sc01@hotmail.com> wrote in message news:Uisib.4367$zw4.3042@nwrdny01.gnilink.net... > Hi, > I've almost finished the RTL for the design. > The question I have is how do I know how large my design is before selecting a FPGA? > > thank you > > Stanley > >Article: 61815
Hi all, I'm wondering how to synthesize the VHDL from SOPC Builder of quartus 2.2 with Leonardo. Indeed, I would like to perform a synthesis separated from the Quartus P&R for a course (I have a limited time and doing the both is far too long). The idea is to provide students an already synthesized system : they just have to complete some peripherals so I can pre-synthesize the whole system , students do synthesize peripherals and the pieces are put together for P&R with quartus. The problem is that with Quartus 2.2, the VHDL produced by SOPC builder is synthesized and P&R by Quartus which double the process time. It's also quite difficult to feed leonardo with the produced VHDL because it contains Quartus pragmas such as --synthesis read_comments_as_HDL on So, I have two solutions : - Perform the synthesis with Quartus and save the result But how can it be done ? I have'nt seen the corresponding menu - Perform the synthesis with Leonardo It would need to remove comments (not difficult with awk) but I would have to deal with the lpm macros. How can I force leonardo to keep their names ? - Extract entities containing pragmas (awk) and leave them for Quartus, the rest would be synthesized with leonardo. But it would be difficult to manage the project... What do you think about that ? Do you have suggestions ? FOR ALTERA ENGINEERS : the former solution with separate vhdl files containing lpm macros was much more easier to deal with.... It's a typical case where upgrade may transform to downgrade ... Thanks a lotfor your ideasArticle: 61816
I have a design with a JTAG chain consisting of APEXII, EPC16UC88, MERCURY, EPC16UC88. I have built the design 3 previous times and been able to program my boards, no problems. Now I have 3 boards, one works fine, one will not accept a .POF file into the second EPC16 part, and the third will not accept a .POF into either of the EPC16 parts. What happens is Quartus starts erasing the part and after about 45 seconds kicks out with an error "Error Operation Failed" I would think I have a bad part, but that would mean I have 3 bad parts out of six (and they are ball grids so not easy to swap out). I think the JTAG chain is OK, I can do .SOF programs and everything works great. Any ideas on what else to check or try, or could I have a batch of bad parts???? I have tried this under Quartus 2.8 and 3.0. I have also tried using a jam file under MaxPlus 10.2. I have tried it with different length cables from my parallel port, I have tried it with different Byte Blasters, and on different computers. ThanksArticle: 61817
Hi. I'm considering Xilinx LogiCORE PCI-X core, and Xilinx HalfBridge core for building a PCI-X bridge. Can anyone share experience with these cores for PCI bridge application ? Does these cores deal with the address translation from "type 1" to "type 0" ? ThankX NAHUMArticle: 61818
Here is a beginning. Look at your design: How many flip-flops, how many BlockRAMs, how many multipliers (if any), how many different clocks, and how many I/O? It should only take minutes to answer these questions. Then you look at the overview in the data sheet and select an FPGA that has at least what you need. Peter Alfke, Xilinx Applications ============================ sc01@hotmail.com wrote: > > Hi, > I've almost finished the RTL for the design. > The question I have is how do I know how large my design is before selecting a FPGA? > > thank you > > StanleyArticle: 61819
Would need about 30 pieces. Please respond to the email address if possible, if you actually have some - thank you. This is for a rebuild of a project done in 1993; a redesign is not economically possible but the devices are long obsolete. Peter. -- Return address is invalid to help stop junk mail. E-mail replies to peter4400@peter2000XY.co.uk but remove the X and the Y. Please do NOT copy usenet posts to email - it is NOT necessary.Article: 61820
Hi, I have been debugging a software application running in an Altera APEX device with Nios 32 (including OCI-Core) via JTAG with no problem at all. Now, I am trying to do the same with an ACEX (EP1K100FC256-2) with no success. The problem seems to be when the debugger tries to connect to the remote target via JTAG. After issuing a "nios-debug" command under SOPC Builder shell I get the following error: "mdi error: found 0 devices instead of 1". It seems as the "nios-debug" script supplied by Altera doesn't recognize ACEX devices, but not quite sure about. Any idea? What is more, any of you have ever debugged software via JTAG with an ACEX? Thank you very much in advance. JoeArticle: 61821
"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:N9uib.745$S06.6@newssvr27.news.prodigy.com... <large snip> > Now, if you instantiate this RPM several times most primitives will do OK, > but it seems that the multiplier RLOC is distorted because the tools apply > the same math as they do to other components. So, everything stops and you > have to figure it out. > > How does one deal with this without resorting to RPM_GRID, which does not > seem ready for prime time (see Floorplanner message). Martin, Perhaps it's Floorplanner's ability to deal with RPM_GRIDs that's not ready for prime time? I had great success with my manual UCF approach to get my registers placed relative to the BlockRAMs. The RPM_GRID attribute is effectively assigned per-macro. You can't have one macro with a mix of RPM_GRID and standard XY resource gridding. I didn't touch Floorplanner to get my grid locations. I went straight to FPGA Editor to get the grid locations; you can find those by clicking on a slice or a multiplier and the RPM_GRID XnYm location is displayed with the other information for that resource. If you want to have macros relative to multipliers or BlockRAMs, you really have to resort to RPM_GRID or absolute LOCs. I don't like LOCs for anything outside of I/O related logic. Check out the XIlinx application note XAPP416 ( http://www.xilinx.com/bvdocs/appnotes/xapp416.pdf ) which helped me get my RPM_GRID working for the BlockRAMs. The same info should apply directly to the multipliers. - John_HArticle: 61822
Hi, I'm trying to implement a design where signals are fed to the Xilinx CoolRunner XPLA3 CPLD from a USB card. All signals are controlled via JavaScript and ActiveX control (including clock), thus making timing between signals being adjustable - from 100 miliseconds to seconds. There are 4 signals - DataIn, Reset, Ready, and Clock. As tested in the simulator, after the first clock cycle when reset is 0 and ready is 1, the outputs should be 1. However, in reality, all outputs remain 0. I have tested the board and the connections to the CPLD with a test lead - all the signals reach it. The CPLD is powered by 3.3V and the signals are 5V (all withing specs, as far as I see), and can be programmed without a problem. The clock signal is connected to pin 2 of the CPLD. Can someone explain why I am facing this problem, or has any solution for it? -Gregory TitievskyArticle: 61823
There is a date coded license file did you ever get that? So the HOTMan software allows you to download remotely and it has a "plugin" technology that allows you to get inbetween the delievery of the bitstream and the final destination. It has examples of how to use the Xilinx download cable and it also has Jtag functions. HOTMan also lets you make your own commands so you can build test software for your system. With just a few lines of code you can deliver your bitstream run some kind of test and then the software will ship back a message that you create. And it will work over the net so you can run it from your office and download into the lab. Let me know if you have problems. Steve "Sriram" <machosri@yahoo.com> wrote in message news:56210527.0310101012.5ec866c2@posting.google.com... > Hi , > I downloaded HOTman from Virtual Computing corporation around April'03 > but when I tried to open the console now it didnt work.Also I went > through the procedure again for running HOTman the first time and > still couldnt get the GUI to appear.I got the error message "Could not > find main class" when I double clicked on the Hotman.jar file. > > Is this a problem of JRE or is the software HOTman no longer working. > I also tried to download the evaluation edition again from the VCC > website and couldnt do it(got an internal server error problem).Have > they closed the site ? > > Has anybody faced similar problems with HOTman? > Also to implement programs from C directly to FPGA would Celoxica's > HandelC oriented DK1-design Suite be the next best option,if I cant > get HOTman working. > > > Kindly do help me out on the above. > > Thanks , > SriramArticle: 61824
Peter, (nice to hear from you again!). The part is still available through the ordinary Xilinx sales channel. So you can enter the order with your favorite distributor. If you have problems, contact me directly. Peter Alfke (peter@xilinx.com) ============================== Peter wrote: > > Would need about 30 pieces. > > Please respond to the email address if possible, if you actually have > some - thank you. > > This is for a rebuild of a project done in 1993; a redesign is not > economically possible but the devices are long obsolete. > > Peter. > -- > Return address is invalid to help stop junk mail. > E-mail replies to peter4400@peter2000XY.co.uk but remove the X and the Y. > Please do NOT copy usenet posts to email - it is NOT necessary.
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