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Nagaraj wrote: > > Hi, > Thank you for the reply. I also calculated for MTBF with XAPP094 > and 4000 series device. But I wanted it for Virtex-E. As you have > mentioned i assume that whatever MTBF I calculate for XC4000 series > will be less than for that for newer device like Virtex-E. > I have one more question. What do you mean by "allowing 1 ns of > slack time" ? > This slack time part i am not clear for my design. Could you give some > detailed information about knowing alloable slack time for my design? The slack time is just the amount of extra settling time you have that is more than the setup time required by the end FF. Or more quantitatively, you add up the clock to output on the starting FF, the path delays, the setup time on the destination FF and any clock delay or jitter which will work against you. Then subtract this from your clock cycle time and what it left is called "slack time". This is the amount of time you have for metastability to settle out. To get this amount of slack time without having to inspect the timing reports by hand, you can specifiy the timing of these paths in your constraints file. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 50601
"Tim" <tim@rockylogic.com.nooospam.com> writes: > Now there is yet another implementation of the Logic Analyzer > part, with some extra stuff added. You can check out > www.rockylogic.com for the Ant8 - a 500MSample/s USB-connected > (USB-powered) Logic Analyzer. Nice, and the price is quite attractive. Does it support adjustable thresholds? If not, what are the standard thresholds? Any plans for a unit with more channels?Article: 50602
Eric Smith wrote: > > "Tim" <tim@rockylogic.com.nooospam.com> writes: > > Now there is yet another implementation of the Logic Analyzer > > part, with some extra stuff added. You can check out > > www.rockylogic.com for the Ant8 - a 500MSample/s USB-connected > > (USB-powered) Logic Analyzer. > > Nice, and the price is quite attractive. > > Does it support adjustable thresholds? If not, what are the > standard thresholds? > > Any plans for a unit with more channels? I would second that. Not only are more channels needed, a better way to connect to the target is needed. Microclips went out with DIPs. On our last board we added 20 pin debug connectors which were pin compatible with HP logic analyzer probes when used with their adapters. This was very nice since it allowed us to connect to the various busses on the board by simply plugging in the adapter. Also, does the software allow more than one pod to be used with a common display? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 50603
Nagaraj wrote: > > I have one more question. What do you mean by "allowing 1 ns of > slack time" ? Rickman has answered this already. Let me just add that "slack time" is the most important parameter. But it is, luckily, under user control. Metastability is not a "yes/no" condition. A flip-flop can become more or less metastable, and thus recover either very fast or considerably slower. MTBF is, therefore, a function of the extra time available for the flip-flop to recover to its "final" stable state. The more time is available, the longer is the MTBF. As Xapp094 and also the recent TechXclusive shows, MTBF varies over more than 10 decimal orders of magnitude, depending on the available slack time. Peter Alfke, Xilinx ApplicationsArticle: 50604
I'm not clear how you get a timing violation during synthesis because the placement is not known and this dictates the clock and data delay. Can you supply the warning message and the offending chunck of HDL? Regards prashantj@usa.net (Prashant) wrote in message news:<ea62e09.0212110917.1e21ae9f@posting.google.com>... > Hi all, > I have been struggling with a problem for nearly a month now. I have a > small piece of code which gives hold time violations when its > synthesized in Quartus II. But if I synthesize and complete the > fitting of the design, there are no hold time violations. Post fitting > simulations dont show any violations either. Has anyone see such > behavior in their designs ? Is this a problem and if so, what needs to > be done to fix it ? > > Thanks, > PrashantArticle: 50605
I think you're on a wild goose chase with the metasability stuff. The solution you are going to use is to have just one clock and then use the other edge sensitive signal to generate a synchronous pulse (via a synchronous edge detector) and use that as an input. In verilog an edge detector looks something like this always @(posedge clk or negedge reset) if (!reset) begin delay1<=0;delay2<=0;pulse<=0; end else begin delay1<=myinput; delay2<=delay1; pulse<=delay1&!delay2; end If you take the approach that the circuit just has to work and the warnings don't matter, you will be limited in the size of the designs you can pursue. Beyond a certain size, you have to trust your tools implicitly. Lots of fun. Regards President, Quadrature Peripherals Altera, Xilinx and Digital Design Consulting email: kayrock66@yahoo.com http://fpga.tripod.com ----------------------------------------------------------------------------- "Lorenzo Lutti" <lorenzo.lutti@DOHtiscalinet.it> wrote in message news:<xOmK9.14257$ab2.409682@news1.tin.it>... > "Lorenzo Lutti" <lorenzo.lutti@DOHtiscalinet.it> ha scritto nel messaggio > news:P6lK9.13754$ab2.391568@news1.tin.it... > > > clock edge overlap, I always get a FF setup violation and > > soon the > > simulation gets lost. I think this is unavoidable when you > > have to do with > > asynchronous signals. Or it isn't? [...] > > Looks like I'm entering in the painful world of metastabilities. I've read > some technical documentats but, as far as I've undestood, the only true > answer could be given by the test of the "real" circuit. However it should > be very useful to have some idea of what will be the magnitude of problems > I'm going to have. > > Just a couple of questions (I hope they are less trivial than the last > ones): > > -In the Xilinx site I've found an interesting document (xapp094, "Metastable > recovery") which gives a statistical distribution of metastabilities' > duration for XC3000 and XC4000 family. Is there something similar for modern > FPGAs (for example I use a XC2S50-5)? Can I suppose they are equal or better > than XC4000? In my application I have an accettable extra delay of roughly > 4-5 ns, which gives very different MTBF between the various models. > > -Is there a way to instruct ModelSim to simulate the metastabilities, i.e. > to set the extimated maximum metastability duration as a parameter so that > it will mark the signals as undefined only when really needed? > > -Is there a way to define some constraints that take account of this > problem? I suppose it should be enough to impose a longer clock-to-setup > time for the "critical" flip-flops, but I don't know how to do it.Article: 50606
And what are you using the 80 tiny pieces of ram for? The reason I ask is that in digital design there are often many ways to solve the same problem. You take the strengths and weaknesses of your implimentation technology into account when you choose from the various options. BTW, I commend your retargeting effort, this is the only effective way I've seen to getting price breaks on expensive parts like FPGAs. I love to dual footprint my designs when its at all possible and price sensitive. Regards President, Quadrature Peripherals Altera, Xilinx and Digital Design Consulting email: kayrock66@yahoo.com http://fpga.tripod.com ----------------------------------------------------------------------------- fpga_wonderkid@yahoo.com (FPGA Wonderkid) wrote in message news:<23069c63.0212130245.4dac83e8@posting.google.com>... > Hi- I use 16 bits of memory (16X1, 16 deep, 1 wide) and 80 nos for > different instances. > > > > > kayrock66@yahoo.com (Jay) wrote in message news:<d049f91b.0212121903.6bba1d63@posting.google.com>... > > First, what are your 80 16X1 rams used for, and in what configuration > > (e.g. 80 wide by 16 deep, etc..) > > > > fpga_wonderkid@yahoo.com (FPGA Wonderkid) wrote in message news:<23069c63.0212120205.478a78c@posting.google.com>... > > > Hi, I am planning to use an Altera Cyclone/ACEX device in place of my > > > existing XC2S200E device. However, as I use lot of distributed RAM, I > > > cannot easily go to Cyclone/ACEX as they do not support distributed > > > RAM like Xilinx. Can anyone tell me how to efficiently convert the > > > spartan-2e distributed RAM primitives into Cyclone/ACEX block ram > > > architecture. What i need to know is how to convert 80 nos of 16X1 > > > RAM, I have implemented in spartan-2e to cyclone architecture w/o > > > consuming too much space. > > > > > > > > > Thanks!Article: 50607
Are you using Chipscope? President, Quadrature Peripherals Altera, Xilinx and Digital Design Consulting email: kayrock66@yahoo.com http://fpga.tripod.com ----------------------------------------------------------------------------- "Tim" <tim@rockylogic.com.nooospam.com> wrote in message news:<atd95l$af1$1$8300dec7@news.demon.co.uk>... > Most readers of this group will have their copy of the > 1988 Xilinx "Programmable Gate Array Data Book" :-) This > is the edition which has neither the year number nor > "First Edition" on the spine. An application brief by Brad > Fawcett (hello, Brad) on page 6-51 of that book is for a > "Logic Analyzer/In-Circuit Emulator", and Brad's suggestion > has been implemented many times in the intervening 15 years. > > Now there is yet another implementation of the Logic Analyzer > part, with some extra stuff added. You can check out > www.rockylogic.com for the Ant8 - a 500MSample/s USB-connected > (USB-powered) Logic Analyzer. > > By the erudite standards of the group, the Ant8 is nothing > to get excited about. The hardest part was cooking up a > flexible state machine implementation which allows for a > range of fancy triggering modes. And it turns out that > just about everyone is only interested in triggering on a > single rising edge. Sigh. > > The rest of the development was just engineering, and it is > well known that any fool can do that ;-) > > Pls hit me here with any technical questions of general > interest - I promise to keep away from product pitches. > > Thanks > TimArticle: 50608
I think it will but the bus hold circuit will be fighting the transition of your already weak input. Regards President, Quadrature Peripherals Altera, Xilinx and Digital Design Consulting email: kayrock66@yahoo.com http://fpga.tripod.com ----------------------------------------------------------------------------- qiu.xiaoyong@zte.com.cn (wosiqiu) wrote in message news:<b053419c.0212122249.bfab7cd@posting.google.com>... > Hi, > I am using the XC95144XL in my design.Now,I configure a pin as > input,but in fact I make it floated externally.I think its bus keeper > will insure I can get a working-well logic '1' signal. Can anybody > tell me whether I am true or not?Thanks. > Regards, > wosiqiuArticle: 50610
I am trying to figure out how to get clock enable flipflops to pack into
IOBs (in an XCV1000E). I am attempting this with ISE4.2 and VHDL.
Getting input and output signals into the IOB works fine.
This is on an input/output bus. Initially, a common clocked signal went
to all the IOBs. ISE did not replicate it. So I tried replicating it in
code, but the Xilinx tools seem to have recognised the duplication and
optimized it out. I tried several different directives in an attempt to
stop that, but the tools seem to insist. Here are several attributes
that I currently am trying. Any ideas are appreciated.
attribute iob: string;
attribute iob of Tn_array: label is "true";
attribute keep: string;
attribute keep of Tn_D: signal is "true";
attribute noreduce: string;
attribute noreduce of Tn_D: signal is "yes";
begin
-- This is done to attempt to force the output enable signals into
-- the IOB latches.
FD_array: for i in 0 to 31 generate
FD(i) <= DQ(i) when Tn_D(i) = '0' else 'Z';
end generate;
Tn_array: for i in 0 to 31 generate
Tn_LATCH: process (C)
begin
if rising_edge(C) then
Tn_D(i) <= Tn;
end if;
end process Tn_LATCH;
end generate;
--
My real email is akamail.com@dclark (or something like that).
Article: 50611>Rickman has answered this already. Let me just add that "slack time" is the most >important parameter. But it is, luckily, under user control. I'd go farther than that: You don't understand metastability until you know what slack time means. It's also very hard to get real/honest MTBF numbers if you don't know about slack time. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 50612
Duane, Having just been faced with similar challenges today - - Check out the Xilinx answer database, record 2207, for a complete list of "rules" regarding IOB packing of registers. I think you need to lose the "keep" attribute on the tristate enable signals as that will prevent the enable registers from going into the IOB. Also you don't mention what your input/output signals are being clocked with. All of the registers that go into a given IOB have to use the same clock and CE sources. Hope this helps. Roger Green "Duane Clark" <junkmail@junkmail.com> wrote in message news:3DFA79B3.5050303@junkmail.com... > I am trying to figure out how to get clock enable flipflops to pack into > IOBs (in an XCV1000E). I am attempting this with ISE4.2 and VHDL. > Getting input and output signals into the IOB works fine. > > This is on an input/output bus. Initially, a common clocked signal went > to all the IOBs. ISE did not replicate it. So I tried replicating it in > code, but the Xilinx tools seem to have recognised the duplication and > optimized it out. I tried several different directives in an attempt to > stop that, but the tools seem to insist. Here are several attributes > that I currently am trying. Any ideas are appreciated. > > attribute iob: string; > attribute iob of Tn_array: label is "true"; > attribute keep: string; > attribute keep of Tn_D: signal is "true"; > attribute noreduce: string; > attribute noreduce of Tn_D: signal is "yes"; > > begin > > -- This is done to attempt to force the output enable signals into > -- the IOB latches. > FD_array: for i in 0 to 31 generate > FD(i) <= DQ(i) when Tn_D(i) = '0' else 'Z'; > end generate; > > Tn_array: for i in 0 to 31 generate > Tn_LATCH: process (C) > begin > if rising_edge(C) then > Tn_D(i) <= Tn; > end if; > end process Tn_LATCH; > end generate; > > -- > My real email is akamail.com@dclark (or something like that). >Article: 50613
In article <atd95l$af1$1$8300dec7@news.demon.co.uk>, Tim <tim@rockylogic.com.nooospam.com> wrote: >Now there is yet another implementation of the Logic Analyzer >part, with some extra stuff added. You can check out >www.rockylogic.com for the Ant8 - a 500MSample/s USB-connected >(USB-powered) Logic Analyzer. Nifty. Out of curiosity, what's the FPGA and how do you handle config (just a config prom?). -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 50614
Yes,I think I can get a logic '1' signal. But I'm not sure wether the
noise can make some disturbance or not. In the datasheet of APEX II, I
read this:
Each APEX II device I/O pin provides an optional bus-hold feature.
When
this feature is enabled for an I/O pin, the bus-hold circuitry weakly
holds
the signal at its last driven state. By holding the last driven state
of the pin
until the next input signal is present, the bus-hold feature
eliminates the
need to add external pull-up or pull-down resistors to hold a signal
level
when the bus is tri-stated. The bus-hold circuitry also pulls undriven
pins
away from the input threshold voltage where noise can cause unintended
high-frequency switching.
So,I think in APEX II the buskeeper will be a natural pullup.I'm
not sure in XC95144XL if it's the same,and how in APEX II the bus
keeper avoid the disturbance of noise.
Regards.
wosiqiu
Article: 50615
saupal@indiatimes.com (Saurabh Pal) wrote in message news:<62ef09ee.0212120101.12969041@posting.google.com>...
> Hi,
>
> Following is a Handel-C program which reads a 128-bit data,
> copies the data to a buffer and, finally, the buffer contents are
> given to the output pins.
>
> The data input/output interface is 32-bit unidirectional.
>
> After implementing the given design on a Xilinx Virtex-II FPGA,
> I'm getting a clock speed of 126.374MHz.
>
> How can a better clock speed can be achieved?
>
> Any assistance appreciated.
>
> Regards,
> Saurabh Pal
Hi Saurabh,
We've just finished evaluating Handel-C and found it
to be an excellent tool. I was happily surprised to
find the circuits that it constructs are reasonably
efficient. Coding for speed takes good knowledge of
what the tool produces. To get an idea of this,
have a look at the app note "The Technology Behind DK1"
on their web site at:
http://www.celoxica.com/technical_library/application_notes/default.asp
A remarkable thing about Handel-C is that the same
sort of optimizations you would use when coding
standard C often improve designs coded in Handel-C.
In your case, loop unrolling helps.
Instead of indexing through the registers,
for your getData proc use:
macro proc getData(data)
{
par {
data[0][0] = DinBus.in[31:24];
data[1][0] = DinBus.in[23:16];
data[2][0] = DinBus.in[15:8];
data[3][0] = DinBus.in[7:0];
}
.
.
.
par {
data[0][3] = DinBus.in[31:24];
data[1][3] = DinBus.in[23:16];
data[2][3] = DinBus.in[15:8];
data[3][3] = DinBus.in[7:0];
}
}
This eliminates the decoding implied by the indexed
accesses, and removes the index counter too.
Do the same thing for your putData proc:
macro proc putData(data)
{
bus_out = data[0][0] @ data[1][0] @ data[2][0] @ data[3][0];
bus_out = data[0][1] @ data[1][1] @ data[2][1] @ data[3][1];
bus_out = data[0][2] @ data[1][2] @ data[2][2] @ data[3][2];
bus_out = data[0][3] @ data[1][3] @ data[2][3] @ data[3][3];
}
Also note that I've taken out the intermediary
signal definition you were using. If you look
closely at how signals are defined to operate,
you can see that they may introduce extra logic.
These two simple changes were enough to bump the
performance up to 197 MHz (on XC2V3000-5),
without any floorplanning. You can go farther and
try constraining your input and output pins,
if they are not already committed. I simply went
down one side of the device, and assigned inputs
and outputs together:
O31
I31
O30
I30
etc.
and this took the speed up to almost 225 MHz:
Constraint | Requested | Actual | Logic
TS_WT1_Speed_1 = PERIOD TIMEGRP "WT1_Spee | 4.000ns | 4.450ns | 2
I haven't looked at it, don't even know if this is optimum
pinning. It looks like you are reversing byte
order between input and output, so it might help if the
pins were placed to match that.
Note that there are still two logic layers left. The circuit you
want is very simple, and would not involve more than
one logic layer if hand coded, except for the output mux.
The output mux can be pipelined to reduce logic levels
(if you can tolerate the delay). (The output mux could
also be eliminated entirely, if you treat your input and
output routines as shift registers.)
The synchronization between the three processes in your
main loop may be also be contributing to the 2 logic levels.
Adding three delays after the parallel part of your
Copy proc (making each process explicitly 4 cycles
long) seemed to help timing a little, but I don't
know if this was coincidence or not.
(By the way, double check your logic, you may want
to have the three delays prior to the copy, to do
the copy on the fourth cycle of the loop instead
of the first).
Short of instanciating (interfacing in H-C speak) the FFs
and doing a structural design, I don't know how to get the
logic down to one level in H-C,
Also check your effort levels in the back end place/route
tools. Simply by raising these you may get better results:
Constraint | Requested | Actual | Logic
* TS_WT1_Speed_1 = PERIOD TIMEGRP "WT1_Spee | 3.000ns | 4.005ns | 2
250 MHz is fairly good, for a circuit compiled from C code.
As everyone else has said, how fast do you need?
Hope something here was of help.
Regards,
John
Article: 50616Martin Schoeberl <martin.schoeberl@chello.at> wrote: : I think javac does no optimization to make it easier for JIT to compile JVM : stack code to a register machine. And the JIT assumes this simple minded : stack code for it's optimization. Javac does indeed do no optimisation. It /used/ to do some inlining to small function calls - but it was decided that the place for optimising was the JIT - and the best thing to feed it was unoptimised bytecode - since often optimising early confused the JIT, and slowed everything down. My perspective is that a compiler should produce results as fast as possible. Squeezing and performance optimisation can be done with a postprocessor - if needed. : I was looking arund to find some byte code optimizer, but have only found : this 'obfuscators'. No optimizer for the stack code. There are optimisers and squeezers out there. Only a few get around to messing with the stack. They claim to do things like "optimizing local variable allocation", though. Try: Java class file optimization and compression tools http://www.geocities.com/marcoschmidt.geo/java-class-file-optimizers.html JAX: http://www.alphaworks.ibm.com/tech/jax/ ...and its bigger brother from WebSphere Studio Device Developer; BLOAT: The Bytecode-Level Optimizer and Analysis Tool http://www.cs.purdue.edu/s3/projects/bloat/ JArg: Java ARchive Grinder http://jarg.sourceforge.net/ Jode: http://jode.sourceforge.net/ JavaGO: http://www.garret.ru/~knizhnik/javago/ReadMe.htm -- __________ |im |yler http://timtyler.org/ tim@tt1.orgArticle: 50617
Martin Schoeberl <martin.schoeberl@chello.at> wrote: :> The advantage of Forth is that it's well-suited as-is for running :> hardware, and once you have it running Java can be implemented on top. :> I would rather use Forth as a machine language than Java bytecodes. : Isn't Forth a 16 bit system? Building a 32 bit JVM on top of this : would be not very efficient. Forth is not inherently 16-bit. I'd be inclined to build a bytecode interpreter onto the metal, though. That is - by and large - what others seem to be doing. ARM's effort in the area - for example: http://www.arm.com/armtech/jazelle?OpenDocument -- __________ |im |yler http://timtyler.org/ tim@tt1.orgArticle: 50618
Is it possible to generate an internal clock signal in the range 20MHz-30MHz inside the Spartan2 ? Thanks, RobArticle: 50619
It's possible to get more than 64 colors out of a simple 6 resistor DAC by dithering the colors using a high speed clock. For instance if the VGA output is at 25MHz alternate between two colors at 50MHz. It's a good idea to alternate between the colors according to the scan line as well to avoid stripes in the output. RobArticle: 50620
Peter Alfke wrote: > Nagaraj wrote: > > > > > I have one more question. What do you mean by "allowing 1 ns of > > slack time" ? > > Rickman has answered this already. Let me just add that "slack time" is the most > important parameter. But it is, luckily, under user control. > > Metastability is not a "yes/no" condition. A flip-flop can become more or less > metastable, and thus recover either very fast or considerably slower. MTBF is, therefore, > a function of the extra time available for the flip-flop to recover to its "final" stable > state. The more time is available, the longer is the MTBF. > As Xapp094 and also the recent TechXclusive shows, MTBF varies over more than 10 decimal > orders of magnitude, depending on the available slack time. > > Peter Alfke, Xilinx Applications One slightly annoying thing about the Xilinx tools is that it doesn't allow for a derived timespec to use the original time +/- some constant. What I'd like to be able to do is - TS_PeriodSpec = ........ XXXnsec; TS_MetastabSpec = ....... TS_PeriodSpec - ExtraSlack; Once again Perl rides to the rescue though.Article: 50621
Hello All. I am getting a strange error on the Xilinx 4.2 SP2 BitGen when it is doing a DRC. After I insert the Chipscope (4.1) ILA into the design via Core Inserter, then I am getting the following error on Bitgen: ERROR:DesignRules:368 - Netcheck: Sourceless. Net U_icon/icon_1/u_icon_core/tap/tap/TDO2 has no source. I don't understand why this is occurring due to Chipscope, and I don't think it is a serious problem. The only thing is that it is preventing me from generating a bit file. Does anyone have any suggestions on how to deal with this? Also, I was thinking of upgrading to Chipscope 5.1, but I cannot seem to get it to open on my computer. I even tried the Chipscope 5.1 version that uses the JRE 1.04 (as discussed in the support pages on the Xilinx website) but it still does not allow me to open the Inserter. Has anyone had this issue either? strut911Article: 50624
Treshold seems to be fixed at 1.4V (see http://www.rockylogic.com/products/antspec.html) More channels for me too, please. "Eric Smith" <eric-no-spam-for-me@brouhaha.com> wrote in message news:qhn0n9myt0.fsf@ruckus.brouhaha.com... > "Tim" <tim@rockylogic.com.nooospam.com> writes: > > Now there is yet another implementation of the Logic Analyzer > > part, with some extra stuff added. You can check out > > www.rockylogic.com for the Ant8 - a 500MSample/s USB-connected > > (USB-powered) Logic Analyzer. > > Nice, and the price is quite attractive. > > Does it support adjustable thresholds? If not, what are the > standard thresholds? > > Any plans for a unit with more channels?
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