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"Tim" <tim@rockylogic.com.nooospam.com> wrote in message news:<at8md9$rvg$1$8300dec7@news.demon.co.uk>... > > Certainly this is not commercially available in the same > > way that other processors are, for example, the 8051 or Coldfire, > > etc... Where can I get a current Transputer? > > Available like the parts you mention, but the MOQ is a few orders > of magnitude larger. A little like XC2S30-6VQ100C (Meow) do a hunt on the ST website for ST20. It is embedded into their DVB decoders eg the ST55xx series. Garry AllenArticle: 50676
We've just finished an evaluation of the DK tool from Celoxica for Virtex2Pro. It's pretty comprehensive with support for cosimulation and some neat partitioning discipline. We're looking for details on how it fits with the Xilinx tools but the embedded offering from Wind River work well with the DK tool. Take a look at the Celoxica site or get more information from Xilinx at http://www.xilinx.com/publications/xcellonline/partners/xc_pdf/xc_celoxica44.pdf ED Austin Lesea <austin.lesea@xilinx.com> wrote in message news:<3DFE2F71.76FB1AB8@xilinx.com>... > Austin, > > The following link: > > http://toolbox.xilinx.com/docsan/xilinx5/data/docs/sim/sim0047_9.html > > discusses the Smart/Swift models which represent the 405ppc in encrypted HDL > code for simulation. > > Austin > > Austin Franklin wrote: > > > > Right now the software support is all there, along with the hardware > > support. > > > > Hi Austin, > > > > How does simulation work? When I simulate my FPGA, how do I also get it to > > simulate the processor/software etc.? > > > > Regards, > > > > AustinArticle: 50677
>Let me make a clarification, when i say data could be written simultaneosly >i want data at that location increamented by the value of output data from >component(s). >So let say if the memory location FF has a value 5 in it. 13 out >of 16 components could be trying to increament location FF with their >particular output. In software you make them wait by using a semaphore. >What could be a very fast way of doing that in Logic. There are several ways to do that - all the ones I know about are used by the low-level parts of software to make locks. Building locks is a common/famous computer science problem. Might be interesting to check text books. One way is to implement a read-modify-write type interface to the memory system. If two (or more) CPUs are trying to access the same location, one wins, and keeps control of that location long enough to do the add and write back. This usually needs an add-to-memory type instruction. Note that the granularity of locking can be on the whole bank/box of memory. You don't have to keep track of the location within the box if you don't want to, but it might help effeciency if adds take a long time. The IBM-360 family had a test-and-set instruction. It set a byte of memory to FF and also set the condition codes based on the old contents. There are similar schemes that do a swap with memory - write something and return what was at that location. Another way is the load-locked, store-conditional pair of instructions. The load-locked remembers the address. A following store-conditional doesn't do anything if some other CPU has written to that location since the load happened. You also need some way to figure out if the store worked, perhaps by loading that word and checking. (which doesn't work in this case, since both CPUs could be adding the save value) You might consider avoiding the problem. For example, allocate a separate block of memory for each of the 16 sources so each one can blindly update its block without checking to see if anybody else is also writing there. When you want to know the answer, you have to do 16 loads and add them up. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 50678
> Let me make a clarification, when i say data could be written simultaneosly > i want data at that location increamented by the value of output data from > component(s). > So let say if the memory location FF has a value 5 in it. 13 out > of 16 components could be trying to increament location FF with their > particular output. In software you make them wait by using a semaphore. > What could be a very fast way of doing that in Logic. Pipeline the design. This sounds like a read-modify write cycle assuming you want to add onto an existing value in the memory location. This would take two cycles by itself. Since you haven't specified a frequency, I'm guessing you just want to do this operation as darn fast as you possibly can. Since this sounds basically like a 16 input adder, it'd probably be best to pipeline the design somehow; because the 16 input adder will probably reduce into four or five logic levels anyway which pushes the operation into two or more clock cycles at the highest operating frequency. (With pipelining the inputs can be handled in multiple clock cycles - eg add 8 groups of two inputs together in one cycle, those four groups of outputs in the next, etc.) With pipelining it should be possible to reduce the operation to effectively single cycle operation, but there may be a latency of six or seven clock cycles between when the addition enters the pipeline and when the result is actually written. Depending on the software, it might be possible to hide this latency as some time is probably required for the software to fetch new instructions and data values. Another alternative is to add to several different memory locations successively to fill the pipeline with data from different addresses, before referencing the first address again. You may also want to synchronize the components using hardware signaling so that they all attempt to access the memory location at the same time. Rob www.birdcomputer.caArticle: 50679
Garry Allen wrote: > > "Tim" <tim@rockylogic.com.nooospam.com> wrote in message news:<at8md9$rvg$1$8300dec7@news.demon.co.uk>... > > > > Certainly this is not commercially available in the same > > > way that other processors are, for example, the 8051 or Coldfire, > > > etc... Where can I get a current Transputer? > > > > Available like the parts you mention, but the MOQ is a few orders > > of magnitude larger. A little like XC2S30-6VQ100C (Meow) > > do a hunt on the ST website for ST20. It is embedded into their DVB > decoders eg the ST55xx series. > Garry Allen I will have to say that ST has one of the worst web sites for finding information that I have come across. Even knowing that I am looking for information on the ST20 series of processors, I could find info on nothing but the ASIC ST20GP6 chip. I found a page with a link for the ST20 core which was an invalid link. None of these pages seemed to have links back up the heirarchy to find similar related products. Searches on ST55 or DVB turned up nothing. I am amazed that ST puts up such a poor web site. So can you tell us what is noteworthy about this processor? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 50680
I am working on a design right now where the input clock feeds a CLKDLL which then feeds a BUFG and fans out to the rest of the design. In my post-route simulation, I am seeing flip flops that should be clocked by the global clock being clocked by such things as: instance_name/net_name/CLKINV which is output from an X_BUF instance. The input to the X_BUF is the global clock, but the output is skewed with respect to the input. Contrary to the name of the signal, the clock is not inverted. This is causing timing issues in my simulation and worries me. When I checked my synplicity synthesis schematic view, the correct clock was feeding the DFFs. Is this a Xilinx issue? I am using 4.2 SP2.Article: 50681
Hai all,
I haven't got the answer for my question.
I hope u have'nt understood.
My quest is what is the remedy for SEU in One Time PROM configured
XILINX FPGA?
Can I use Triple Redundancy logic?{will this acceptable for only SRAM
configured FPGA?
I refered the xilinx website and there is no information about ,what
OTP is made of in Xilinx FPGA?Is it metal-metal antifuse or CMOS based
memories or floating gate technique?If it is metal-metal antifuse
means no problem at all in space!!
Kindly reply my doubts
Thanx in advance.
Bye.
S.Thiruppathirajan
Peter Alfke <peter@xilinx.com> wrote in message news:<3DFA73CE.2EC14CF8@xilinx.com>...
> Josh Model wrote:
>
> > http://www.xilinx.com/products/military/radhardv.htm
> >
> > This should get you started, especially the SEU paper. Xilinx's FPGA's have
> > their configuration stored in an external PROM, probably OTP. To summarize,
> > suggested solutions involve Triple mode redundancy, and CRC checking the
> > bitstream using periodic repeated reconfiguration.
> >
> > One thing to watch out for, though, is current surges during
> > reconfiguration/power up.
>
> Just a slight correction:
> Yes, Xilinx FPGAs prior to Virtex-II have an Icc surge when first powering up.
> Virtex-II and later do NOT have that surge.
> More importantly:
> This surge does NEVER occur upon reconfiguration while Vcc is maintained, it
> only occurs when Vcc is (re)applied.
>
> Peter Alfke, XilinxApplications
Article: 50682"Hua Ai" <hai@ualberta.ca> wrote in message news:kLcL9.104004$Qr.2594636@news3.calgary.shaw.ca... > Hi, > > Recently I have to switch from ISE for windows to ISE for solaris, > everything works fine except that one of my design can not be synthesized in > ISE for solaris. The XST reports me the following message when it is doing > low level synthesis: > > Library "/CAD/tools/xilinx/data/librtl.xst" Consulted > INTERNAL_ERROR:Xst:cmain.c:3195:1.89.2.1 - To resolve this error, please > consult the Answers Database and other online resources at > http://support.xilinx.com > --> > > This design can be synthesized very well in ISE for windows. Though I can > still switch back to windows again, I am very curious about what happend > here. Could anyone give me some enlightenment? > Yes - look up the error in the Xilinx Answers database at http://support.xilinx.com See answer record #15476 regards Alan -- Alan Fitch [HDL Consultant] DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: alan.fitch@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com This e-mail and any attachments are confidential and Doulos Ltd. reserves all rights of privilege in respect thereof. It is intended for the use of the addressee only. If you are not the intended recipient please delete it from your system, any use, disclosure, or copying of this document is unauthorised. The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 50683
Hi, I have some questions about neural networks. Where do the geeks for this kind of thing hang out ? Thanks RobArticle: 50684
Hello All. I have a clock that is distributed largely throughout the design and in some places it gets gated in order latch incoming data on a data bus. Although I could design around it, the purpose is for verification of an ASIC. I would prefer to try and keep the design as intact as possible. So the question is: If I have a clock going to a non-clock resource, does the whole clock routing use non-clock nets? Or is it just that particular instance? This is very important to my design, and will dictate how much re-design effort will be required to port the ASIC to the FPGA. Thanks for any help. strut911Article: 50685
Hi, working for a software MPEG company that want to provide now hardware solutions as well, I would like to have your opinion about how implementing this new configuration. We found that a DSP only solution would not provide enough power. Something like a board with DSP plus FPGA(s) should be better. What is the process to go from evaluation to specification and then implementation of such a system ? We already have source code and technical knowledge in MPEG and DSP. From your point of view, is hiring FPGA specialized engineer mandatory ? I guess many of you would answer yes :) , but using consulting is an option too, and eventually learning ourselves (?). Is mixing C code (on DSP) and hardware optimized functions (on FPGA) a good choice for speed ? (versus C only on DSP) How long (man/month) should it take in this situation ? This is not the case, but suppose that the encoder is MPEG-4 video with DCT/IDCT/Motion Est/ and perhaps interpolation in FPGA. And as a starting point what would you recommend ? thanks, ErwanArticle: 50686
"Rob Finch" <robfinch@sympatico.ca> wrote in message news:4bEL9.2326$iQ3.613217@news20.bellglobal.com... > Hi, > > I have some questions about neural networks. Where do the geeks for this > kind of thing hang out ? comp.ai.neural-nets Leon -- Leon Heller, G1HSM leon_heller@hotmail.com http://www.geocities.com/leon_hellerArticle: 50687
"Rob Finch" <robfinch@sympatico.ca> wrote: "I have some questions about neural networks. Where do the geeks for this kind of thing hang out ?" Try comp.ai.neural-nets on Usenet. -Will Dwinnell, MBA http://will.dwinnell.comArticle: 50688
Hi!
In a design for a Xilinx XC5204 the place and route tool displays the
following warning:
Warning:Place:128 - IOPLACETASK: No I/O comps to place
But no errors. What does this mean? The IOBs are connected.
Thanks
Dirk Dörr
Article: 50689You forgot to say which synthesis tool you were using. They all do clock slightly differently. (You also forgot to mention what FPGA you were using.) But... If you're using 'Brand-X', go up to their web site and download their DDR SDRAM reference designs. In the documentation for one of them, there is details on how to use clock as a net. SH7. On 17 Dec 2002 03:54:24 -0800, strut911@hotmail.com (strut911) wrote: >Hello All. >I have a clock that is distributed largely throughout the design and >in some places it gets gated in order latch incoming data on a data >bus. Although I could design around it, the purpose is for >verification of an ASIC. I would prefer to try and keep the design as >intact as possible. So the question is: If I have a clock going to a >non-clock resource, does the whole clock routing use non-clock nets? >Or is it just that particular instance? This is very important to my >design, and will dictate how much re-design effort will be required to >port the ASIC to the FPGA. Thanks for any help. >strut911Article: 50691
Configuration time for the Altera ACEX 1K parts according to the data sheet is "less than 40ms" ... perhaps there is additional information but I can't seem to find it. I figure that the configuration time varies considerably between the EP1K10 and the EP1K100 but I would like to know how much time I should expect for the different size parts , does anyone have any real experience here and can give me some better numbers ? Thanks , Khim Bittle ( These parts are being designed into a video processor which needs to reload the array once or twice with a selected algorithm during a processing cycle ) (remove NOSPAM from header to reply ) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Clifton Systems Inc. 2240 Monument Rd. Myersville, MD 21773 USA 301-293-2317, 800-745-2931, fax 301-293-2326 khimbittle@cliftonsystems.com http://www.cliftonsystems.com Phoneline video surveillance products ... Standard / Custom / OEM. Embedded GPS / AVR / RTOS design & development. Electronic design consulting.Article: 50692
Khim Bittle wrote: > Configuration time for the Altera ACEX 1K parts according to the data > sheet is "less than 40ms" ... perhaps there is additional information > but I can't seem to find it. I figure that the configuration time > varies considerably between the EP1K10 and the EP1K100 but I would > like to know how much time I should expect for the different size > parts , does anyone have any real experience here and can give me some > better numbers ? Thanks , Khim Bittle > > ( These parts are being designed into a video processor which needs to > reload the array once or twice with a selected algorithm during a > processing cycle ) > I'm currentl investigating the embedded programmability of these devices. There are various influences to consider : The programming clock, JTAG can go up to 10MHz. The programming mode, parallel is probably faster than serial. Assuming that only the ones(or zeroes) have to be written, how full is your device ? Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 50693
In article <65edfa70.0212170408.1d1ad3d8@posting.google.com>, Erwan <lebrase@yahoo.fr> wrote: >Hi, > >working for a software MPEG company that want to provide now hardware >solutions as well, I would like to have your opinion about how >implementing this new configuration. We found that a DSP only solution >would not provide enough power. >Something like a board with DSP plus FPGA(s) should be better. >What is the process to go from evaluation to specification and then >implementation of such a system ? We already have source code and >technical knowledge in MPEG and DSP. You would probably do better with FPGA only, or FPGA and uP (something more conventionally programmable), although it depends on the area and cost model. >From your point of view, is hiring FPGA specialized engineer mandatory >? I guess many of you would answer yes :) , but using consulting is an >option too, and eventually learning ourselves (?). It depends on performance. Hiring an expert (like Ray Andraka) tends to get about a 4x improvement in area/delay product, which probably has about a 10x improvement in cost. However, that costs money, so factor that in as NRE vs part cost. >Is mixing C code (on DSP) and hardware optimized functions (on FPGA) a >good choice for speed ? (versus C only on DSP) You might want to think of the split differently, as the communication costs between the two will be high. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 50694
On Tue, 17 Dec 2002 17:51:18 +0100, Rene Tschaggelar <tschaggelar@dplanet.ch> wrote: >Khim Bittle wrote: >> Configuration time for the Altera ACEX 1K parts according to the data >> sheet is "less than 40ms" ... perhaps there is additional information >> but I can't seem to find it. I figure that the configuration time >> varies considerably between the EP1K10 and the EP1K100 but I would >> like to know how much time I should expect for the different size >> parts , does anyone have any real experience here and can give me some >> better numbers ? Thanks , Khim Bittle >> >> ( These parts are being designed into a video processor which needs to >> reload the array once or twice with a selected algorithm during a >> processing cycle ) >> > >I'm currentl investigating the embedded programmability >of these devices. > >There are various influences to consider : >The programming clock, JTAG can go up to 10MHz. >The programming mode, parallel is probably faster than serial. >Assuming that only the ones(or zeroes) have to be >written, how full is your device ? > Since fast loading is vital for my application I am only considering parallel mode with external memory or processor selected to configure the Altera part as fast as it can handle it. Khim Bittle (remove NOSPAM in email )Article: 50695
Steve, > The bottom line is _nobody_ pays out a license just because. I don't know what you mean by that, but I know it's not true. I have dealt with many patent issues where they simply paid the license rather than fight it in court. > From what I have seen is a company would rather spend a million dollars not > to pay _any_ kind of license fee. Some, certainly, but not EVERY company. > From what I've seen big companies will > stomp on your head and put you out of business before they license anything > from a small company. That may be true, but the case that was being discussed in this thread were two small companies. > It's seen as a weakness if somebody else has done > something in your space before you do. If you license it then your > competitor can license it and _nobody_ wants that. That depends on the value of it to your "product". There are many products that use patented/licensed stuff, such as using an embedded OS. If your product IS an embedded OS, it's a bad idea to license someone else's OS, but if your product is a vehicle navagation system, licensing an OS isn't a big deal. Regards, AustinArticle: 50696
I wouldn't read too much into what appears in the back-annotated VHDL. If you look at the top of that file, you'll see the following lines: -- [snip] This netlist uses simulation -- primitives which may not represent the true implementation of the device, however -- the netlist is functionally correct. Do not modify this file. If you want to know the true implementation, then use fpga_editor. If you are running into timing issues in post-route simulation, then take a look at your constraints and the timing analysis results - make sure you've correctly applied the clock period and that the routed design meets timing. more details about the timing failures would help get a better answer... HTH, MikeArticle: 50697
You should try to make the FPGA proto as similar to the ASIC as possible, this means restricting your ASIC design to constructs that can be successfully emulated in your FPGA technology. You knew you'd be emulating your ASIC, and the fact that one or more of the designers doesn't know what good synchronous design is doesn't mean you have to fudge your emulation strategy, it just means that guy(s) get to recode his block the right way. A design coded to the restrictions of an FPGA implimentation will be a breeze to make as an ASIC. disclaimer: Yes I know that there are times that you cannot do this like when your ASIC design is explicilty doing something tricky to save power or whatever, but this case didn't sound like it was one of those cases but more of a "do I really have to go back and make it right or can I just go round and round with hold violations". Best Regards President, Quadrature Peripherals Altera, Xilinx and Digital Design Consulting email: kayrock66@yahoo.com http://fpga.tripod.com ----------------------------------------------------------------------------- strut911@hotmail.com (strut911) wrote in message news:<4379d3e0.0212170354.745abafd@posting.google.com>... > Hello All. > I have a clock that is distributed largely throughout the design and > in some places it gets gated in order latch incoming data on a data > bus. Although I could design around it, the purpose is for > verification of an ASIC. I would prefer to try and keep the design as > intact as possible. So the question is: If I have a clock going to a > non-clock resource, does the whole clock routing use non-clock nets? > Or is it just that particular instance? This is very important to my > design, and will dictate how much re-design effort will be required to > port the ASIC to the FPGA. Thanks for any help. > strut911Article: 50698
I'll take a SWAG at this one: You ran your synthesis tool and neglected to tell it to instantiate I/O cells (IOBs). The P&R tool sees this, gives you a warning, then automatically puts them in for you knowing the port directions from your netlist. Am I close? Best Regards, President, Quadrature Peripherals Altera, Xilinx and Digital Design Consulting email: kayrock66@yahoo.com http://fpga.tripod.com ----------------------------------------------------------------------------- dirk.doerr@delsy.de (Dirk_Doerr) wrote in message news:<5740bed4.0212170651.40f7ce21@posting.google.com>... > Hi! > > In a design for a Xilinx XC5204 the place and route tool displays the > following warning: > > Warning:Place:128 - IOPLACETASK: No I/O comps to place > > But no errors. What does this mean? The IOBs are connected. > Thanks > > Dirk DörrArticle: 50699
Thanks, Alan. But I already checked that record and those solutions don't apply to my case. After some analysis, I think it's probably a bug of ISE 5.1i for solaris. My design is something like this. I have a synthesizable function block which integrated block memory cores and some MAC cores. I simply need to integrate multiple such function blocks together in a higher level. Those memory cores will have to be organized into a bigger memory block therefore I need a decoder to decode some address lines to drive those memory enables. Here is the problem: if I don't use the decoder at all (i.e. all the enable ports are drived by one signal), then the design could be synthesized by ISE 5.1i for solaris. In this case, all my function blocks are synthesized without problem. But if I add a decoder written by concurrent statements (with ... select ..., or when ... else) or by case statement, the error will occur when xst is doing low level synthesis and it reports the internal message: ========== Library "/CAD/tools/xilinx/data/librtl.xst" Consulted INTERNAL_ERROR:Xst:cmain.c:3195:1.89.2.1 - To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.com --> ========== Of course, the decoder itself could be synthesized nicely if it is put into a single file. And the whole design could be synthesized in ISE 5.1i for windows with no complaints. I would appreciate if anyone could give a shot to this problem. It would be even greater if someone in xilinx have interests to further analyze this with me, after all, I probably still have to switch my work to solaris. Thanks a trillion! :) Regards, Hua Alan Fitch wrote: > Yes - look up the error in the Xilinx Answers database at > http://support.xilinx.com > > See answer record #15476 > > regards > > Alan
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Compare FPGA features and resources
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