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I've done that on many designs. The weak pullups are enough as long as the
memory is located close to the FPGA. Where I have an influence, I recommend
pullups on the control signals so that reconfiguration won't upset the
contents of the RAM. It is very useful to have the capability to reconfigure
without corrupting RAM contents (see my paper on the radar environment
simulator for examples of this, available at no charge on my website).
Falk Brunner wrote:
> "Prashant" <prashantj@usa.net> schrieb im Newsbeitrag
> news:ea62e09.0212201207.82e34a7@posting.google.com...
>
> > Step 1 : Program FPGA to read data from serial port and write to the
> > external RAM. I described this in details in my previous post. My
> > feeling is that this part is getting done correctly. I do keep the
> > write signal asserted all the time, but the chip select signal
> > deasserts itself when no writing is being done. 64,000 words are
> > written to the external RAM.
> >
> > Step 2: In a similar process as above, I reprogram the FPGA to read
> > data from the external RAM and write to the serial port of the PC.
> > This data is then checked on the PC and found to be exactly the same
> > as what was written to the RAM in step 1.
>
> ??? Do you really RECONFIGURE the FPGA?? You mean, you pull PROGRAM low to
> reset the configuration, download a new configuration via serial/JTAG mode
> and run the second configuration to read the data from the SRAM?
> Sound dangerous. The IOS go tristate when PROGRAM is pulled low, so who is
> driving CS, RD, WR to the SRAM? There are at least EXTERNAL pull-ups
> required.
>
> --
> MfG
> Falk
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 50851In article <3E0387F7.CB8D5E6B@andraka.com>, Ray Andraka <ray@andraka.com> wrote: >I am aware of some of those customers that purposely turn off the inference of >the SRL16's because of a misguided (IMHO) attempt of having 'generic RTL >code'. Many of the others don't get SRL16's because they put resets on all of >the flip-flops, which keeps synplify from inferring the SRL16, whether it is >intentional or not. I do know that I use the SRL16's much more extensively >than most users (I've got designs where 70% of the LUTs used are SRL16's). Also, although I don't use SRL16s in my retiming code, I'd probably see a nontrivial benefit if I did. My hand-benchmarks used a fair number (I think my AES core uses a good 10% as SRL-16s). -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 50852
Hello,
I have an EMI noise problem with a cooling fan on an FPGA based system.
As a result, I am considering using a thermostat to control my cooling fans
in my system. I would like to attach the thermostat directly to the worst
case element on the board. To do so I need to decide what the likely
maximum allowable case temperature is. I am using a Spartan2E
XC2S50E-7TQ144C. I believe that the part is dissipating about a watt
although I haven't measured this yet. When I look at XAPP415 I see that
they list a maximum Theta J-A of 57.6 C/W with a typical value of 33.5C/W.
They also list Theta J-C of 5.5 W/C (typical). The first question is, "What
are the assumtions about heatsinking through the ground plane in the PCB for
theta J/C ?" The second question is can I use the 5.5 number to calculate
the temperature setting for my thermostat? Thus the maximum junction
temperature is 85C and the part dissapates 1 watt for a J/C temperature rise
of 5.5C. Thus the temperature of the thermostat could be set at say 79.5C.
For safety, I could use a 65C thermostat. The intent of all this is to
allow the customer to run the part in a low noise condition if the
environment is cool enough, but yet protect the system from overheating.
As I think about it turning the fan on will generate a nasty EMI glitch
that would corrupt the user's measurements. Perhaps, I should provide any
idiot light/beeper that would tell the user to turn on the fan. Still, how
do I make the determination as to what the allowable case temperature should
be.
By the way, the system is a low noise pulse width modulated anemometer
which is intended to be used in the field (i.e. in the sun on the salt flats
in Utah.)
Thanks,
Theron Hicks
Article: 50853Ray Andraka wrote: > Seems somewhat limiting, but then it is an employer's market more or > less. It would rule me out too, as well as the few people I know to be > very strong in both FPGAs and computer arithmetic/DSP. > > John Jakson wrote: > >> I have been seeing an interesting group of job posts for an FPGA >> supercompuer startup for the Bioinformatics industry. The positions >> apparently requires a Phd from only the best 5 US schools so that >> rules me out. Seems to be a new team, location in NY city, maybe SJ >> or SD. >> >> goto \/ and enter FPGA and look at Cybercoders, 2 pages, 8 positions. >> >> http://seeker.dice.com/seeker.epl?rel_code=1102&op=2 >> <http://seeker.dice.com/seeker.epl?rel_code=1102&op=2> >> >> Also a google on schrodinger (sitemap, careers..) looks remarkably >> similar as do posts on a no of other job sites! >> >> Good luck hunting! >> > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > > \ Hi Ray I kind of posted it to illustrate the nonsense that goes on when two cultures that normally do not work together are forced to rub shoulders. In this particular case the company involved is 50 people with 30+ Phd Bioinformatics types who do not understand that you can be a brilliant and employed engineer and not even degreed (I know a few) let alone have a Phd let alone selected to 5 schools. Now we all expect medical Dr's to be Phd'ed otherwise they wouldn't be a Dr for the obvious legal reasons, but I haven't ever worked with Phd EEs as a matter of legal necessity. A few have, but most don't. Anyway I hope that all the good available EEs in this group who do know what they are doing do apply for these positions. Eventually they will get the message that there probably aren't too many ivory tower virgins for them to recruit. Once they realize the cultural difference, 8 lucky guys might get busy. Irony is that even most of Xilinx or Altera EEs are also unqualified to work on this FPGA project, hee hee.Article: 50854
Hi, One way of doing floating point computation is to first shift the binary inputs to the left and then shift it back on the outputs.I am not sure whether Virtex II pro has an easy way to do that or not. sincerely ------------- Kuan Zhou ECSE department On Mon, 16 Dec 2002, Terrence Mak wrote: > Hi, > > Does Xilinx Virtex2Pro support the floating point computation? In fact what > is the advantages of embedded the PowerPC in the FPGA. What's software > design environment support the system design of Virtex2Pro with the PowerPC? > > Besides, would you mind suggest any FPGA prototyping board available in the > market is embedding the Virtex2Pro and with PCI interface? Thanks. > > Terrence Mak > > > >Article: 50855
Exactly. I'm probably about as experienced an FPGA designer you will find
anywhere....I've done nothing but FPGAs since 1994, and have completed well
over 100 FPGA designs in that time. Frankly, many of the PhD types I've run
across wouldn't know where to start when presented with a real design with
time to market, device size/cost/power and real performance constraints.
There are of course exceptions, but they are relatively rare. If the issue
is for legal reasons, a P.E. would be more appropriate than a PhD. I'm not
aware that a PhD in engineering carries any more legal status than a B.S.
John Jakson wrote:
>
> Hi Ray
>
> I kind of posted it to illustrate the nonsense that goes on when two
> cultures that normally do not work together are forced to rub shoulders.
> In this particular case the company involved is 50 people with 30+ Phd
> Bioinformatics types who do not understand that you can be a brilliant
> and employed engineer and not even degreed (I know a few) let alone have
> a Phd let alone selected to 5 schools. Now we all expect medical Dr's to
> be Phd'ed otherwise they wouldn't be a Dr for the obvious legal reasons,
> but I haven't ever worked with Phd EEs as a matter of legal necessity. A
> few have, but most don't.
>
> Anyway I hope that all the good available EEs in this group who do know
> what they are doing do apply for these positions. Eventually they will
> get the message that there probably aren't too many ivory tower virgins
> for them to recruit.
>
> Once they realize the cultural difference, 8 lucky guys might get busy.
>
> Irony is that even most of Xilinx or Altera EEs are also unqualified to
> work on this FPGA project, hee hee.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 50856Theron Hicks wrote: > When I look at XAPP415 I see that > they list a maximum Theta J-A of 57.6 C/W with a typical value of 33.5C/W. > They also list Theta J-C of 5.5 W/C (typical). The first question is, "What > are the assumtions about heatsinking through the ground plane in the PCB for > theta J/C ?" I think the extra heat conduction through the pins to the pc-board is more relevant in the junction-to-ambient case, and does very little for the already low junction-to-case situation. I would glue or clamp a generous piece of aluminum onto the FPGA, and then measure its temperature. I am sure there are soft-start ways for the fan, and when you have a big piece of Al, you can mount the fan really far away, and still be effective. You can also use Cu and even Ag, they are even better. :-) Peter Alfke, Xilinx ApplicationsArticle: 50857
The 18 x 18 multipliers are ideally suited to shift data ( multiplication by a power of 2 = shift) There as many multipliers as there are BlockRAMs, so you might never run out of them... Peter Alfke, Xilinx Applications ==================== Kuan Zhou wrote: > Hi, > One way of doing floating point computation is to first shift the binary > inputs to the left and then shift it back on the outputs.I am not sure > whether Virtex II pro has an easy way to do that or not. > > sincerely > ------------- > Kuan Zhou > ECSE department > > On Mon, 16 Dec 2002, Terrence Mak wrote: > > > Hi, > > > > Does Xilinx Virtex2Pro support the floating point computation? In fact what > > is the advantages of embedded the PowerPC in the FPGA. What's software > > design environment support the system design of Virtex2Pro with the PowerPC? > > > > Besides, would you mind suggest any FPGA prototyping board available in the > > market is embedding the Virtex2Pro and with PCI interface? Thanks. > > > > Terrence Mak > > > > > > > >Article: 50858
I have seen some of these things constructed in such a way that only one person can meet the job requirements. Hate to be a cynic but isn't this person usually a newly graduated PHD from a foreign country that they can get to work for them at a nice price? Sometimes reality bites. Hopefully for all the reasons you mentioned that a non-PHd is well suited for the job, it will also bite them back. Cheers, Jim Ray Andraka wrote: > Exactly. I'm probably about as experienced an FPGA designer you will find > anywhere....I've done nothing but FPGAs since 1994, and have completed well > over 100 FPGA designs in that time. Frankly, many of the PhD types I've run > across wouldn't know where to start when presented with a real design with > time to market, device size/cost/power and real performance constraints. > There are of course exceptions, but they are relatively rare. If the issue > is for legal reasons, a P.E. would be more appropriate than a PhD. I'm not > aware that a PhD in engineering carries any more legal status than a B.S. > > John Jakson wrote: > > >>Hi Ray >> >>I kind of posted it to illustrate the nonsense that goes on when two >>cultures that normally do not work together are forced to rub shoulders. >>In this particular case the company involved is 50 people with 30+ Phd >>Bioinformatics types who do not understand that you can be a brilliant >>and employed engineer and not even degreed (I know a few) let alone have >>a Phd let alone selected to 5 schools. Now we all expect medical Dr's to >>be Phd'ed otherwise they wouldn't be a Dr for the obvious legal reasons, >>but I haven't ever worked with Phd EEs as a matter of legal necessity. A >>few have, but most don't. >> >>Anyway I hope that all the good available EEs in this group who do know >>what they are doing do apply for these positions. Eventually they will >>get the message that there probably aren't too many ivory tower virgins >>for them to recruit. >> >>Once they realize the cultural difference, 8 lucky guys might get busy. >> >>Irony is that even most of Xilinx or Altera EEs are also unqualified to >>work on this FPGA project, hee hee. > > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > > -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Director of Training mailto:Jim@SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787 Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~Article: 50859
In article <3E039579.C7F02062@xilinx.com>, Peter Alfke <peter@xilinx.com> wrote: >You can also use Cu and even Ag, they are even better. :-) I'm just waiting for polycrystaline diamond coatings. :) -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 50860
Mr. Giaccaglini, The Altera web site has some information for what you want to do. The page http://www.altera.com/literature/lit-acx.html contains the following: - AN 116: Configuring SRAM-Based LUT Devices. This documents the configuration process and how to set up the board. It also has an example design for a MAX device which reads from a Flash eprom and sends the configuration data to the FPGA. - "Design File for Configuring FLEX 10K & FLEX 6000". This is VHDL code for a MAX device to implement the design. The configuration process is identical for ACEX 1K, so you can use this file. Sincerely, Greg Steinke gregs@altera.com "Giaccaglini Giorgio" <g.giaccaglini@libero.it> wrote in message news:<QerM9.32988$TC5.1006092@twister1.libero.it>... > I want to programme an ACEX1K (where I put a NIOS CPU) using a simple CPLD > (as controller) and a Flash Eprom in which I have the FPGA configuration and > the application. > > Do you have a VHDL source for the controller that download the FPGA? > > Thank you very much for your help. > > Giorgio Giaccaglini > Aethra Telecommunication > Italy > +39 02 2189877 > g.giaccaglini@aethra.it > www.aethra.itArticle: 50861
In article <3E03A7BA.90605@SynthWorks.com>, Jim Lewis <jim@SynthWorks.com> wrote: >I have seen some of these things constructed in such a way >that only one person can meet the job requirements. >Hate to be a cynic but isn't this person usually a newly >graduated PHD from a foreign country that they can get to >work for them at a nice price? Sometimes reality bites. >Hopefully for all the reasons you mentioned that a non-PHd >is well suited for the job, it will also bite them back. Also, far too many spin ASICs. These applications are either poster-children for FPGA cluster-boxes (Quickturnish boxen, or boxen of cheap FPGAs ($.01 or less/CLB)) or clusters-of-PCs, perhaps clusters-of-PCs with Nvidia graphics cards (there is a LOT of FP in those GPUs). Yet you still here of new companies going with an ASIC approach. As someone who is really close to meeting the listed requirements (once I write the F@#)$* dissertation), I would NOT hire me to actually implement such a thing, as it really is detailed implemnetation and programming, and a fair mix of algorithm understanding. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 50862
Jim Lewis wrote: > I have seen some of these things constructed in such a way > that only one person can meet the job requirements. > Hate to be a cynic but isn't this person usually a newly > graduated PHD from a foreign country that they can get to > work for them at a nice price? Sometimes reality bites. > Hopefully for all the reasons you mentioned that a non-PHd > is well suited for the job, it will also bite them back. > > Cheers, > Jim > > Usually those types of adverts are posted in specific places where US citizens won't find them, ie very local newspapers, & in IEEE Spectrum back pages where you write back to an obvious US gov labor office where it's obvious that the job is already held by a H1 holder hoping for a Green Card. This ploy works atleast 95% of the time and the US gov knows the game in hand. How would I know that, nudge nudge wink wink! In this case I am 100% sure it is a cultural wall between scientists & engineers. The scientists aren't used to dealing with a horde of relatively uneducated co workers, I know this from other EE insiders working in the Bio FPGA field. I would venture that Phd's do have one huge advantage over EEs, they seem to be much better connected to the startup $ from investors & esp DOD even if they don't know how to hire the teams. I'd would ignore the silly limits & apply if you are interested, nothing to lose.Article: 50863
In article <b2PM9.243699$pN3.19940@sccrnsc03>, John Jakson <johnjakson@yahoo.com> wrote: >One ASIC company Paracel supposedly gave up after realising that ASICs >take a long time to develop, aren't reprogrammable, and are useless if >you didn't think of every possible app before you taped out. They are a >division of Celera, the company that co won with the gov the Human >Genome mapping project. The actual Genome mapping was done with mega >clusters of Alpha racks hosted by Compaq. Good for Alpha PR since it >wasn't going anywhere anyway. IIRC, their ASIC ended up being a SIMD array anyway. If you are going to go that route, you would do better making an SMP of vectors. Vectors may be out-of-vogue, but they really are powerful. There is a reason why the Earth Simulator is the #1 supercomputer, with "only" 5000 CPUs. ASCI Q (#2) is less than 1/4 the teraflops, with 2x the CPUs. Similarly, the video cards have portions that look like vector machines without some of the nicer control mechanisms. >Any sane EE would likely just buy off the shelf DINI boards and start >from there, well I would. I'd split it in half: The integer/fixed-point half would be all FPGA or perhaps Chamelion parts/similar ALU array if any useful one ships. Without that, Xilinx parts, as you really want SRL16s for various delay chains. FP applications, I'd still vote cluter-of-PCs. <$500,000 buys 660 GFlops worth of cluter-based supercomputer (http://space-simulator.lanl.gov/). If they were willing to spend a wee bit more, they could have gotten a $<1M teraflop. > > As someone who is really close to meeting the listed requirements > > (once I write the F@#)$* dissertation), I would NOT hire me to > > actually implement such a thing, as it really is detailed > > implemnetation and programming, and a fair mix of algorithm > > understanding. > >Well thats honest! But is Berkeley in the list of top 5? We like to say #1.... But that's omitting that it is generally considered a 4-way tie (Berkeley, Stanford, MIT, CMU) in CS. :) >Actually Nick, just for saying that, I would give you the job, not >detail FPGA work but consulting on the C codes operational intent, >assuming you know all about Blasting. I remember looking at Blast a while ago. Pretty hash, nice hash... But I ended up using Smith/Waterman as my benchmarks, as it makes a good, simple benchmark for FPGAs: it specializes well (saves a good amount of real-estate), works well with 16 bit precision, etc etc etc. >I am real curious if anyone knows, is there any scoop on Hal, are they >for real? Star Bridge Systems has been around for a bit, is that who you mean? Their website has generally ditched the "hal" term, probably got a bit of smackdown from Arthur C Clark's lawyers, but they are still around. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 50864
Peter Alfke wrote: > Russell wrote: > >>I need a linux version of webpack with a gui >>that works. If it wasn't for spartan-II devices >>with distributed ram (SRL16) and some floorplanning >>ability, i'd be using altera now. > I'll forward this to our software tools management. > It is nice to hear that superior hardware feature still mean a little > something... > > Peter Alfke > ============================ Thanks. FPGA tools are the only reason i'm still stuck on windows. Only after getting use to linux after a few months or maybe after more than one attempt at finding the right distro, do you realize how much windows turns your pc into a stupid consumer appliance. I found the 'right' distro for me is debian, because it has a really good way of installing and uninstalling programs and resolving library dependencies when installing new programs.Article: 50865
Uwe Bonnes wrote: > Russell <rjshaw@iprimus.com.au> wrote: > : I need a linux version of webpack with a gui > : that works. If it wasn't for spartan-II devices > : with distributed ram (SRL16) and some floorplanning > : ability, i'd be using altera now. > > I installed a normal windows version of webpack/ise with a recent version of > wine on linux. With some patches already included in newer version of wine, > webpack works quite well. No chance for running impact, and no interest from > xilinx to get help to get impact running however... > > For webpack installation in wine, unzip the exe file in a directory. Read > the wine docs about Installshield 6 (in short builtin ole32/oleaut32/rpcrt4 > and native std*.tlb). For running, native msvcrt helps in some > cases. Sometimes startup hangs, but restarting normally works then. I've tried installing other cad packages in wine, but the installer kind of hangs even tho there is HDD accesses every few seconds. Is 64MB ram enough? Does the webpack gui work in your setup?Article: 50866
Tom,
I do assemble surface mount parts in what is only just above a hobbiest level
shop. The trick is to use a very small iron. A magnifier to help with the vision
may be useful but not absolutely necessary. A cheap jeweler's loupe will save
many headaches in troubleshooting your assembly. Hand soldering resistors and
capacitors down to 0603 size is not to bad. 0805 size parts are easy even for a
47 year old man who feels half blind. Surface mount semiconductors are much
simpler to mount than you would ever believe. Even the fine pitch parts (0.5 mm
pin pitch) are remarkably easy to solder. If you are dealing with standard SOIC
parts (0.05" pitch) then they are really easy to do. The trick is to tie down one
corner with a small amount of solder and then tie down the opposite corner at
exactly the right spot. The other pins automatically line up. The only thing
that I would say is that if you are paying for boards to be made, pay the extra
for solder mask. It is worth 10 times what they charge in terms of less
headaches. ( I wouldn't even try a 0.5 mm pitch part without solder mask.) The
gull wing IC leads are much easier to deal with than the J-lead style. (Xilinx
TQ144 is a gull wing, their PC84 package is J-lead). I personally would not
even consider a Ball Grid Array type package although some say they are easy. One
more comment... surface mount ICs are easy to install. They can be really
difficult to remove without damaging the board beyond repair. Take your time if
you need to remove a part.
By the way, do you folks over there have Digikey available. While they are
sometimes a little more expensive than some of the competition they do sell small
quantities of surface mount parts. I suspect that Farnell will do so as well.
Here in the USA, they are Newark and I know that Newark does so. In fact, Newark
sometimes gets small quantities of Farnell parts for me when Newark's US warehouse
is out of stock.
Theron Hicks
Theo Markettos wrote:
> Hi Tom,
>
> Thomas Womack <pmxtow@merlot.uucp> wrote:
> > This may be an incoherent request, but I'll go ahead.
> >
> > When I last played with electronics, resistors were little cylindrical
> > things with long wire legs, and ICs had at most forty pins, which came
> > out of the side at convenient 2.54mm spacing; you could design on
> > bread-board. If you wanted to connect to a computer, you used the
> > parallel port, or the four-channel analogue-digital converter on the
> > BBC Micro joystick port. If you were really advanced, you might try to
> > build a two-layer PCB with little metal fingers at the bottom to plug
> > into an ISA slot on a PC.
>
> Sounds like what I do at work :-) Seriously, just because everything has
> gone surface mount isn't necessarily a good reason for you to do the same.
> We deal almost exclusively with through-hole components because the boards
> are easy to repair in the field (20000ukp machines in hospitals). Often you
> can get away with using through-hole if you want, with perhaps daughter
> boards with surface mount chips on them. The speed won't be wonderful, but
> if you're hacking sometimes you don't really care about speed.
>
> > So, what do people do to prototype now? As I read it, you do a lot in
> > simulation and then, once you're happy with a design, you send a file
> > to a boutiquie to get a PCB made and the components fitted to it. How
> > much does it cost to get one two- or four-layer PCB made, how long
> > does it take, and do you have to provide the company with all the
> > components you want fitted, or will they have 1kohm surface-mount
> > resistors and 555 oscillators in stock?
>
> It depends. I'm just getting my first board built at home - through a
> contact, so it isn't costing me anything - but I've heard
> http://www.olimex.com/pcb recommended. They're in Bulgaria, but a double
> sided 160x100mm board is $26 plus postage, which is very good (and $5
> postage is probably cheaper for UK people than fabbing in the US).
>
> You _can_ get people to build boards for you, but you'll be stung by the
> tooling charge for small quantities. Also getting obscure components in small
> quantities is difficult - you have to pretend[1] to be a company before
> distributors will talk to you, but you can sometimes get samples (eg Maxim
> give them free from their website).
>
> [1] AFAIK completely legally. IANAL, but anyone can be a sole trader
> without any paperwork if you don't make a profit - this is what I do to stop
> silly web forms from telling me to go back and fill in the company field.
>
> Surface mount soldering is possible by hand. I've done it with a piece of
> wire wrapped around a free-with-cornflake-packet iron - not the best tools
> for the job, but possible. If you don't go down the PCB route, another
> method is to solder wires to each pad to convert the SMD to a through-hole
> layout - tedious but possible. For an example, see a board I built:
> http://www.chiark.greenend.org.uk/~theom/riscos/superio/
>
> If you're into getting components (since I know you're in the UK), Maplin
> are fairly useless these days unless you're near a shop, but it's often
> still easier to mail order. Rapid http://www.rapidelec.co.uk/ are very good
> and cheap (definitely worth getting a catalogue), whilst RS
> http://rswww.com/ and Farnell http://www.farnell.com/ are more expensive but
> have wider ranges. For credit cards, Farnell have a minimum order of 10ukp
> whilst Rapid charge 3ukp postage below 30ukp of order (haven't used RS
> recently from home, so can't comment). Rapid are better at selling things
> in small quantities (sometimes Farnell/RS only sell things in packs of 5 or
> 10).
>
> > How do you interface widgets to a computer nowadays? Are there chips
> > which can convert USB or PCI to something easier to contemplate; is it
> > practical for a hobbyist to connect things to the PCI bus?
>
> There are USB microcontrollers out there; Cypress make some. There are also
> USB to serial chips - there's a thread on comp.arch.embedded on this very
> subject at the moment.
>
> > Which is the right group for me to be asking these questions in?
>
> comp.arch.hobbyist is another group to look at. It's fairly low traffic,
> but mostly consists of people doing this sort of thing at home, as opposed
> to full time (so can't afford $$$ for tools etc - but there are tricks to
> get around this). It's bot-moderated (to stop floods of OT noise it was
> receiving), but if you post you'll get an email explaining it all.
>
> Hope this helps,
> Theo
>
> PS Tom, grab me (caliston) on #chiark if there's anything you want to
> ask with a slightly lower latency :-)
>
> --
> Theo Markettos theo@markettos.org.uk
> Liphook, Hampshire, UK theom@chiark.greenend.org.uk
> http://www.markettos.org.uk/
Article: 50867
Tom,
I do assemble surface mount parts in what is only just above a hobbiest level
shop. The trick is to use a very small iron. A magnifier to help with the vision
may be useful but not absolutely necessary. A cheap jeweler's loupe will save
many headaches in troubleshooting your assembly. Hand soldering resistors and
capacitors down to 0603 size is not to bad. 0805 size parts are easy even for a
47 year old man who feels half blind. Surface mount semiconductors are much
simpler to mount than you would ever believe. Even the fine pitch parts (0.5 mm
pin pitch) are remarkably easy to solder. If you are dealing with standard SOIC
parts (0.05" pitch) then they are really easy to do. The trick is to tie down one
corner with a small amount of solder and then tie down the opposite corner at
exactly the right spot. The other pins automatically line up. The only thing
that I would say is that if you are paying for boards to be made, pay the extra
for solder mask. It is worth 10 times what they charge in terms of less
headaches. ( I wouldn't even try a 0.5 mm pitch part without solder mask.) The
gull wing IC leads are much easier to deal with than the J-lead style. (Xilinx
TQ144 is a gull wing, their PC84 package is J-lead). I personally would not
even consider a Ball Grid Array type package although some say they are easy. One
more comment... surface mount ICs are easy to install. They can be really
difficult to remove without damaging the board beyond repair. Take your time if
you need to remove a part.
By the way, do you folks over there have Digikey available. While they are
sometimes a little more expensive than some of the competition they do sell small
quantities of surface mount parts. I suspect that Farnell will do so as well.
Here in the USA, they are Newark and I know that Newark does so. In fact, Newark
sometimes gets small quantities of Farnell parts for me when Newark's US warehouse
is out of stock.
Theron Hicks
Theo Markettos wrote:
> Hi Tom,
>
> Thomas Womack <pmxtow@merlot.uucp> wrote:
> > This may be an incoherent request, but I'll go ahead.
> >
> > When I last played with electronics, resistors were little cylindrical
> > things with long wire legs, and ICs had at most forty pins, which came
> > out of the side at convenient 2.54mm spacing; you could design on
> > bread-board. If you wanted to connect to a computer, you used the
> > parallel port, or the four-channel analogue-digital converter on the
> > BBC Micro joystick port. If you were really advanced, you might try to
> > build a two-layer PCB with little metal fingers at the bottom to plug
> > into an ISA slot on a PC.
>
> Sounds like what I do at work :-) Seriously, just because everything has
> gone surface mount isn't necessarily a good reason for you to do the same.
> We deal almost exclusively with through-hole components because the boards
> are easy to repair in the field (20000ukp machines in hospitals). Often you
> can get away with using through-hole if you want, with perhaps daughter
> boards with surface mount chips on them. The speed won't be wonderful, but
> if you're hacking sometimes you don't really care about speed.
>
> > So, what do people do to prototype now? As I read it, you do a lot in
> > simulation and then, once you're happy with a design, you send a file
> > to a boutiquie to get a PCB made and the components fitted to it. How
> > much does it cost to get one two- or four-layer PCB made, how long
> > does it take, and do you have to provide the company with all the
> > components you want fitted, or will they have 1kohm surface-mount
> > resistors and 555 oscillators in stock?
>
> It depends. I'm just getting my first board built at home - through a
> contact, so it isn't costing me anything - but I've heard
> http://www.olimex.com/pcb recommended. They're in Bulgaria, but a double
> sided 160x100mm board is $26 plus postage, which is very good (and $5
> postage is probably cheaper for UK people than fabbing in the US).
>
> You _can_ get people to build boards for you, but you'll be stung by the
> tooling charge for small quantities. Also getting obscure components in small
> quantities is difficult - you have to pretend[1] to be a company before
> distributors will talk to you, but you can sometimes get samples (eg Maxim
> give them free from their website).
>
> [1] AFAIK completely legally. IANAL, but anyone can be a sole trader
> without any paperwork if you don't make a profit - this is what I do to stop
> silly web forms from telling me to go back and fill in the company field.
>
> Surface mount soldering is possible by hand. I've done it with a piece of
> wire wrapped around a free-with-cornflake-packet iron - not the best tools
> for the job, but possible. If you don't go down the PCB route, another
> method is to solder wires to each pad to convert the SMD to a through-hole
> layout - tedious but possible. For an example, see a board I built:
> http://www.chiark.greenend.org.uk/~theom/riscos/superio/
>
> If you're into getting components (since I know you're in the UK), Maplin
> are fairly useless these days unless you're near a shop, but it's often
> still easier to mail order. Rapid http://www.rapidelec.co.uk/ are very good
> and cheap (definitely worth getting a catalogue), whilst RS
> http://rswww.com/ and Farnell http://www.farnell.com/ are more expensive but
> have wider ranges. For credit cards, Farnell have a minimum order of 10ukp
> whilst Rapid charge 3ukp postage below 30ukp of order (haven't used RS
> recently from home, so can't comment). Rapid are better at selling things
> in small quantities (sometimes Farnell/RS only sell things in packs of 5 or
> 10).
>
> > How do you interface widgets to a computer nowadays? Are there chips
> > which can convert USB or PCI to something easier to contemplate; is it
> > practical for a hobbyist to connect things to the PCI bus?
>
> There are USB microcontrollers out there; Cypress make some. There are also
> USB to serial chips - there's a thread on comp.arch.embedded on this very
> subject at the moment.
>
> > Which is the right group for me to be asking these questions in?
>
> comp.arch.hobbyist is another group to look at. It's fairly low traffic,
> but mostly consists of people doing this sort of thing at home, as opposed
> to full time (so can't afford $$$ for tools etc - but there are tricks to
> get around this). It's bot-moderated (to stop floods of OT noise it was
> receiving), but if you post you'll get an email explaining it all.
>
> Hope this helps,
> Theo
>
> PS Tom, grab me (caliston) on #chiark if there's anything you want to
> ask with a slightly lower latency :-)
>
> --
> Theo Markettos theo@markettos.org.uk
> Liphook, Hampshire, UK theom@chiark.greenend.org.uk
> http://www.markettos.org.uk/
Article: 50868>Alternate Step 2 : I program the FPGA to run my 'design code' which >reads data from the external RAM and uses it to produce the required >outputs. This time 64 values are read in 64 cycles from the external >RAM for every run of my 'design code'. Thus the design code will run >for 1000 runs before all 64000 values are used from the external RAM. > It is during the alternate step 2, when I read 64 words in 64 cycles @ > 40MHz, that some of the data read is found to be erroneous. Is there a simple timing problem? If you are doing a read, what's the time from clock to address out of FPGA, address to data valid at RAM, setup time at FPGA. Correct for speed of light on traces, clock jitter, many outputs switching... How much do yo have to spare? Is there any pattern to which data bits are getting picked/dropped? Or which address lines are not working? If you run it again do you get the same errors? If you run it several times, do most of the errors happen at the same spot? If you reload your Step 2 code is the data still correct? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 50869
"Theron Hicks" <hicksthe@egr.msu.edu> wrote in message news:au01e8$17oj$1@msunews.cl.msu.edu... (snip) > As I think about it turning the fan on will generate a nasty EMI glitch > that would corrupt the user's measurements. Perhaps, I should provide any > idiot light/beeper that would tell the user to turn on the fan. Still, how > do I make the determination as to what the allowable case temperature should > be. > > By the way, the system is a low noise pulse width modulated anemometer > which is intended to be used in the field (i.e. in the sun on the salt flats > in Utah.) How about a hot-wire anemometer? Do you have to worry about the effect of the fan on the anemometer itself? -- glenArticle: 50870
> It is during the alternate step 2, when I read 64 words in 64 cycles @ > 40MHz, that some of the data read is found to be erroneous. > How do you know the data read in alternate step 2 is erroneous ? If you re-run step 2 again after running alternate step 2, are the data values corrupted ? Are the I/O constraints in the config file the same between the two configurations ? eg. same pin settings, same switching standards ? RobArticle: 50871
"Ray Andraka" <ray@andraka.com> wrote in message news:3E0393A3.C6F00486@andraka.com... > Exactly. I'm probably about as experienced an FPGA designer you will find > anywhere....I've done nothing but FPGAs since 1994, and have completed well > over 100 FPGA designs in that time. Frankly, many of the PhD types I've run > across wouldn't know where to start when presented with a real design with > time to market, device size/cost/power and real performance constraints. > There are of course exceptions, but they are relatively rare. If the issue > is for legal reasons, a P.E. would be more appropriate than a PhD. I'm not > aware that a PhD in engineering carries any more legal status than a B.S. Not to say that you wouldn't do a great job, but sometimes they want someone to understand FPGA design, algorithm design, and molecular biology. There are plenty of B.S. out there that understand two of the three, but finding all three is harder. -- glenArticle: 50872
Just thinking out loud... This is really a bit off topic (but somewhat similar) but, I've been thinking about trying to build a simple neural network accelerator (mostly as an academic exercise). Each neuron needs to take input from multiple sources and accumulate the results, ideally within a single clock cycle. The problem with using bram for this is that it doesn't allow enough simultaneous read ports. So much time would be spent reloading the bram or switching outputs for different neurons that it would mostly negate any advantage of building the thing in hardware. So, I've been thinking about using registers and distributed ram to build a serially loaded synaptic weights matrix(s). As long as the network can be built entirely within the FPGA and weights matrix doesn't need to be reloaded, I think the whole thing could be made to work very fast. Of course I'm thinking of trying something really simple to begin with like recognizing characters from an 8x8 pixel image input. I'd be relying on a pre-trained network. RobArticle: 50873
Russell <rjshaw@iprimus.com.au> wrote: : Uwe Bonnes wrote: :> Russell <rjshaw@iprimus.com.au> wrote: :> : I need a linux version of webpack with a gui :> : that works. If it wasn't for spartan-II devices :> : with distributed ram (SRL16) and some floorplanning :> : ability, i'd be using altera now. :> :> I installed a normal windows version of webpack/ise with a recent version of :> wine on linux. With some patches already included in newer version of wine, :> webpack works quite well. No chance for running impact, and no interest from :> xilinx to get help to get impact running however... :> :> For webpack installation in wine, unzip the exe file in a directory. Read :> the wine docs about Installshield 6 (in short builtin ole32/oleaut32/rpcrt4 :> and native std*.tlb). For running, native msvcrt helps in some :> cases. Sometimes startup hangs, but restarting normally works then. : I've tried installing other cad packages in wine, but the installer kind of : hangs even tho there is HDD accesses every few seconds. Is 64MB ram enough? : Does the webpack gui work in your setup? You can't run the full webpack installer directly. The exe need a lot for memory which collides with the wine memory layout. But you can use unzip on the exe. This will create a lot of files in the current directory. Run the setup.exe that was created there. Be sure to use a recent wine version, don't fiddle with windows dlls (no change in the ~/.wine/config [DllOverrides] section and don't give a --dll yyy=n option to wine on the command line), but have std*.tlb from windows available in the directory declared in the [wine] System directory. That should be enough to get the IS6 installer working. Beware! It's slow, even on windows. To run webpack v5, set the ~/.wine/config [Version] to nt40, or otherwise webpack will hang silently ( like it does on a real win95/98 machine). Hint to the xilinx developpers: Some check for the windows version and some message to the user would be helpfull. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 50874
pmxtow@merlot.uucp (Thomas Womack) wrote in message news:<at4pse$k8m$1@oyez.ccc.nottingham.ac.uk>... > This may be an incoherent request, but I'll go ahead. > > When I last played with electronics, resistors were little cylindrical > things with long wire legs, and ICs had at most forty pins, which came > out of the side at convenient 2.54mm spacing; you could design on > bread-board. If you wanted to connect to a computer, you used the > parallel port, or the four-channel analogue-digital converter on the > BBC Micro joystick port. If you were really advanced, you might try to > build a two-layer PCB with little metal fingers at the bottom to plug > into an ISA slot on a PC. > > Nowadays, passive components are little flecks of ceramic with solder > pads at each end, small ICs come in tiny flat-packs with centipede > fringes of legs around, and the interesting ones come either in large > flat-packs with centipede fringes, or in BGA form. And I presume the > signal-integrity requirements are such that bread-board, and even the > two-layer PCB, are Right Out. The BBC Micro and the ISA slot have > gone the way of the dinosaur; the parallel port is dying out. > > So, what do people do to prototype now? As I read it, you do a lot in > simulation and then, once you're happy with a design, you send a file > to a boutiquie to get a PCB made and the components fitted to it. How > much does it cost to get one two- or four-layer PCB made, how long > does it take, and do you have to provide the company with all the > components you want fitted, or will they have 1kohm surface-mount > resistors and 555 oscillators in stock? > > How do you interface widgets to a computer nowadays? Are there chips > which can convert USB or PCI to something easier to contemplate; is it > practical for a hobbyist to connect things to the PCI bus? > > Which is the right group for me to be asking these questions in? > > Tom Tom, you must be very old - probably about my age, to remember those big resistors ! ;*) Seriously, there are many ways to do prototypes or hobby projects. Believe it or not but those "big" resistors you are used to are still available. The biggest problem these days as you point out are the high pitch IC packages (commonly known as PQFP for Plastic Quad Flat Pack) and of course BGA and evern worth FPBA (Fine pitch Ball Grid Arrays) ! BGAs and FPGAs are virtually impossible to do in two or even 4 layer PCBs. Depending on the number of balls you are forced to use quite a few extra layers. Our company, like many others out there, specialize in all kinds of prototypes and all sizes of productions runs. For hobbyists FBGA "prototypes" are prohibitively expensive (unless you cashed in your stock option at the right time ;*). All of our low budges clients make sure they don't use any of the BGAs at all. It is sometimes hard but possible. Many chips do come in a variety of packages so you can chose the best solution for your needs. As others already have suggested, another popular solution is to use FPGAs and widely available prototyping boards. There you don't need to hire anybody, you can do it your self ! If you are still lost, please feel free to email me privately and I'd be happy to help. We do just as many low budget small projects, as we do full custom ASICs and 20 layer PCBs ! Best regards, rudi ------------------------------------------------ www.asics.ws - Solutions for your ASIC needs - NEW ! 3 New Free IP Cores this months (so far :*) FREE IP Cores --> http://www.asics.ws/ <--- ----- ALL SPAM forwarded to: UCE@FTC.GOV -----
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