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Frederic,
Try the following to remove the ambiguity:
(d7,d6,d5,d4,d3,d2,d1,d0) <= std_logic_vector'("ZZZZZZZZ");
Don't miss the single quote (') between the type and the literal.
This is not quite type casting. It is called a type qualifier.
Did you mean for this to be an inout port?
signal d0,d1,d2,d3,d4,d5,d6,d7 : inout std_logic;
You cannot drive an input port.
Cheers,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787
Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Frederic Bastenaire wrote:
> Hello,
>
> I have a newbie style question in VHDL:
>
> I declared 8 discrete signals, connected to IO pins of my FPGA:
>
> signal d0,d1,d2,d3,d4,d5,d6,d7 : in std_logic;
>
> Now I would like to manipulate them as an array, to assign them in a single
> statement for example.
> I thought aggregates were the right thing to use, but XST complains about
> type ambiguity when I write:
> (d7,d6,d5,d4,d3,d2,d1,d0) <= "ZZZZZZZZ";
>
> Using an alias does not seem to be the right solution either, one can not
> write
> alias data(0) : std_logic is d0;
>
> I also have to manipulate an 18 bit address define as 18 discrete signals
> connected to IO pins of my FPGA: having
> 18 assignments every time I have to update this address is not very
> elegant... I am sure there is a better solution do you have
> any suggestions?
>
> Thank you for your help,
>
> Frederic Bastenaire (fba@free.fr)
>
>
>
Article: 51451Andrew Rogers wrote: > Just took a look at the free WebPack ISE software for Windows and found > some documentation on XDL that seems to have Linux like commands. > > D:\Xilinx\help\data\xdl\xdl-ucs-ext.html > > Does this mean that the free WebPack ISE is also available for Linux or > Unix? If I can get free FPGA software for Linux then I can get by > without Open Source software tools. The webpack tools can, AFAIK, can be run in command line mode under Wine. I don't think you'll get the Project Navigator GUI going though. Regards, JohnArticle: 51452
John Williams wrote: > Andrew Rogers wrote: > >> Just took a look at the free WebPack ISE software for Windows and >> found some documentation on XDL that seems to have Linux like commands. >> >> D:\Xilinx\help\data\xdl\xdl-ucs-ext.html >> >> Does this mean that the free WebPack ISE is also available for Linux >> or Unix? If I can get free FPGA software for Linux then I can get by >> without Open Source software tools. > > > The webpack tools can, AFAIK, can be run in command line mode under > Wine. I don't think you'll get the Project Navigator GUI going though. > For those interested, I found some info on WINE and Xilinx at http://www.polybus.com/xilinx_on_linux.html Regards Andrew RogersArticle: 51453
The library should be in your Xilinx directory (it is installed during the
xilinx installation under xilinx/vhdl/src/unisims. You'll have to compile it
with your simulator before using it. I'm not sure where it is on the Xilinx
website. I know you can get them off the Aldec website, and I'm pretty sure you
can get them off the modelsim website.
Jim Raynor wrote:
> Ray,
> Thanks for the response. Could you tell me where to download the
> library?
>
> Thanks again
>
> Chris
>
> "Ray Andraka" <ray@andraka.com> wrote in message
> news:3E231694.F2763AE6@andraka.com...
> > you need to include the library and use clauses to invoke the unisim
> library.
> >
> > Jim Raynor wrote:
> >
> > > hi,
> > >
> > > I am having problem in simulating the Virtex's Primitive (e.g
> CLKDLL,
> > > BUFG...) using Modelsim. Could anyone tell me how to do it? I got
> errors
> > > in the Modelsim like
> > >
> > > # WARNING[1]: main.vhd(244): No default binding for component:
> "ibufg".
> > > (No entity named "ibufg" was found)
> > > # WARNING[1]: main.vhd(247): No default binding for component: "clkdll".
> (No
> > > entity named "clkdll" was found)
> > > # WARNING[1]: main.vhd(248): No default binding for component: "bufg".
> (No
> > > entity named "bufg" was found)
> > >
> > > Thanks.....
> > >
> > > Chris
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930 Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> > "They that give up essential liberty to obtain a little
> > temporary safety deserve neither liberty nor safety."
> > -Benjamin Franklin, 1759
> >
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 51454You might consider doing it the other way around... Define the pins as std_logic_vector (7 downto 0); and use an alias to let you access the individual bits and call them d0, d1 etc. I have used aliases with internal signals with no trouble, but possilbly there is a gotch-yah on a port. Try it and see. Clyde Frederic Bastenaire wrote: > Hello, > > I have a newbie style question in VHDL: > > I declared 8 discrete signals, connected to IO pins of my FPGA: > > signal d0,d1,d2,d3,d4,d5,d6,d7 : in std_logic; > > Now I would like to manipulate them as an array, to assign them in a single > statement for example. > I thought aggregates were the right thing to use, but XST complains about > type ambiguity when I write: > (d7,d6,d5,d4,d3,d2,d1,d0) <= "ZZZZZZZZ"; > > Using an alias does not seem to be the right solution either, one can not > write > alias data(0) : std_logic is d0; > > I also have to manipulate an 18 bit address define as 18 discrete signals > connected to IO pins of my FPGA: having > 18 assignments every time I have to update this address is not very > elegant... I am sure there is a better solution do you have > any suggestions? > > Thank you for your help, > > Frederic Bastenaire (fba@free.fr)Article: 51455
astonishs@yahoo.com (astonish) wrote in message news:<c27d8629.0301130133.6f37a396@posting.google.com>...
> Celoxica's White Paper on TripleDES describes
>
> typedef rom unsigned 4 SBox[64];
>
> static SBox SBoxes[8] =
> {
> SBox1, SBox2, SBox3, SBox4,
> SBox5, SBox6, SBox7, SBox8
> };
>
> How can I initialize the SBox array and what are
> SBox1, SBox2, .. ,SBox8?
>
> Any assitance appreciated.
>
> Astonish
You might also want to check out out web site, we provide
a Free Triple DES IP Soft Core. It works with FPGAs and full
custom ASIC implementations.
Please visit www.asics.ws for more information.
Best Regards,
rudi
------------------------------------------------
www.asics.ws - Solutions for your ASIC needs -
FREE IP Cores --> http://www.asics.ws/ <---
----- ALL SPAM forwarded to: UCE@FTC.GOV -----
Article: 51456Hi folks, > Yes, we already turn off the unused trees of the global clock network to save > power (two generations old now). Doesn't everyone? > > As for the clock tree's power consumption being a "large part" of the power, I > would encourage you to play with the on line power (excel) estimator > spreadsheets and see for yourself what power resources use, if you are so > inclined. > > http://www.xilinx.com/support/techsup/powerest/index.htm > > (For Virtex II Pro, reduce the predictions by 15 % for all core (1.5V > features), leave all IOs the same. Add the 6 mW/100 MHz per 405 PPC's, and the > mW's (I don't recall the budget) for the MGTs per their speed.) There is now a spreadsheet particular to Virtex II Pro. It is available (along with spreadsheets for other families) from here : http://www.xilinx.com/ise/power_tools/spreadsheet_pt.htm. Brendan > > > Austin > > Thomas Stanka wrote: > > > Kuan Zhou <zhouk@rpi.edu> wrote: > > > I am a newbie in FPGA field.I often heard people are talking about the > > > power consumption of the clock inside FPGA.What's the main issue of it? > > > Will the clock line consume lots of power? > > > > Yes. The problem in fpga is, that the clock is prerouted to every > > clockable element, where as in ASIC the clocktree will cover only used > > cells. > > So your clocktree will be allways be one of the the largest nets > > independend of your design even if your using only a hand full of FF. > > In newer fpgas there might be some technics to gate unused parts of > > the clocktree, to reduce power. > > Im not sure if Xilix allready gate unused parts of the clocktree, > > Actel do in its AX technology. > > > > bye ThomasArticle: 51457
Hello, Can anyone tell me the major differences between a CPLD and a FPGA and maybe also why an FPGA is better? thx very much! Tom, -- Install Debian now: http://debian.linux.beArticle: 51458
Tom Deblauwe <tomNOSPAM.deblauwe@pandora.be> wrote: : Hello, : Can anyone tell me the major differences between a CPLD and a FPGA and maybe : also why an FPGA is better? CPLD: A few blocks with a lot of inputs (26,54) inputs and some outputs (16) and mostly one big interconnection block FPGA: A lot (several hunderd to several thousand) blocks with some inputs and few outputs embeded in a fabric of interconnection CPLD: Mostly non-volatile programming FPGA: Mostly always volatile or one-time programming CPLD: Very predictable timing FPGA: Timing very dependant on actual placement of routing. Which one is better? The one that fits your needs best, you can afford and you can actually get. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 51459
--Actually, I understood that assigning a aggregate with aliased signals causes an internal error
-- in XST, here is an example:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity array_entity is
Port (
di0 : inout std_logic;
di1 : inout std_logic;
di2 : inout std_logic;
di3 : inout std_logic;
di4 : inout std_logic;
di5 : inout std_logic;
di6 : inout std_logic;
di7 : inout std_logic);
end array_entity;
architecture Behavioral of array_entity is
alias d0 : std_logic is di0;
alias d1 : std_logic is di1;
alias d2 : std_logic is di2;
alias d3 : std_logic is di3;
alias d4 : std_logic is di4;
alias d5 : std_logic is di5;
alias d6 : std_logic is di6;
alias d7 : std_logic is di7;
signal data_l : std_logic_vector(7 downto 0);
begin
(d7,d6,d5,d4,d3,d2,d1,d0)<=std_logic_vector'("10101010");
-- This causes the following error:
--FATAL_ERROR:HDLParsers:vhptype.c:172:$Id: vhptype.c,v 1.6 2001/10/12 21:32:28 weilin Exp $:200
-- - INTERNAL ERROR... while parsing C:/work/array/array.vhd line 36.
-- Contact your hot line. Process will terminate.
-- On the other hand, using non aliased signals like this:
-- (di7,di6,di5,di4,di3,di2,di1,di0)<=std_logic_vector'("10101010");
-- works fine...
end Behavioral;
Yours,
FB
Article: 51460Hi All; I am looking at the xc2s_eval as a pci card for a small project ( 10 or so cards). What are your opinions on the card? We need Linux support, 32 IO (min) and the ability to have multiple 200Mhz counters. The board mentioned has a 37 pin sub D connector that makes things even nicer. Thanks PatArticle: 51461
Well, first you need a sync stripper if video has sync on it. If video and H/V syncs are seperated then you don't need it. But a good PLL is essential. ICS, Analog Device and others have them, keep searching. Condiser the PLL interface familiar to you, since most of them are programmable. Also consider "broad band" design (your clock frequency will vary for different videos).Article: 51462
thx very much for ur detailed description ! the problem has been solved "Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:avv60g$jth6h$1@ID-84877.news.dfncis.de... > "tk" <tokwok@hotmail.com> schrieb im Newsbeitrag > news:avsfjl$5jb$1@www.csis.hku.hk... > > thx Falk > > > > the PC_INIT is a reset signal > > I don't quite understand problem 1, could you elaborate more ? > > The FPGA has its own clock source, the PC has its own clock source. SO there > are two systems with unrelated clocks talking to each other. So there is NO > guarantee when a signal from the PC will change in relation to your FPGA > clock. This can (no, WILL!!!!) mess up the state machine. If the FSM (finite > state machine) uses a one-hot encoding, you have a 100% chance to freeze it, > as you have noticed. So when you synchronize the signals comming from your > PC using two FlipFlops, it will be practically safe. I say practically, > because there is a pure mathematical chance that the bad asynchrounus signal > get through the synchronizer, but the probability is somewhere in 1 out of > milliards of years. Have a look on the xapps on the xilinx website, there > are some that discuss this problem (metastability). > The main problem is that, if one asynchronous signal from the PC goes to > more than one FlipFlop in FSM, tha ich can (WILL!!!) happen, that it changes > just a fraction of a ns before the FPGA clock arrives. And since the delay > from the IO cell to the two FlipFlops are never identical, one FlipFLop will > see a LOW, the other a HIGH. Depending on the state encoding, this will > cause a jump into a wrong state or total mess up (freezing). > > Regards > Falk > > > >Article: 51463
1. You have to compile the xilinx unisim library in Modelsim. Check the Xilinx answers database for record #2561. I had to do this, but I cannot remember the exact commands I used in Modelsim (wish I had written them down!). I do remember that Xilinx's TCL script did not work for me. The Xilinx source is in your directory $Xilinx\vhdl\src\unisims. I also just noticed that they include a perl script in $Xilinx\vhdl\bin\nt which purports to compile the libraries. Could be worth a try if you have perl installed. 2. Modify your modelsim.ini file to include lines like these: simprim = $MODEL_TECH/../simprim unisim = $MODEL_TECH/../unisim 3. Include the library in your source file: -- synthesis translate_off library unisim; use unisim.vcomponents.all; -- synthesis translate_on Those pragmas are for Synplify. Note: my computer is running pathetic ol' NT4, so the directory paths I have given may not be exactly the same on your computer. Barry Brown "Jim Raynor" <chris_cheung66@hotmail.com> wrote in message news:JfDU9.24993$8V5.2262500@news1.telusplanet.net... > hi, > > I am having problem in simulating the Virtex's Primitive (e.g CLKDLL, > BUFG...) using Modelsim. Could anyone tell me how to do it? I got errors > in the Modelsim like > > # WARNING[1]: main.vhd(244): No default binding for component: "ibufg". > (No entity named "ibufg" was found) > # WARNING[1]: main.vhd(247): No default binding for component: "clkdll". (No > entity named "clkdll" was found) > # WARNING[1]: main.vhd(248): No default binding for component: "bufg". (No > entity named "bufg" was found) > > Thanks..... > > Chris > > >Article: 51464
Hi Keith, > For dataflow, no. For state machines, I don't think HDLs can be > beat. Well, it depends. If you have a schematic library that allows you to draw a flow diagram and makes it drag and drop, it's REALLY easy...and easy to do...and easy to read. > The design is simply too large > to make it practical though. There is NO design that is "simply too large to make it practical", as it depends on how you draw your schematics. You actually think 1000 pages of TEXT is "easier"??? > > > * Time consuming > > > > I'd argue that....as well > > Again, schematics are nice for dataflow. I very much dislike > schematics for state machines. It depends on how it's drawn. Any tool can be abused, or used properly. Fought with, or worked with. > With the "proper library" I'd rule the world. Bingo, and that is why I DO rule the world ;-) > > Er, actually, that is not true. It IS used for very large designs that have > > high clock frequencies. > > VHDL is too. ;-) Er, yeah. That's why the fast PCI cores are done in schematics ;-) > > For most designs, it is better to simply use what you are most comfortable > > with. > > I'll dissent here. Documentation means something. My comfort > isn't everything. Hum. I think we strap you to a chair, and make you drink four 2L bottles of Diet Coke and see you say that after a few hours... > I document my VHDL to the nines (mostly > because even I can't remember what I did last month). I find it > hard to document schematics to the same degree. As I've said, a tool is only as good as the person using it. I have no problem documenting schematics, and far better than I've seen HDLs documented. And, as you've said, data path is just obvious...and therefore would require much less documentation. It even has a built-in block diagram. > > As with any thing engineering, any tool can be used exceptionally as > > well as poorly. > > Poor tools tend to be used poorly. Good tools may not be any > better, but there is at least a chance. ;-) Well, then...DON'T USE ORDAD! Regards, AustinArticle: 51465
> > Actually, it is VERY portable to another FPGA or ASIC with the proper > > libraries. > > I'd agree with that, however I would also argue that schematic is not very > portable between schematic entry tools. Of course, but Kevin said technologies, not tools, hence... ;-) > > There are pro's and con's of each methodology, for sure. HDLs for FPGAs has > > come a LONG way in the past 5 years, to where for MOST cases, it is equal or > > better. It is rarer that one actually NEEDS to do schematics. Also, you > > can basically use some HDLs as netlisters, and get an equal design out of it > > as you could with a schematic. it IS a lot of work...but it can be done. > > This is where I beg to differ. I really want to see that in person... > Proper support of the generate statements > and user attributes by the sythesis tools started to change that about 4 years > ago, Agreed, and as I said above... > and now the majority of the tools have the necessary hooks in them to do > low level design for performance/density when needed. Again, this is not an exception to what I said above... > The key to working > quickly with schematics is to work hierarchically and assemble a library of > reusable components (my schematic library had 2 bit slices of many functions, > for example). It is the construction of a comprehensive library to take > advantage of reuse that makes the difference. Agreed...and it's the same for VHDL, again, you aren't disputing what I said above here... > The same is true for working with > instantiated primitives (netlisting as Austin puts it) in HDLs: you build up a > library of placed instantiated parts, and if you do the library right you can > make it parameterized. Once you have assembled a reasonable library, netlisted > designs can be done just a quickly as strictly RTL designs, and really the only > difference is the bottom level of the hierarchy. VHDL offers considerably more > power for generating parameterized macros than is available with schematic. By > using parameters with the generate statements, a single macro design covers what > would have been dozens of schematic library elements. OK, I'm not seeing your begged differing here...as far as I can tell, we agree. AustinArticle: 51466
library unisim; use unisim.vcomponents.all; Is supported in Synplify after 7.2.1 - Ken McElvain Barry Brown wrote: > 1. You have to compile the xilinx unisim library in Modelsim. Check the > Xilinx answers database for record #2561. I had to do this, but I cannot > remember the exact commands I used in Modelsim (wish I had written them > down!). I do remember that Xilinx's TCL script did not work for me. The > Xilinx source is in your directory $Xilinx\vhdl\src\unisims. I also just > noticed that they include a perl script in $Xilinx\vhdl\bin\nt which > purports to compile the libraries. Could be worth a try if you have perl > installed. > > 2. Modify your modelsim.ini file to include lines like these: > simprim = $MODEL_TECH/../simprim > unisim = $MODEL_TECH/../unisim > > 3. Include the library in your source file: > -- synthesis translate_off > library unisim; > use unisim.vcomponents.all; > -- synthesis translate_on > > Those pragmas are for Synplify. > > Note: my computer is running pathetic ol' NT4, so the directory paths I have > given may not be exactly the same on your computer. > > Barry Brown > > > "Jim Raynor" <chris_cheung66@hotmail.com> wrote in message > news:JfDU9.24993$8V5.2262500@news1.telusplanet.net... > >>hi, >> >> I am having problem in simulating the Virtex's Primitive (e.g CLKDLL, >>BUFG...) using Modelsim. Could anyone tell me how to do it? I got errors >>in the Modelsim like >> >> # WARNING[1]: main.vhd(244): No default binding for component: >> > "ibufg". > >>(No entity named "ibufg" was found) >># WARNING[1]: main.vhd(247): No default binding for component: "clkdll". >> > (No > >>entity named "clkdll" was found) >># WARNING[1]: main.vhd(248): No default binding for component: "bufg". (No >>entity named "bufg" was found) >> >> Thanks..... >> >> Chris >> >> >> >> > >Article: 51467
"Kevin Brace" <kev0inbr1aceusen2et@ho3tma4il.c5om> ha scritto nel messaggio news:avupsr$ep2$1@newsreader.mailgate.org... [Schematic] > * Less portable to another platform (i.e., Xilinx to > Altera) Or just Xilinx to Xilinx: Foundation schematics are incompatible with ISE. -- LorenzoArticle: 51468
Basically, schematic entry tools are still in use only because people without a software background are still allowed into a FPGA design field. The day management will finally realize how much money can be saved by keeping these people (a.k.a. hardware engineers) out of all but the simplest FPGA designs - the time of the schematics will be over. These HW guys can't spell "version control" !!! Enough said. bktan1974@netscape.net (John Tan) wrote in message news:<eb4dd21b.0301120804.6a2e6729@posting.google.com>... > Hi, what is the merit & constraint of each of these design entry > methods > > - schematic design > - VHDL > > i have heard pple saying any changes in schematic entry, will cause > all timing to be changed and you got to check your timing again; is > this true ? ANd how about VHDL; is it really better? > > > I have last done a uni. project to implement a convolutional codec > using schematic entry method; and frankly i i can't imagine to program > the design in VHDL ...it's just too enormous the codes!Article: 51469
I heard some time ago that Cesys's Spartan-II PCI card cannot take a
burst transfer (Probably means the PCI bridge chip of the card signals
Disconnect with Data during the first data phase to cut off the burst
transfer.), and the card itself can only accept data at 1MB/s to 2MB/s
(Similar to ISA bus.).
However, because the PCI card already has a PCI bridge chip on it, you
don't have to deal with a PCI IP core, so it should be fairly easy to
get it working.
If you are not happy with the bandwidth restriction of the Cesys
PCI card, I will say that the other low cost alternative you have is to
buy Insight Electronics Spartan-II PCI Development Kit for $275 with a
parallel port JTAG cable, but you need a PCI IP core to get it working.
http://www.insight-electronics.com/cgi-bin/bvutf8/memec/scripts/local/mc_loc_b.jsp?Div=INSIGHT&Reg=AMERICAS&Country=UNITED_STATES&Lang=EN&EDOID=187428&Manu=XILINX
Xilinx's PCI IP core costs $2,000 or $5,000, although I heard that they
can donate it to you for free if it is being used for academic research.
Opencores.org's PCI IP core is free, but you might have hard time
getting it to work.
If those two don't work, it is possible to develop your own PCI IP core,
and use it with the Insight Electronics Spartan-II PCI card because I
have done that myself (Used only free tools like ISE WebPACK and
ModelSim XE-Starter.), but it will take many months developing the PCI
IP core itself, so I don't recommend that option.
Kevin Brace (If someone wants to respond to what I wrote, I prefer if
you will do so within the newsgroup.)
Pat Ford wrote:
>
> Hi All;
> I am looking at the xc2s_eval as a pci card for a small project ( 10 or so
> cards). What are your opinions on the card?
> We need Linux support, 32 IO (min) and the ability to have multiple 200Mhz
> counters. The board mentioned has a 37 pin sub D connector that makes things
> even nicer.
> Thanks
> Pat
Article: 51470Hello My name is Ann and I'm student from Poland. I have to make a presentation about Virtex, Virtex II and Virtex II Pro devices. I've got a few questions. What is a slice and what for it was developed? What are the major differences between Virtex, Virtex II and Virtex II Pro devices? If you have any presentation about those devices I would be very grateful for sending it to me. Thank you very much! AnnArticle: 51471
In article <f881b862.0301141000.6baec97c@posting.google.com>, Michael S <already5chosen@yahoo.com> wrote: >Basically, schematic entry tools are still in use only because people >without a software background are still allowed into a FPGA design >field. The day management will finally realize how much money can be >saved by keeping these people (a.k.a. hardware engineers) out of all >but the simplest FPGA designs - the time of the schematics will be >over. >These HW guys can't spell "version control" !!! Enough said. Ha Ha Ha Ha Ha... I admit I use schematics simply because thats how I think... It is a very convenient representation if thinking in terms of luts, flip-flops, SRLs, and placement. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 51472
Okay, you are right. Schematics is not very portable from one tool to another tool. Kevin Brace (If someone wants to respond to what I wrote, I prefer if you will do so within the newsgroup.)Article: 51473
its a databus from a very old game console ..... On Tue, 14 Jan 2003 15:07:08 +0800, Michael Hetherington <chinookREMOVE@REMOVEpacific.net.sg> wrote: >TigerMole wrote: >> I am glad to hear this :-) >> >> So i don't have to use some additional 74HCT4066 ?!! >> >> THX >> TigerMole >> >> >> On 13 Jan 2003 15:56:44 GMT, mikeandmax@aol.com (Mikeandmax) wrote: >> >> >>>Tiger growled- >>> >>>>Is it possible to implement a bidirectional digital switch >>>>in a CPLD ? I want to cut off a databus ... >>>> >>> >>>sure! I/O on most CPLDs is tristate-able - >>>here is a snippet of code fer-instance - >>> >>>port ( data_a, data_b :inout std_logic; >>> a__to_b, b_to_a : in std_logic) >>>. >>>. >>>. >>>.architecture >>>. >>>begin >>>data_a <= data_b when b_to_a else 'Z'; >>>data_b <= data_a when a_to_b else 'Z'; >>> >>>end; >> >> > >I thought the switch should look something like: > >port( a, b: inout std_logic; > c: in std_logic); > >Probably it would be hard to implement something like >this in FPGA. 4066 is analogue switch. So it also depends on >what bus you are switching i2c or usb? :-). The question remains. > >CheersArticle: 51474
Have you tried the data sheets on the Xilinx website? I think all the info you
need is in there. Regarding slices, it is a subgrouping in the CLB to keep the
architectural view looking more or less the same as it did with previous
generations. The logic in a slice is depicted rather clearly in the data sheet:
it is basically two 4-LUTs with associated flip flops, plus carry chain logic
for a 2 bit slice of arithemetic.
Ann wrote:
> Hello
> My name is Ann and I'm student from Poland. I have to make a presentation
> about Virtex, Virtex II and Virtex II Pro devices. I've got a few questions.
> What is a slice and what for it was developed?
> What are the major differences between Virtex, Virtex II and Virtex II Pro
> devices?
> If you have any presentation about those devices I would be very grateful
> for sending it to me.
> Thank you very much!
> Ann
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
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