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Yes, It's DOS, actually its a little more complicated with protected mode stuff, but basically your right. I can set up the address and buffer in the dos code, but I don't know where to stick this information in the PLX9054. I must be missing something in the documentation. There ought to be a register where I load the DMA address and buffer size. I just can't find it. Thanks Paul Austin Franklin wrote: > > "Paul Cousoulis" <paulcsouls@worldnet.att.net> wrote in message > news:3E2B40E7.5B7EE005@worldnet.att.net... > > Hi Austin > > > > I guess part of my problem is that I'm not using the PLX SDK. DJGPP is a > > protected mode DOS C compiler. I've been using it to test my FPGA > > design. I can read and write the PLX configuration address space and I > > can access the local bus to write the registers in the FLEX 6000. I need > > an address and a buffer for the DMA. > > What OS? I assume DOS? If so, your application should do a malloc and get > the address, with DOS there is no need to do virtual to physical address > translation, I do not believe...and you should be all set. > > AustinArticle: 51701
I will send third motion to contact their Tech Support. I have dealt with Sara Steigerwald and Vidyullatha Murthy who were both excellent in helping me deal with getting the most from the Synplicity tool in concert with the Xilinx flow. Clyde Ken McElvain wrote: > Later in this thread someone suggests contacting Synplicity support to > see if they can take a look at the setup and make suggestions. I have > to second that. > > Without being able to see the design I can give you a few things to > look for. This may be useful to others. > > Some background first: > One difference between between Synplify and other FPGA synthesis tools > is that it is heavily timing constraint driven. Most ASIC synthesis > tools behave this way also. The other strategy in use is to > compile for area or delay. Optimizing for delay would try to > minimize levels without much regard for resource use. Synplify will > try, in its estimation, to meet your timing goals with the > smallest area. For large designs this will usually give the best > real performance because it keeps the wires short and also keeps > you in a smaller (and cheaper) part. > > The complication is that Synplify is only estimating the routing delays > and can in some designs/paths be overly optimistic or pessimistic about > routing. It may therefor sometimes leave a timing optimization undone > because it thinks it already met the goal and is conserving area. > > 1) Check that the number of paths covered by constraints is similar. We > often see a large difference in the number of covered paths based on > constraints forwarded by the synthesis tools. It may be that the paths > you are seeing in the Synplify result are just not covered in the XST > result. > > 2) Synplify by default constrains I/O delays to 1 period of the > controlling clock. I don't think XST does. You can set default > input and output constraints of -100ns to match the XST constraints. > This is one common cause of (1) above. > > 3) Synplify may be underestimating routing delays. You can compensate > for this in Synplify's constraints. There is an adjustment option > in the clock, I/O, and register constraints that can be used to > tighten or loosen synthesis constraints without changing the > constraints written to the NCF. In the various pages of the constraint > editor (SCOPE) you will find columns labeled "route". Put your > adjustment there. A positive number of ns will tighten the constraint > and a negative number will loosen the constraint. Do not use extreme > values especially for I/O or register adjustments because it can be > like squeezing a balloon. Try to keep the values under 10% of your > clock period. The first place to try an adjustment is in the clock > constraint. > > 4) Constraint driven synthesis can backfire if you have a core with > significant setup or clock to out delay with no timing model. > Synplify's default assumption is 0ns setup and 0ns clock to out. > We should probably have used at least the flip-flop setup and clock to > q, but we didn't. We are working on the whole issue of modeling cores. > For now, if your critical paths enter or exit a core, then the best > thing to do is to supply a model. > > Hopefully one of these will clear up your problem. If not, then > I would repeat the first suggestion of contacting Synplicity support. > > - Ken McElvain, CTO > Synplicity > > Roger Green wrote: > > > I have recently been driven to switch to Synplify synthesis, from XST, for a > > fairly complex PCI core VHDL design targeting a Virtex 300 in order to work > > around various ISE tool bugs (which is another story all together). After a > > fairly painful conversion of constraints (for both timespecs and previous > > floorplannning) and getting the design to actually compile again, I have > > noted that the logic paths now failing to meet my timespecs are in logic > > that previously was not a problem with XST synthesis, although there were > > problems paths then also. At first glance, my "gut" says that there are > > more logic levels (LUTs) being used in the problematic paths, but I don't > > have a direct proof of that, since I never actually looked at these specific > > paths with the XST runs. I am using the identical "max" effort settings for > > PAR settings as before the synthesis tool switch. > > > > I was wondering if any of the experts here have had any similar or different > > experiences regarding the "performance" of these two tools on the same > > source design. Or perhaps someone could point me to some links to any > > "objective" comparison of these tools and/or information regarding what > > types of logic each is better/worse at optimizing? > > > > -- > > Roger Green > > B F Systems - Electronic Design Consultants > > www.bfsystems.com > > > > > >Article: 51702
"Austin Franklin" <austin@da98rkroom.com> writes: > How do you know what the "desired effect" is, if no one specified it in the > first place? The desired effect is specified by the language semantics. > You are combining optimization with compilation. They are different. It's essentially impossible to find a non-optimizing compiler these days. Even when you give "-O0", you usually get some simple optimizations. In some cases, the back end is not even capable of generating code unless certain code transformations (which may or may not be optimizations) have been done first. > > Thus it is not essential to have a spec for what > > the output of the compiler will be, but rather what things it may do. > > I don't know what you mean by "what things it may do", is that not it's > "output"? What else can "it do"? Hopefully my laundry ;-) I meant what things the optimizer can do. It has to preserve certain invariants. As long as it does that, you don't need a spec (other than the actual compiler source code) that says exactly what you'll get for any given input. > > However, there are so many possibilities for what might happen that it > > is impractical to say "if you write an if statement that tests the third > > integer component of a record, and the else portion contains an assigment > > of a local float variable from a literal followed by continue statement, > > you will get the following code...". > > Again, I disagree. Pre-optimized processing is quite deterministic, as is > optimization, but with optimization you globalize the input. Optimization doesn't just happen at one level. There are usually some optimizations done on the parse tree, some on intermediate code, and some on generated code. At no stage in that process is your original code completely compiled but not at all optimized.Article: 51703
vaxent@my-deja.com (Davar Robdan) writes:
> I'm a VHDL learner, and looking for some VHDL source.
> Is there anyone who have a 32bit ALU with floating point written in
> VHDL? Or can you tell me where on the web I can find it?
Yes, there is, and you can find it on the web at:
http://www.google.com/
Article: 51704Hi, The Xilinx PCI core "works" in PCI-X slots, but you have to make sure your board design is compliant with the PCI 2.3 specification, and you are also advised to check the system BIOS settings for slot initialization. It is possible to have the BIOS ignore/bypass the bus mode detection and default to a specific mode. I have a machine where you can set "AUTO" or select one of several specific bus modes... Determination of what bus mode (PCI or PCI-X) should be used on a given bus segment is a function of the PCIXCAP signal. In general, this signal is not to be connected to the FPGA in an FPGA based design. As such, it is typically a PCB design issue, not a FPGA configuration speed issue. The operation of PCIXCAP is analogous to M66EN for sensing if a bus segment is capable of 66 MHz operation. It is true that devices are supposed to capture the bus initialization pattern at the rising edge of RST#. However, if a card is correctly designed as PCI only, its PCIXCAP pin is tied to ground, and the bus host should NEVER attempt to initialize the bus in PCI-X mode. An example of where you can get into trouble with your PCB design: If you are building a PCI card, and you do not plate all the GND pins on the edge connector and bus them together as required in the specification. One of those GND pins was changed to PCIXCAP in the PCI-X Addendum. If that is one that you failed to plate, the system would see you PCI-only card as a PCI-X capable device... Hope that helps, EricArticle: 51705
Hello, I'm pleased to announce the initial release of Confluence 0.1; a new hardware design language created by Launchbird Design Systems, Inc. Confluence is a simple, yet high expressive language that compiles into Verilog, VHDL, and C. Its implicit parallelism and modular style still feels like coding in Verilog or VHDL, yet the features of the language provide a level of flexibility unknown to either of the two. We are currently in the process of assembling a group of systems coded in Confluence to act as both benchmarks and as tutorials for our customers. The code generated from two of these systems has already been released to OpenCores.org: http://www.opencores.org/projects/cf_fft/ http://www.opencores.org/projects/cf_cordic/ To give you an idea of the typical code density, the bulk of CF_Cordic was written in just under 100 lines of Confluence code and CF_FFT was only twice that. Our team has been developing Confluence for close to a year and we feel the time is right to slowly release this product into the market. We are looking for design engineers and consultants not afraid to learn a new language to join our Confluence Beta Program. Drop me a line if interested. Regards, Tom PS: Please excuse the website. We're pouring our resources into development. -- Tom Hawkins tom1@launchbird.com Launchbird Design Systems, Inc. http://www.launchbird.com/Article: 51706
hmurray@suespammers.org (Hal Murray) wrote in message news:<v2lvoj4eb6aif5@corp.supernews.com>... > >Sure, any bad designer can create an unreadable design using any set > >of tools. (or even a good designer who wants his design to be > >unreadable as Job Security). What I an saying is that it IS easier to > >make HDL code understandable than making schematic design, because you > >are working at a higher level of abstraction: you don't have to > >examine a mess of gates and FFs to understand what this counter/FSM is > >supposed to do. > > I don't see how HDLs automatically work at a higher level of > abstraction. > > I can put a whole CPU in a single box on schematics. > Is that high enough? That's my favorite for management presentations: I draw a "system block diagram" - a big nicely-colored rectangle with the caption "System" ;) If you want a working system, someone must design actual logic...either as gates/FFs or "higher level of abstration". It just means that istead of drawing an AND gate (one inverted input) to determine next-state, you write "if condition1 and NOT condition2" - it's easier to understand what you are trying to do. When going up the hierarchy, interconnected blocks are blocks, and it doesn't matter if they are drawn graphically or written as blocks of text.Article: 51707
I forgot to mantion. The program works on desktops normally. Some of the desktops have WinXP (the same as laptops) and some of them Win2000. The only difference is that the laptops have 256MB RAM and the desktops, at least, 512.Article: 51708
Yes, the license is NOT hacked. It's the original one.Article: 51709
Witam, Today I tried recompiling one of Altera projects using free MaxPlus and I discovered that FLEXlm says that time has been set back. Althoubg I did not believe in success I tried downloading new license and reinstalled MaxPlus. Of course it did not help. FELXlm website wasn't very usefull. -- Pozdrowienia, Marcin E. Hamerla "Płoń, płoń, płoń parlamencie, spali Cię ogień na historii zakręcie."Article: 51710
OK, guys. I have found the solution. It seems that the laptops are using too much of RAM. I have reduced in display properties setings the colors setings to 16 bits, and now everything works fine. Thanks for your help.Article: 51711
For DMA channel 0 it is DMAPADR0(PCI address 84h) & DMASIZ0(PCI address 8ch). For DMA channel 1 it is DMAPADR1(PCI address 98h) & DMASIZ0(PCI address A0h). It took me about 15 sec to find out the info in the PCI 9054 Data Book. You are really missing something. Probably a Data Book. Paul Cousoulis <paulcsouls@worldnet.att.net> wrote in message news:<3E2B51C7.C433D0C0@worldnet.att.net>... > Yes, It's DOS, actually its a little more complicated with protected > mode stuff, but basically your right. I can set up the address and > buffer in the dos code, but I don't know where to stick this information > in the PLX9054. I must be missing something in the documentation. There > ought to be a register where I load the DMA address and buffer size. I > just can't find it. > > Thanks > Paul > > Austin Franklin wrote: > > > > "Paul Cousoulis" <paulcsouls@worldnet.att.net> wrote in message > > news:3E2B40E7.5B7EE005@worldnet.att.net... > > > Hi Austin > > > > > > I guess part of my problem is that I'm not using the PLX SDK. DJGPP is a > > > protected mode DOS C compiler. I've been using it to test my FPGA > > > design. I can read and write the PLX configuration address space and I > > > can access the local bus to write the registers in the FLEX 6000. I need > > > an address and a buffer for the DMA. > > > > What OS? I assume DOS? If so, your application should do a malloc and get > > the address, with DOS there is no need to do virtual to physical address > > translation, I do not believe...and you should be all set. > > > > AustinArticle: 51712
Folks, Just wondering if anyone has written a parser for Xilinx timing reports yet. I need one for some research I'm doing and don't want to reinvent the wheel unnecessarily! Cheers, Richard --- Richard Bannister Department of Computer Science Trinity College DublinArticle: 51713
Hello, We have built a board with a Virtex2 (Xc2V500-456) Any attempt to configure via the JTAG port fails. If I try to read the idcode the answer is 0. The only successful configuration is the slave selectmap. Software: Ise 5.1 Windows XP Any suggestion please? Balint Seres sb@camex.huArticle: 51714
Austin Lesea <austin.lesea@xilinx.com> wrote in message news:<3E28729F.1881CF5E@xilinx.com>... > Marc, > > Gosh, too easy! > > Austin Indeed. Perhaps we make it too easy for some people coming to the newsgroup asking questions! Marc > > Austin Lesea <austin.lesea@xilinx.com> wrote in message news:<3E258425.7C2ED314@xilinx.com>... > > > > > > Cisa wrote: > > > > > > > Now I have a clk whose frequency is 30.72,and I want to use DCM > > > > to generate another clk whose frequency is 1.28MHz. > > > > How can I get it?I failed in reality.Pls give me some advance. > > > > > > Cisa, > > > > > > The DCM outputs (all execpt for the CLKDV and CLK2X) have a minimum > > > output frequency of 24 MHz. > > > > > > CLK2X is 48 MHx min, and CLKDV is 24/16 MHz (1.5) min. > > > > > > I suggest to use a simple synchronous counter to simply divide by 24 > > > (synchronously). At these low frequencies, you do not need the 100 ps > > > alignment offered by the DCM. > > > > Or perhaps use the DCM to divide by 12, then use a single flop to do > > the final divide by two... > > > > MarcArticle: 51715
Hi Ken, Thanks for the good general pointers and description of the Synplify tool operations. I'm certain it will be helpful in my continuing efforts to optimize my current design as well as to others here. > The complication is that Synplify is only estimating the routing delays > and can in some designs/paths be overly optimistic or pessimistic about > routing. It may therefor sometimes leave a timing optimization undone > because it thinks it already met the goal and is conserving area. > > 1) Check that the number of paths covered by constraints is similar. We Actually, I'm not constraining my design very much at all for the synthesis tool. Other than using a global directive for clock period and telling both tools to "not share resources" or equivalent to attempt to prevent them from optimizing out detailed rtl level source that I put there intentionally. I'm also optimization for "speed" in both cases, as this particular design has no size concerns at the moment. Its only using about 40% of a Virtex 300 from a CLB perspective (but all the block RAM). > > 2) Synplify by default constrains I/O delays to 1 period of the > controlling clock. I don't think XST does. You can set default > input and output constraints of -100ns to match the XST constraints. > This is one common cause of (1) above. > I'm actually including specific IOB types in my source wrapper and directing PAR to use IOB registers for all my critical output signals. Synplify, unfortunately still insisted on optimizing away several fanout registers I had coded specifically to allow this to happen. I had to add several "syn_preserve" attributes in my source for those register/signals to prevent this from happening, in spite of the "don't share" global directives. > 4) Constraint driven synthesis can backfire if you have a core with > significant setup or clock to out delay with no timing model. > Synplify's default assumption is 0ns setup and 0ns clock to out. > We should probably have used at least the flip-flop setup and clock to > q, but we didn't. We are working on the whole issue of modeling cores. > For now, if your critical paths enter or exit a core, then the best > thing to do is to supply a model. > Since the Xilinx PCIcore is essentially a very low level netlist, and no synthesis constraints were recommended other than the global settings I metioned earlier, there doesn't appear to be a problem there. However I'm only using a 33MHz interface at the moment, so I wouldn't expect that to be very demanding for a Virtex part. Xinlinx, similar to my approach, provides detailed constraints for their core at the place and route level, not synthesis. Again, thanks and best regards. RogerArticle: 51716
tom1@launchbird.com (Tom Hawkins) wrote in message news:<833030c0.0301192000.24caa78b@posting.google.com>... > Hello, > > I'm pleased to announce the initial release of Confluence 0.1; > a new hardware design language created by Launchbird Design Systems, Inc. > > Confluence is a simple, yet high expressive language > that compiles into Verilog, VHDL, and C. > > Its implicit parallelism and modular style still feels like coding in Verilog > or VHDL, yet the features of the language provide a level of flexibility > unknown to either of the two. > > We are currently in the process of assembling a group of systems coded in > Confluence to act as both benchmarks and as tutorials for our customers. > The code generated from two of these systems has already been released to > OpenCores.org: > > http://www.opencores.org/projects/cf_fft/ > http://www.opencores.org/projects/cf_cordic/ > > To give you an idea of the typical code density, the bulk of CF_Cordic was > written in just under 100 lines of Confluence code and CF_FFT was only > twice that. > > Our team has been developing Confluence for close to a year and we > feel the time is right to slowly release this product into the market. > We are looking for design engineers and consultants not afraid to learn > a new language to join our Confluence Beta Program. > > Drop me a line if interested. > > Regards, > > Tom > > PS: Please excuse the website. We're pouring our resources into development. Great, just what the world needs another HDL! So who are the people behind it, and why? Will the language be open? The ASIC world has already seen most of the C languages die off, SystemC will probably stick around though, maybe HandelC. Verilog is now splitting into multiple forks, but IMHO Superlog is the way to go! Verilog/VHDL have been under the same committe now for awhile so that war is over. Verilog RTL can already be compiled to efficient C, I do it, others have too. JJArticle: 51717
The timing analyzer tool available in both the ISE and older design manager front ends (or a standalone tool itself) provides a nice filtered view of the timing analysis report and will provide different sets of results per your demand (only failed paths, different speed grade, different number of items reported). If you want to understand the timing results, this - along with the View settings to bring out the physical elements in the overall delay - will provide you with a lot of information. If you're looking to parse information to input directly to another tool you're developing, you'll need to supply a little more info, I'd expect. I never did like the long text versions of the timing reports. I was very happy when the timing analyzer tool added the nice constraints browsing capabilities. "Richard" <gospod88@hotmail.com> wrote in message news:f7779f31.0301200252.d61da6b@posting.google.com... > Folks, > > Just wondering if anyone has written a parser for Xilinx timing reports yet. > > I need one for some research I'm doing and don't want to reinvent the wheel > unnecessarily! > > Cheers, > Richard > > --- > > Richard Bannister > Department of Computer Science > Trinity College DublinArticle: 51718
"Eric Smith" <eric-no-spam-for-me@brouhaha.com> wrote in message news:qhk7h0ee6u.fsf@ruckus.brouhaha.com... > "Austin Franklin" <austin@da98rkroom.com> writes: > > How do you know what the "desired effect" is, if no one specified it in the > > first place? > > The desired effect is specified by the language semantics. > > > You are combining optimization with compilation. They are different. > > It's essentially impossible to find a non-optimizing compiler these days. That doesn't matter. I have no problem with it optimizing...it SHOULD optimize. If anything, the worst it'll do is do a better job, as I was able to do my job by creating a construct that allowed it to do what I wanted. > > > Thus it is not essential to have a spec for what > > > the output of the compiler will be, but rather what things it may do. > > > > I don't know what you mean by "what things it may do", is that not it's > > "output"? What else can "it do"? Hopefully my laundry ;-) > > I meant what things the optimizer can do. It has to preserve certain > invariants. As long as it does that, you don't need a spec (other than > the actual compiler source code) that says exactly what you'll get for > any given input. Hum. I certainly don't design things like that. I have an expected result I am trying to get, and I design something to give me that result...I don't just make a random design that hopefully gives me some random result... Gee, no wonder I get so much work fixing things that people can't understand why it doesn't work...and the fact is, most of the time it's simply they didn't specify the problem very well, and therefore weren't able to understand what they needed to do to solve the problem. > > > However, there are so many possibilities for what might happen that it > > > is impractical to say "if you write an if statement that tests the third > > > integer component of a record, and the else portion contains an assigment > > > of a local float variable from a literal followed by continue statement, > > > you will get the following code...". > > > > Again, I disagree. Pre-optimized processing is quite deterministic, as is > > optimization, but with optimization you globalize the input. > > Optimization doesn't just happen at one level. Of course, I never said that was the case. You're not getting the point here. If you don't understand the need and usefulness for what I (and many others) said have found vast usefulness for, I don't have the time to explain it to you, as it's far more than I could explain in a few posts. I did not say that EVERY circumstance warrants such, but knowing how the tools do what they do CAN be very useful, just like understanding the architecture of the chips you are designing for. So, you can either try and understand it or simply believe it doesn't serve any useful purpose (when I clearly know it does...and...perhaps you might want to figure out why that is that I believe it does, and you believe it doesn't...and, not to sound arrogant, it's not because I don't know what I'm talking about). AustinArticle: 51719
Hi, I am facing problem in Arm-integrator board where communication between Arm and PLD is possible. The problem is as follows: I have written own interrupt handler routines(SWI handler routine, fiq and irq handler routine). I have written a small program to enable all the interrupts(like Uart) and service them properly. When I execute the program alone, The program behaves properly. Now I have put one USB code in PLD portion and enabled srtipe to pld bridge and inetrrupt sources. The problem is if the software application raises one SWI the processor just hangs, it does not go to SWI handler. What can be the source of problem? why that SWI interrupts is not egtting processed? 2. I am using AXD-Debugger for debugging. if I use scanf() or gets() functions in my c-program it does not stop in AXD-window and sometimes give data_abort inetrrupt..why is this so? is that use of scanf() and gets() or getchar() function is prohibited in AXD-Debugger? Sudip Saha sudipsaha5@yahoo.comArticle: 51720
"Ray Andraka" <ray@andraka.com> wrote in message news:3E2B50BE.14EBFE8@andraka.com... > As does synthesis. Synthesis goes by a set of rules, however when the rules > get sufficiently complex, the exact implemention tht results can be hard to > accurately predict. It HAS to be accurately predictible or it be full of bugs and give unpredictible results! > However if you change the input at all, > the output may change a lot in response to a subtle change because an > alteration in the way the rules are applied to the code. Yes, but the rules are random? Somehow aren't "known"? I'm not following you here, or agreeing with you. I don't disagree that they can't "test" every possible case, of course not...but for any GIVEN case, the output should be predictible...and the set of rules SHOULD be known, it doesn't make them up on the fly! What you are suggesting is a system that would have a very high potential for buggy output, and be poor engineering at best...where the tool can become unwieldy and possibly useless... Causing you to have to possibly take an excessive amount of time to discover said problem and then TRY to work around, what would be, a tool "problem". Perhaps this is rare, but the point is, the potential in your scenario is there. Of course it's there for any tool, no doubt. But it disturbs me that people actually believe in this "random" nature by design...instead of, what I would consider sound engineering. AustinArticle: 51721
Hello All, Looking for Virtex 2 FPGA development board with parallel port or serial port and USB port. Preferably A/D and D/A on it as well for rapid prototyping applicaitons, 1 milllion gates+. Can any of you recommend companies that do such boards. Tanks. EdizArticle: 51722
Check the links on http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=protoboards_protoboards_page Ediz Cetin wrote: > Looking for Virtex 2 FPGA development board with parallel port or serial > port and USB port. Preferably A/D and D/A on it as well for rapid > prototyping applicaitons, 1 milllion gates+. >Article: 51723
Hello, I was wondering if it is possible to implement 2 ring oscillators on an fpga (xilinx or altera) with very similar frequencies (difference in periods: ~1ps, approximate frequency: 100-500MHz). It is paramount that the 2 frequencies can be controlled to be able to acheive the period differential of ~1 ps. btw, what would be a reasonable jitter value for an fpga-implemented ring oscillator ? thx -FrankArticle: 51724
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