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Has anyone experienced problems with the XCV2500-FG456 device from Xilinx? The device DCMs appear to lose lock due to internal ground bounce. Initially, my design was exceeding the SSO guidelines. In addition, about 750 mV of periodic noise was visible when measuring Vcco with respect to ground. By switching driver strengths, adding extra decoupling caps, and utilizing unused pins as virtual grounds, I am now meeting the SSO guidelines, and the noise has been reduced to 60 mV. Despite these improvements, the DCMs still lose lock. It just takes two days instead of two minutes. Has anyone experienced similar behavior with the 500 part or the wire-bond 456 package? Any suggestions on how to solve this problem? As a side note, I have not experienced any of these problems in using the 3000 or 4000 parts. John MArticle: 51776
Hi I've been working on creating my own 32bit floating point arithmetic library. It is not yet complete (I have yet to start the division) and may also still contain some bugs. If you are interested, I'll send you the VHDL sources. Maybe you can help me find some bugs. However, if you would like to try writing your own library, I can recommend the following book: Omondi, A.R. "Computer Arithmetic Systems - Algorithms, Architecture and Implementations", Prentice Hall International 1994. ISBN: 0-13-334301-4 I also used some articles on floating point arithmetic which I got from citeseer.nj.nec.com. Good luck Eduard Kriegler Kriegler@sun.ac.za "Davar Robdan" <vaxent@my-deja.com> wrote in message news:81d9346a.0301191254.11d65100@posting.google.com... > Hi there all, > > I'm a VHDL learner, and looking for some VHDL source. > Is there anyone who have a 32bit ALU with floating point written in > VHDL? Or can you tell me where on the web I can find it? > > Thank you > VaxenTArticle: 51777
Which one is the "best"? What are the various advantages and disadvantages of each one? Thanks. Rog.Article: 51778
Hello all, I want to know how do I add a switch to a ISE command in Project navigator, without dos command window (if is possible). Any sugestions? 10xArticle: 51779
Hi - Do you have separate decoupling for the VCCAUX pins? You may want to peruse the Xilinx Answers Database for information on VCCAUX decoupling. The last time I did so, the information I found wasn't particularly useful, but you may be luckier. Bob Perlman On 21 Jan 2003 10:36:46 -0800, statepenn99@yahoo.com (John M) wrote: >Has anyone experienced problems with the XCV2500-FG456 device from >Xilinx? The device DCMs appear to lose lock due to internal ground >bounce. Initially, my design was exceeding the SSO guidelines. In >addition, about 750 mV of periodic noise was visible when measuring >Vcco with respect to ground. By switching driver strengths, adding >extra decoupling caps, and utilizing unused pins as virtual grounds, I >am now meeting the SSO guidelines, and the noise has been reduced to >60 mV. Despite these improvements, the DCMs still lose lock. It just >takes two days instead of two minutes. Has anyone experienced similar >behavior with the 500 part or the wire-bond 456 package? Any >suggestions on how to solve this problem? As a side note, I have not >experienced any of these problems in using the 3000 or 4000 parts. > >John MArticle: 51780
John, I suggest you open a case with the hotline. Yes, if you have really terrible ground bounce, then you will exceed the input jitter tolerance specification, and the DCM will not lock. App note 623 on powering is helpful, and to really see what is going on, you need to pin out a IO driven to a logic '0' to see just how bad the ground bounce is inside the die. http://support.xilinx.com/xapp/xapp623.pdf fg are wire bond, and are more sensitive to strong currents (more inductance in the ground returns) than the flip chip packages you mention. They require better bypassing techniques to get the same level of jitter performance as a flip chip package. All design (SSO tables, DCM operation, system jitter, etc) assumes that the ground bounce stays below +/- 100 mV peak to peak for proper operation. There is also a requirement on Vccaux, which powers the DCM. http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=13756 (tech answer 13756) There may be other issues as well that our hotline is well trained in, and can quickly get you up and running, Austin John M wrote: > Has anyone experienced problems with the XCV2500-FG456 device from > Xilinx? The device DCMs appear to lose lock due to internal ground > bounce. Initially, my design was exceeding the SSO guidelines. In > addition, about 750 mV of periodic noise was visible when measuring > Vcco with respect to ground. By switching driver strengths, adding > extra decoupling caps, and utilizing unused pins as virtual grounds, I > am now meeting the SSO guidelines, and the noise has been reduced to > 60 mV. Despite these improvements, the DCMs still lose lock. It just > takes two days instead of two minutes. Has anyone experienced similar > behavior with the 500 part or the wire-bond 456 package? Any > suggestions on how to solve this problem? As a side note, I have not > experienced any of these problems in using the 3000 or 4000 parts. > > John MArticle: 51782
And logic leading into and out of that described by the case statement, and the
number of cases, etc. There are quite a few variables that affect the construction,
hence the apparent ambiguity. Like I said before, if you need to do better than what
the tools do, then you need to push a little harder. Frankly, I find it easier to be
explicit (structural instantiation) in these cases rather than doing the 'pushing on
a rope' trick in trying to second guess the tools. The point is, there is a
mechanism in place to permit you to be explicit in the cases where it matters, and to
let the tools infer logic based on the internal set of rules when it is not. As an
exercise, you might try using a case statement in varying situations and see how the
tool responds. I think you will see the results vary by aggressiveness of the
timing, number of cases, surrounding logic etc. There will also be variation due to
optimization of the logic of the case by itself. I certainly don't see a cut and
dried cookbook result coming out of it for all the possibilities you get with a real
world circuit.
Magnus Homann wrote:
> Ray Andraka <ray@andraka.com> writes:
>
> > I never said random. The issue is that the rules set is a very complex set of
> > rules, based not only on coding style, but also on performance, area (a default
> > setting if you don't specify it), what the logic between the registers actually
> > is etc.
>
> And timing constarints, I would hope. And thus the architecture. And
> speed grade.
>
> Homann
> --
> Magnus Homann, M.Sc. CS & E
> d0asta@dtek.chalmers.se
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 51783Can anyone suggest any litterature concerning ring oscillators in fpgas ? - Frank frank8017@excite.com (frank) wrote in message news:<60bf6cad.0301201203.7b4a0ac5@posting.google.com>... > Hello, > > I was wondering if it is possible to implement 2 ring oscillators on > an fpga (xilinx or altera) with very similar frequencies (difference > in periods: ~1ps, approximate frequency: 100-500MHz). It is paramount > that the 2 frequencies can be controlled to be able to acheive the > period differential of ~1 ps. > btw, what would be a reasonable jitter value for an fpga-implemented > ring oscillator ? > > thx > > -FrankArticle: 51784
> I am trying to send characters serially using Atmel FPSLIC Board. Does any > one knows how to do that . Both serial ports of Atmels FPSLIC board are connected to hardware UARTs. These are controlled by the AVR microcontroller. You find them documentated in the datasheet (AVR peripherials section) and in app-notes on Atmels web page. If you want to add more UARTs to your project, you will have to program them in AVR software (see the usual AT90 AVR tinkerer pages) or model them with VHDL (see opencores.org et al).Article: 51785
Nial Stewart napisal(a): >> Ok, I believe it but first I would like to know if I should cut down >> windows and reinstall OS or there is simpler solution. > >I would completely un-install Flexlm then use a registry cleaner >(I've used RegCleaner from http://www.vtoy.fi/jv16/shtml/software.shtml >before) to completely remove all traces of Flexlm from the >registry. Re-install Flexlm and see if it works. I got help from Altera support. Solution was simpler: I searched for all the files with date newer than 2003-01-21 and changed their dates. -- Pozdrowienia, Marcin E. Hamerla "Płoń, płoń, płoń parlamencie, spali Cię ogień na historii zakręcie."Article: 51786
> I would completely un-install Flexlm then use a registry cleaner > (I've used RegCleaner from http://www.vtoy.fi/jv16/shtml/software.shtml > before) to completely remove all traces of Flexlm from the > registry. Re-install Flexlm and see if it works. FlexLM, at least some versions of it, store a special sequence in disk sector lba 0x20 (dec 32) of the boot harddrive. This is an unused area on all harddrives larger than 8GB. With a disk sector editor you can spot the sector easily. It contains random garbage data, while the sourounding neighbour sectors are cleared with zeros. A full format, and even re-partitioning the drive won't wipe that unused area. So, to "uninstall" FlexLM completely, one has to manually erase that sector after the normal uninstall procedure. Note that editing disk sectors can cause damage to your data, if not done right.Article: 51787
I've heard of that, but didn't know that you can delete that sector. Which
tool (disc sector editor) do you use ?
regards,
--
Domagoj Babic
domagoj (et) engineer.com
"jetmarc" <jetmarc@hotmail.com> wrote in message
news:af3f5bb5.0301211308.17b40244@posting.google.com...
> > I would completely un-install Flexlm then use a registry cleaner
> > (I've used RegCleaner from http://www.vtoy.fi/jv16/shtml/software.shtml
> > before) to completely remove all traces of Flexlm from the
> > registry. Re-install Flexlm and see if it works.
>
> FlexLM, at least some versions of it, store a special sequence in disk
sector
> lba 0x20 (dec 32) of the boot harddrive. This is an unused area on all
> harddrives larger than 8GB. With a disk sector editor you can spot the
> sector easily. It contains random garbage data, while the sourounding
> neighbour sectors are cleared with zeros.
>
> A full format, and even re-partitioning the drive won't wipe that unused
area.
> So, to "uninstall" FlexLM completely, one has to manually erase that
sector
> after the normal uninstall procedure.
>
> Note that editing disk sectors can cause damage to your data, if not done
> right.
Article: 51788On Tue, 21 Jan 2003 13:43:24 -0500, Roger wrote: > Which one is the "best"? > > What are the various advantages and disadvantages of each one? > > Thanks. > > Rog. Verilog is more consise and easier to read. Simulation speeds for Verilog are much faster and in my experience there are lot fewer synthesis problems with Verilog because the language is much simpler.Article: 51789
Definitely. When using blockram bits for register remeber to partition the registers. What I mean to say is that try grouping the registers of the same kind together in one block ram. Though this may cause wastage opf ram blocks,but access to parallely updated registers becomes easier. Amit dileepjkurian@yahoo.com (DILEEP) wrote in message news:<d07c8bc2.0301202059.81a924d@posting.google.com>... > hi, > i have around 150 registers(16 bit) in my design, can i use Block > Ram bits for registers. i am using xcv800 Xilinx fpga. > Thanking you > Dileep > Acl Hyderabad > IndiaArticle: 51790
john jakson wrote: > SW engineers find Seq easy & Par hard, ie Thread safety issues > HW engineers find Par easy & Seq hard, ie buggy state machines My guess is SW engineers writing parallel SW is somewhere inbetween because time and space are thrown into the problem. How to balance the work done on each processor and where the data is is something the user can and must mess with. It's kind of like messing with cache but much worse. > > do j=1,n > > do i=1,n > > a(i,j) = k1*b(i+1,j) + k2*b(i-1,j) > > enddo > > enddo > > This sort of computation isn't even remotely difficult or interesting > for ASIC/FPGAs. Even if this loop nest is distributed across 250 nodes each of which has 4 processors on a shared bus? There's a lot of synchronization and communication going on in this example. I agree it's simple compared to other things done on parallel machines but it's not trivial. > For a any computer, throughput is figured by dividing total no of > math/move operators required into total capability of machine > available, this usually gives a good best case upper bound. Then start > dividing by a fudge factor for unforseens. I usually don't see compute > times ever given for SW since SW engineers either don't care or don't > know, x86s are now basically unpredictable (1 op per Hz is my rule). > Embedded & DSP SW guys do generally know because the cpu/DSPs are more > predictable & slower and the performance is part of the spec. Cycle > counting seems to be alien to SW guys, but all HW design requires > detailed cycle planning of all math operations & mem rd/wr. I can't talk for all SW guys but I can talk a little about scientific computing. They don't usually care about absolute numbers of operations so much as the complexity of an algorithm (is it O(n^2) or O(n log n)?) because they just have big problems that they want done in as little time as possible. They don't have hard and fast time constraints. It's really a matter of how big of a problem can they solve in 8 hours (overnight run time) > In HW, same rule, except you get to determine whether real estate > gates/luts are used for muls (about 2000 gates) or adders, muxes, mems > etc. In modern FPGAs the 18.18 muls & memories are available in the > fabric. For this example you could use 2 muls, an adder, 2 mem blocks > 1 dual ported b[] and one single ported a[] and a state machine. But > the b[] refs can be a single mem rd so now only a single dual port or > 2 single port mems needed. The i+1 & i-1 would also be combined with > the loop counter and delay registers. Compute time is now n*n clocks > which could be upto 120MHz or more. Things can be speeded up more by > replicating the engine m times, but you are limited to 2 mem accesses > per cycle per block ram. m has to be big. Remember, the fastest computer on this planet runs at 40TFlops. So assume there are 1000 blocks of ram (typical supercomputer). Something not obvious here is that the processor that computed b(i,j) is also the one that computes a(i,j). Also, the memory block that contains a(i,j) also contains b(i,j). This means that b(i-1,j) will not be in the same memory block as the one next to the processing circuitry that computes a(i,j) for all i,j. So some communication/synchronization is required to move the data. > So FPGAs cycle about 10-20x slower than P4s, but you can plan on >100 > *+ [] & thousands of other small ops per cycle for a huge improvement > over x86 & you can still throw in 1 or more cpus, hard or soft. If there's 100,000 lines of code, of which 10,000 is critical, I don't know if it's realistic to assume the fpga can do all the critical stuff. Maybe it can if the fpga is treated as a specialized coprocessor and, for example, implements the BLAS library. > Ultimately, it has nothing to do with quality of SW tools, only > breadth & quality of HW-SW design knowledge, and very little of that > design know how exists in any SW tools. The tools are good enough for > most HW people to do what they want. This is what I'm trying to get at. The problem with scientific computing is that the people that write the software won't/can't design hardware. HW designers can but they cost a lot more than a C compiler targeting a standard cpu. So a solution with FPGAs requires the compiler to do a lot. What you're saying is current compilers can't take fortran or ansi C and build an fpga. Buried in this was a discussion of whether the fpga should do everything or just data movement but reducing the problem doesn't seem to help much. It sounds like a better way to improve C or Fortran might be to use an fpga as a coprocessoer that implements common math routines or common communication protocols and let the user treat that as fixed hardware. I'm still curious about one thing. Do HW people have to muck around with anything after the verilog or vhdl is optimized?Article: 51791
I have some project files that I created with Xilinx Foundation Series 2.1i Student Edition. The extension of the project file is .pdf. Now I installed Xilinx ISE 4.2i Student Edition. They change the project extension to .npl and I can't seem to open my old project file with this new software. Is there anyway that I can convert the old project file so I can open it with the new 4.2i software? Thanks!Article: 51792
"Roger" <rogerwilson@hotmail.com> wrote in message news:XDgX9.2707$Lm4.191024@newsfep2-win.server.ntli.net... > What are the various advantages and disadvantages of each one? From what I heard, Verilog is used in the United States for commercial civilian purposes. VHDL is used in the United States for the defense department. VHDL is more commonly used in Europe. Verilog is simpler. If you know VHDL, it is easy to learn Verilog. If you know Verilog, it is still hard to learn VHDL.Article: 51793
"Roger" <rogerwilson@hotmail.com> wrote in message news:<XDgX9.2707$Lm4.191024@newsfep2-win.server.ntli.net>... > Which one is the "best"? > > What are the various advantages and disadvantages of each one? > > Thanks. > > Rog. This is a religious issue (similar to asking "what editor to use"). Both will do the job, and the differences are small. Differences: * Verilog syntax is easier to learn (similar to C) while VHDL is similar to the less-familiar Ada. * VHDL is much more strongly typed: Verilog has only some basic types and allows automatic conversion of vectors of mismatching widths. In VHDL you often need a conversion function to assign a value from one signal to another. It is a true PITA, but in a large design can save you weeks of searching for odd errors caused by automatic conversion of widths. In addition, in VHDL you can create new types of signals as needed (very common: create an enumerated type for all states in each FSM in the design or each control-signal group). Verilog will only allow you to assign names to numeric constants. * The other side of VHDL's strong typing is that usually VHDL simulations are slower. * VHDL is more complete as a programming language and has better built-in file I/O. IMO it makes it much better for writing test-benches. OTOH, Verilog has an API (called PLI) to "real" programming languages like C++ and even (god forbid) VB. I've never used this, so I can't report on how useful/powerful/easy-to-use it is. * My recommendation: if you buy any IP as source-code (either synthesizable or behavioral models of external sub-systems) use the language used for these IPs. Converting them is often impossible and, even if possible, a lot of trouble. If you don't buy IPs, decide by the tools you want/have to use: some are better and some are cheaper in one language or the other. It is also possible that your FPGA/ASIC vendor will have preferences for one or the other language (most FPGA vendors and tools are bilingual; some ASIC vendors prefer one language, typically Verilog). You may prefer to select your tools by language preference instead (I know - that was the original question). VHDL is slightly harder to learn, but all else being equal, I think it is the better long-term choice. If at all possibly, avoid situations in which you must use both languages in the same design - it is more than a double headache.Article: 51794
[good stuff snipped] >It sounds like a better way to improve C or Fortran might be to use an >fpga as a coprocessoer that implements common math routines or common >communication protocols and let the user treat that as fixed hardware. Most of the number crunching in scientific computing is floating point, so appropriate "common math routines" aren't that common. Communication is hard. It takes wires and packaging. You might be able to use FPGAs to help, but it won't be anything as simple as adding in a PCI card with an FPGA on it. >I'm still curious about one thing. Do HW people have to muck around with >anything after the verilog or vhdl is optimized? PCB layout. Packaging: wire lengths and cooling and power and connectors. System architecture level issues. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 51795
> I have some project files that I created with Xilinx Foundation Series 2.1i > Student Edition. The extension of the project file is .pdf. > Now I installed Xilinx ISE 4.2i Student Edition. They change the project > extension to .npl and I can't seem to open my old project file with this new > software. > Is there anyway that I can convert the old project file so I can open it > with the new 4.2i software? > Thanks! Hint: Complete the project in Foundation 2.1, or restart in ISE 4.2i... I remember reading a number of posts in this newsgroup of people having compatibility issues with projects from different software. adrianArticle: 51796
"Noddy" <g9731642@campus.ru.ac.za> wrote in message news:1043219080.653312@skink.ru.ac.za... > Hint: Complete the project in Foundation 2.1, or restart in ISE 4.2i... I > remember reading a number of posts in this newsgroup of people having > compatibility issues with projects from different software. > > adrian Arrgh, I already completed all the projects for Foundation 2.1i. It's from my old classes. They are schematic files for my FPGA board, not HDL files. But now I want to use the newer one while building my new projects. And I don't want to have two different versions of software in the same computer in order to read both new and old projects. It takes too much space.Article: 51797
Yup, its a problem with many tools. If you have a date stamp beyond the actual date they refuse working. Using the C tool "touch" is a convinient way to solve this problem. Thomas "Marcin E. Hamerla" wrote: > Nial Stewart napisal(a): > > >> Ok, I believe it but first I would like to know if I should cut down > >> windows and reinstall OS or there is simpler solution. > > > >I would completely un-install Flexlm then use a registry cleaner > >(I've used RegCleaner from http://www.vtoy.fi/jv16/shtml/software.shtml > >before) to completely remove all traces of Flexlm from the > >registry. Re-install Flexlm and see if it works. > > I got help from Altera support. Solution was simpler: I searched for > all the files with date newer than 2003-01-21 and changed their > dates. > > -- > Pozdrowienia, Marcin E. Hamerla > > "Płoń, płoń, płoń parlamencie, spali Cię ogień na historii zakręcie."Article: 51798
Thanks. >* VHDL is much more strongly typed: Verilog has only some basic types >and allows automatic conversion of vectors of mismatching widths. In >VHDL you often need a conversion function to assign a value from one >signal to another. It is a true PITA, but in a large design can save >you weeks of searching for odd errors caused by automatic conversion >of widths. In addition, in VHDL you can create new types of signals as >needed (very common: create an enumerated type for all states in each >FSM in the design or each control-signal group). Verilog will only >allow you to assign names to numeric constants. I consider the wires/vectors sort of "type" system to be a major fuckup. Note that's all you get with most schematic packages too. It seems really stupid and error prone to be stuffing things like control signals into the back end of a vector so you can avoid a major amount of clutter as a bus gets passed around. >* The other side of VHDL's strong typing is that usually VHDL >simulations are slower. Could you please say more? I think of strong typing as a compile time issue. The final circuit is going to be just wires and gates. Why does it take longer to simulate if they came from one language or another? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 51799
Hi Kyle, brief answer: no. They are not compatible and there is no tool to convert them. Have a look at a *.pdf and the *.npl in an Editor, have a look at the two different *.sch in an Editor and you'll see the differences. Schematic from Aldec Foundation => ISE: not possible (except redrawing all). Hint: go for either Active-HDL by Aldec (that can read the old stuff) or go for VHDL. My two Euro-Cent, Fritz
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