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"Bernhard Mäder" <nonuschk@gmx.net> wrote in message news:3ddbcd43$1@news.swissonline.ch... > > Just drive the gray encoded read/write pointers(addresses) via FlipFlops, > > sample them on the other side and reconvert them to binary to calculate > the > > difference between the read/write pointer. > > > > No RAM, simple FlipFlops are just right. > > > > Hmm, is there a possibility to pass (registered) signals to other clock > domains in Handel-C? I suggested the mpram version because I think mprams > are the only structures available that can be used to pass data between two > clock domains. > > > > > We do, and its not such a big issue. Usually you use them as black boxes, > > which are supplied by the FPGA/ASIC/whatever Vendor. Xilinx has some VHDL > > sources for asynchronous FIFOs. Have a look at the xapps. > > > > I have done that, but unfortunately they are all for HDLs and not > Handel-C.... > > The thing is, I know how the fifos should look like in hardware. What I > don't know is how to describe them in C. > > thx, > Bernhard > > I've been pondering this, and wondering what is a neat answer. When you say "asynchronous fifo" do you mean that data is put in to the fifo in one clock domain, and received in a different asynchronous clock domain? Does the delay matter between clock domains, i.e. does it matter if clock cycles are used to resynchronise the data? Is data transfer one way only? The reason I ask is that in HandelC it would make sense to use a channel to send the data from one domain to the other, as that would take care of synchronisation - and then use a synchronous FIFO in the second clock domain (implemented in a RAM). The source will then automatically block when the channel has not been read, so you will have to make sure the data transfer on the source side can cope with this. You will also incur a number of clock cycles delay in the channel, hence my question if the delay between the clock domains matters. Using a shared MPRAM is also a recommended way by Celoxica, but you need to make sure a) you have one in the technology you are using b) you can cope with overflow /underflow somehow as the pointers into the RAM are in the two different clock domains. To implement the other suggestions people have made (i.e. some pieces of wire going from one clock domain to the other) you would need to create two main() functions in two different projects, and then simulate with the netlist simulator to verify it (or even better build it!) regards Alan -- Alan Fitch [HDL Consultant] DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: alan.fitch@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com This e-mail and any attachments are confidential and Doulos Ltd. reserves all rights of privilege in respect thereof. It is intended for the use of the addressee only. If you are not the intended recipient please delete it from your system, any use, disclosure, or copying of this document is unauthorised. The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 49976
the problem that you have described was similar to the one I had encountered during a spartan 2 based desig that i had done few months ago. see when you configure the fpga directly thru jtag, the bitstream is saved into the fpga's configuration memeory(sram). but since configuration done will be asserted soon, before your verification begins your fpga synthesised hardware has already started functioning and changed the contents of the sram. this is sure to cause discrepancies in the verification process. verification will work 100% if you had configured an external ISP PROM(if you had one in your design). the issues arises only when u try to configure the fpga and allow it's hardware to start functioing immediately. this is how i convinced myself of the discrepancy. hope it helps and i guess that the verification failure will not stall your operation in any way. Nachiket Kapre. Design Engineer. Paxonet Communications. k_guichard@hotmail.com (Kyle Guichard) wrote in message news:<dc00661e.0211251638.1200650e@posting.google.com>... > Hi all, > > When I program my spartan 2 using the ISE software using JTAG, it > tells me that "programming succeeded." However, when I verify the > design, it comes up with thousands of discrepancies in the design > actually on the fpga. When I implement very simple logic like an AND > gate, it works sporadicaly and does not work at all after shutting > down the fpga. > > Any help or direction would be great. > > thanks! > kyleArticle: 49977
hi all. I'm battling with Microblaze at the moment. What I thought was a realitively simple image processing algorithm takes an age to complete. One of the problems is the ZBT memory controller that comes with Microblaze requires not 2, not 3 but 5 cycles to perform a read. I guess I have to except Microblaze can't pipeline reads, but I have other master devices on the OPB which could, especially as they will always be reading sequential addresses. So my question, has anyone used a zbt memory (hence the controller) in a microblaze system. The documentation gives precious little info. Can the controller reduce the read cycles using the sequential address signal provided by the OPB. In short, is there anyway to reduce the number of required read cycles. thanks tim QinetiQArticle: 49978
Seth, check out: Tarari www.tarari.com, or Celoxica's RC1000 http://www.celoxica.com/technical_library/datasheets/default.asp Noel Kolin Paul <kolin@cs.colostate.edu> wrote in message news:<3DE3F3CF.7090400@cs.colostate.edu>... > u can check www.alphadata.com > > David wrote: > > You can check www.dalanco.com > > > > David > > > > Seth wrote in message ... > > > >>I am looking for vendors of PCI FPGA boards for production, not just > >>prototyping. > >> > >>So far I know of Annapolis Microsystems which offers boards with > >>Virtex chips and RAM. > >> > >>Can anyone recommend any others? > > > > > >Article: 49979
Xilinx does this quite often. every new version comes with a pre-condition. i tried on my machine with NT and it does not work at all! it almost took a day for me to rectify....... "Neeraj Varma" <neeraj@cg-coreel.com> wrote in message news:<aqd4kj$8vu3f$1@ID-159439.news.dfncis.de>... > Hi - my AEs installed 5.1i on WinNT without problems. However, when they > tried installing service packs (sp-3 is available now), it gave hell lot of > installation problems. I would not recommend using WinNT from 5.1i onwards. > > --Neeraj > > > "Stephen Williams" <icarus-hates-spam@icarus.com> wrote in message > news:3DC94F41.5020000@icarus.com... > > > > > Rick Filipkiewicz wrote: > > > > > >> I read on this NG that from 5.x onwards Win-NT is no longer `supported' > > >> by Xilinx. Since I'm loathe to change O/S for no very good reason and > > >> AFAIC, Win-NT 4.0 SP6A is as close to bomb-proof as any 'doze O/S has > > >> ever got I'd like to at least try installing 5.1 under NT. > > > > > > Russell wrote: > > > > > > Win2k is as bomb-proof as anything, and does all the usb and plug/pray > > > stuff. > > > > > > > ISE 5.X and Win2000 are probably OK, but if they say "not NT" then > > they may have a good reason for saying so. There are sometimes drivers > > involved, so Rick is asking a perfectly reasonable question. Getting > > an install without destroying the O/S may involve turning some stuff > > off at install time. > > > > Foundation 4.2i (ISE 4) and Win2K can make a real mess if you are > > not careful. Rick is right to be cautious on this score as well. > > -- > > Steve Williams "The woods are lovely, dark and deep. > > steve at icarus.com But I have promises to keep, > > steve at picturel.com and lines to code before I sleep, > > http://www.picturel.com And lines to code before I sleep." > > > > abuse@xo.com > > uce@ftc.gov > >Article: 49980
although your reset is asynchronnous, you stmc clock is not evident from the way you have written the sequential next state process. first of all if sync stmc next state assignment process is always clocked and . next state generation process is combinatorial. so if ur reset is async you say //sequential next state process if (reset=active_high_value) then present_state <= RESET ; elsif(clk'event and clk=active_high_val) then present_state <= next_state //combi next state generation process if you want to use async reset here then you will have to add the "async reset" logic to each state of you machine which is really silly way of doing things, and after all since you cant avoid using reset in you next state assignment process you migth as well use it only there instead of both places.it will save you a lot of coding effort and make the code smaller and less prone to mistakes. this is cleaner way that will be syntheissable by all(well almost) synthesis tools. regards, Nachiket Kapre Design Engineer. Paxonet Communications Inc. Muzaffer Kal <kal@dspia.com> wrote in message news:<gucmtu0emn5tnj7d4ha88c2ug710u6o6tv@4ax.com>... > On 19 Nov 2002 21:37:29 -0800, muthu_nano@yahoo.co.in (Muthu) wrote: > > >Hi, > > > >In a state machine, since i want a RESET state (till the reset is > >released,it has to be in this state)i coded as below. > > > >//combinational portion to decide next state > > > >case(present_state) > >RESET: > >begin > > > >if(reset) > > begin > > next_state = state1; > > end > >else > > begin > > next_state = RESET; > > end > >end > >. > >. > >. > >endcase > > > >// Sequential logic > > > >always .... > >begin > > if(!rst) > > begin > > present_state <= RESET; > > end > >. > >. > >. > >end > > > > > >Is the inclusion of Asynchronous RESET signal in the combination > >portion is the correct way? > > > >Best regards, > >Muthu > > No; as this is an async reset, the flops will be reset till it is > released so no next state will be loaded during reset and you don't > need to check reset signal in the next state calculations. > > Muzaffer Kal > > http://www.dspia.com > ASIC/FPGA design/verification consulting specializing in DSP algorithm implementationsArticle: 49981
why dont you try synchroniser across the two domains since that will make your deisgn safer and independent of jitter which as ray mentioned is suscptibel to rpocess vaiations and other physical factors like temeperature.. Nachiket Kapre Design Engineer Paxonet Communications "louis" <n2684172@ms17.hinet.net> wrote in message news:<arcgqh$3og@netnews.hinet.net>... > There's a external clock input (20MHz) on my system, and I multiply > it to 2X (40MHz) by DLL as the working clock. > However, I have to exchange data in several > modules between these two clock domains. I don't know if it safe to sample data > on both positive edges of these two clocks? > Will the clock jitter cause the metastability? Or I have to generate data > on positive edge and retrieve data on negative edge instead? > The target chip is SpartanIIE. Any comment and suggestion will be very > appreciated. > > louisArticle: 49982
I've installed the WebPack 4.1 and it's all ok! Thankyou Giovanni "Bob" <nimby1_not_spmmm@earthlink.net> ha scritto nel messaggio news:65ME9.1851$yy.325651@newsread1.prod.itd.earthlink.net... > We had to download an older version of the Webpack programming tool. Their > website has these old versions available. >Article: 49983
Thats www.alpha-data.com , the hyphen being important ! Thanks for the reference, Bill "Kolin Paul" <kolin@cs.colostate.edu> wrote in message news:3DE3F3CF.7090400@cs.colostate.edu... > u can check www.alphadata.com > > David wrote: > > You can check www.dalanco.com > > > > David > > > > Seth wrote in message ... > > > >>I am looking for vendors of PCI FPGA boards for production, not just > >>prototyping. > >> > >>So far I know of Annapolis Microsystems which offers boards with > >>Virtex chips and RAM. > >> > >>Can anyone recommend any others? > > > > > > > >Article: 49984
Has anyone succeeded in manually creating a BMM file to allow the Data2BRAM tool to change memory contents of a BIT file? If so, what did their BMM file look like in relationship to their design heirachy? Thanks in advance, -- GaryArticle: 49985
Hi Ted, > I got the 20 MHz limit by using the standard AHDL: > accum[].d = accum[q] + add[] (all registered) > > Using the library lpm_addsub() incresed the speed to about 30MHz. I > really need to go at least up to 50MHz. I've been doing a quick test, but I'm afraid that about 30MHz is as high as you'll get in a -4 device; the critical path is the raw carry chain in the device. A quick try on a 10K10-3 got me at about 45MHz. Best regards, BenArticle: 49986
I have given pin constriants and global clock buffers are exactly in their places. One difference what i found w.r.t. 4.2i is the new tool is considering some of the nets as clock signals and giving some hold violations. My worry is when 4.2i can give good results why can't 5.1i? (for exactly the same source code) regards, nagarajArticle: 49987
"E. Backhus" <backhus@isms.hs-bremen.de> wrote in message news:1af13149.0211262320.5d1c6310@posting.google.com... > Hi, > > > I plan to use 33 ohm series [ source ] termination resistors for half > > of these 544 lines (since I intend to use half of them for sending and > > half of them for receiving data ; and apparently the receivers do not > > need termination) > > > > Any suggestions on what is done in such a situation wherein one needs > > to put in "so many termination resistors " and very limited space > > [BGA part] is available ? > > You should contact a high-end PCB manufacturer and ask for resistors > that can be integrated into the PCB tracks. These resistors are not > "long and thin copper wires", they are made from special resistor > material for PCBs. For 33 Ohms i expect those to consume not more > space than your copper tracks, but you have to produce an extra gerber > file that shows the geometry of these special tracks. On your PCB > layer The result will look like this for 2 parallel tracks: > > C = Copper track > R = Resistor Track > > CCCCCC > CCCCCCCCCCRRRRRRRRRRRRCCCCCCCC > CCCCCC > CCCCCCCCCCRRRRRRRRRRRRCCCCCCCCCC > > > Have a nice routing > Eilert > These 'Ohmega' buried resistors work. However, from our experience, they are expensive and result in a lower-yield circuit board. Also, not all pcb fab houses can build boards with this technology. I would recommend not using them unless the density of the board is very high, and there's just no other way to do it. For the hell of it, here's a link: www.ohmega.com BobArticle: 49988
Hi - On 26 Nov 2002 23:20:16 -0800, backhus@isms.hs-bremen.de (E. Backhus) wrote: >Hi, > >> I plan to use 33 ohm series [ source ] termination resistors for half >> of these 544 lines (since I intend to use half of them for sending and >> half of them for receiving data ; and apparently the receivers do not >> need termination) >> >> Any suggestions on what is done in such a situation wherein one needs >> to put in "so many termination resistors " and very limited space >> [BGA part] is available ? > >You should contact a high-end PCB manufacturer and ask for resistors >that can be integrated into the PCB tracks. These resistors are not >"long and thin copper wires", they are made from special resistor >material for PCBs. For 33 Ohms i expect those to consume not more >space than your copper tracks, but you have to produce an extra gerber >file that shows the geometry of these special tracks. On your PCB >layer The result will look like this for 2 parallel tracks: > >C = Copper track >R = Resistor Track > > CCCCCC > CCCCCCCCCCRRRRRRRRRRRRCCCCCCCC > CCCCCC > CCCCCCCCCCRRRRRRRRRRRRCCCCCCCCCC Before you do this, find out (a) what it will cost and (b) how many PCB fab houses support the process. I looked into this a couple of years ago, and unless things have changed, the answers are (a) a lot and (b) not many. Bob Perlman Cambrian Design WorksArticle: 49989
"Anand" <anand287@lycos.com> schrieb im Newsbeitrag news:a6908954.0211261743.1d96e642@posting.google.com... > I plan to use 33 ohm series [ source ] termination resistors for half > of these 544 lines (since I intend to use half of them for sending and > half of them for receiving data ; and apparently the receivers do not > need termination) > > Any suggestions on what is done in such a situation wherein one needs > to put in "so many termination resistors " and very limited space > [BGA part] is available ? Switch to Virtex-II, they provide internal termination capabilities. -- MfG FalkArticle: 49990
Hi Muthu, It sounds like you still need to add "external macro pins" to your macro. This is how you name the ports to be used in your instantiation. Check out answer record 10901 (particularly step 3) at: http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=10901 Think of it like adding ports to your lower level HDL so that you are able to instantiate it. I hope this helps. Best regards, Ryan Laity Xilinx Applications Muthu wrote: > Hi, > > Here i generated a Hard-macro using FPGA editor. But in the creation > itself i am getting the warnings below. > > //////////////////////////////////////// > save -w macro D:\\bei_bfr_smc_64_6.nmc > WARNING:FPGAEditor:172 - Placing and routing an unbound system macro > may given unexpected > > results. > Component "PWR_GND_0" assigned to be reference component. > WARNING:DesignRules:18 - Macrodefcheck: This macro has no external > pins defined. > //////////////////////////////////////// > > And i instantiated this module as a black box in the design and > synthesised.During Place and Rounte I am expecting that, the macro > will be expanded in the translation phase. but it is giving the below > errors. > > /////////////////////////////////////// > ERROR:NgdBuild:76 - File > "D:/bei_bfr_smc_64_6.nmc" cannot be merged > into block "bfr_ins1/bei_bfr_smc_ins1" > (TYPE="bei_bfr_smc_64_6") because one or more pins on the block, > including pin "sampled_out", were not found in the file. Please > make > sure that all pins on the instantiated component match pins in the > lower-level design block (irrespective of case). If there are > bussed pins on > this block, make sure that the upper-level and lower-level netlists > use the > same bus-naming convention. > /////////////////////////////////////// > > How should we view the file for checking hte singals.? is the way of > instantiating macros is correct? > > Thanks in advance. > > Best regards, > MuthuArticle: 49991
Falk Brunner wrote: > Switch to Virtex-II, they provide internal termination capabilities. > As Falk said, your problem disappears completely with Virtex-II, which is a better deal anyhow, considering several improved features, like better clock management and larger BlockRAMs, and (if I remember right) even a lower price. I am still on vacation, but back this coming Monday. Peter AlfkeArticle: 49992
On Wed, 27 Nov 2002 15:28:15 GMT, Bob Perlman <bobsrefusebin@hotmail.com> wrote:
>On 26 Nov 2002 23:20:16 -0800, backhus@isms.hs-bremen.de (E. Backhus)
>wrote:
>>[attribution lost]
>>> I plan to use 33 ohm series [ source ] termination resistors for half
>>> of these 544 lines [snip]
>>> Any suggestions on what is done in such a situation wherein one needs
>>> to put in "so many termination resistors " and very limited space
>>> [BGA part] is available ?
>>
>>You should contact a high-end PCB manufacturer and ask for resistors
>>that can be integrated into the PCB tracks. [snip]
>
>Before you do this, find out (a) what it will cost and (b) how many
>PCB fab houses support the process. I looked into this a couple of
>years ago, and unless things have changed, the answers are (a) a lot
>and (b) not many.
For not-quite this density, I have used Panasonic EXB2HV resistor
packs. 8 independent resistors, flow-through footprint, 0.5 mm pitch,
cheap, and in-stock at Digi-Key. The worst part is getting the
prototypes soldered down. It sounds like your needs would be met
by two interleaved banks of these, maybe one on each side of the
board?
- Larry
Article: 49993How fast can a smaller adder be implemented? You could simply break the 32 bit accumulator into pieces with carries registered between the stages. (forgive me if my AHDL syntax is wrong - it's been years) accum[32..24] = accum[32..24] + add[32..24] + c[2]; (c[2],accum[23..16]) = accum.q[23..16] + add[23..16] + c[1]; (c[1],accum[15..8]) = accum[15..8] + add[15..8] + c[0]; (c[0],accum[7..0]) = accum[7..0] + add[7..0]; If you had thousands of changes of the accumulator value and needed extreme precision in the phase value, you'd need to coordinate the staging of when each add section is updated so the propagating carries and the new add values setp through together. In most cases, this isn't a requirement at all - it all flows cleanly without special coding. "ted" <edaudio2000@yahoo.co.uk> wrote in message news:c54bf83f.0211270012.21e12052@posting.google.com... > > > > Either you are using a very old and slow device, or there is something > > wrong with your design. > > ... but to help you, we will need to know which device and which > > design entry method you are using. It would also be a help if you > > posted your code. > > > Very valid quesion to ask! > I forgot to mention the constrains. > > This "extra" circuit is to be retroffited onto a board > already containing an Altera 10K. The boards in stock already have > parts with a -4 speed rating. So that is my target. We could > re-populate the boards with faster devices, but at least I would like > to know that is the only viable option!! > > The other alternative is to re-lay the board, and add a new device. > Because the DDS is the only function needed, it would be too expensive > to use large FPGAs, > so the only cost-relevant option would be to use a CPLD. > > So the question should be re-phrased: Any hints on how to get the best > carry performance out of an Altera 10k (-4). > > I got the 20 MHz limit by using the standard AHDL: > accum[].d = accum[q] + add[] > (all registered) > > Using the library lpm_addsub() incresed the speed to about 30MHz. I > really > need to go at least up to 50MHz. > > I have also fiddled with the various global options optimise settings. > > Any hints? > > Thanks in advance! > > Also thanks to those who have already responded! > > Theo > > > PS I have also noticed the MAX-II simulator gives result nothing like > the ones I get on the oscilloscope.Article: 49994
Binary rate multipliers don't fit nearly as well into current FPGAs as do accumulator based approaches. DDS - direct digital synthesis - can provide something like the Fo = Fi * (N/4096) mentioned. By clocking a 12 bit accumulator at Fi, the MSbit toggles at Fo as long as N is 11 bits or fewer - a larger value looks like a negative phase increment. The approach can be scaled to any needed size with the upper limit of frequency Fo of Fi/2. The jitter you get here is at most 1 Fi period, peak to peak. The binary rate multiplier produces much higher jitter and is more difficult to code with today's HDLs. "Jim Granville" <jim.granville@designtools.co.nz> wrote in message news:3DE47276.41C9@designtools.co.nz... > > Skillwood wrote: > > > Hi all, > > Can somebody tell me how to generate a signal frequency based on a count > > input value. > > say I have a 12 bit i/p which can be used to give binary inputs. I want > > to generate an o/p signal frequency corresponding to each different > > i/p(2^12). > and > > How can i generate 2f,3f.. from the system clock f . > > You cannot generate arbitary multiples of a lower clock, without > something like a faster oscillator : be it VCO, DLL, etc. > So 2fi, 3fi..4095fi is not practical. > > However, I think what you are after is Fo = Fi * (N/4096), where > N is 0..4095. Fi can be in the 100's of MHz in modern silicon. > > For HW examples of this, look for Binary Rate Multipliers > CD4089 is one device number. There is some phase jitter on the > output. > > This same topology can make what we call a Picket Fence DAC. > > - jgArticle: 49995
John_H wrote:
>
> Binary rate multipliers don't fit nearly as well into current FPGAs as do
> accumulator based approaches.
<snip> .... and is more difficult to code with today's HDLs.
Both are valid design approaches, but the comments above I find
hard to follow :
This is the engine of a 10 bit Rate Multiplier (in CUPL ) :
fSUM.d = (fSet0 & RmC9 & !RmC8 & !RmC7 & !RmC6 & !RmC5 & !RmC4 & !RmC3 &
!RmC2 & !RmC1 & !RmC0 )
# (fSet1 & RmC8 & !RmC7 & !RmC6 & !RmC5 & !RmC4 & !RmC3 & !RmC2 &
!RmC1 & !RmC0)
# (fSet2 & RmC7 & !RmC6 & !RmC5 & !RmC4 & !RmC3 & !RmC2 & !RmC1 &
!RmC0)
# (fSet3 & RmC6 & !RmC5 & !RmC4 & !RmC3 & !RmC2 & !RmC1 & !RmC0 )
# (fSet4 & RmC5 & !RmC4 & !RmC3 & !RmC2 & !RmC1 & !RmC0 )
# (fSet5 & RmC4 & !RmC3 & !RmC2 & !RmC1 & !RmC0 )
# (fSet6 & RmC3 & !RmC2 & !RmC1 & !RmC0 )
# (fSet7 & RmC2 & !RmC1 & !RmC0 )
# (fSet8 & RmC1 & !RmC0 ) /* 256 pickets -> 25% freq, etc */
# (fSet9 & RmC0 ) /* 512 pickets -> 50% Freq */
;
Surely this does not challenge 'today's HDLs' ?
We use Rate Multipliers in CPLDs, because they need LESS resource than
Accumulators.
The OP did not say if he targeted FPGA or CPLD.
-jg
Article: 49996
"Anand" <anand287@lycos.com> wrote in message
news:a6908954.0211261743.1d96e642@posting.google.com...
> hi everybody,
>
> I hope this is the right audience for this question.
>
> I am designing a Printed Circuit Board which mainly consists of an
> FPGA [XCV2000E, xilinx virtex-E 2000 part,package : FG1156 ,fine pitch
> ball grid array] , "16" SCSI connectors [68 pin female]
> and oscillator,regulator and configuration PROM.
>
> Now, I am using 544 I/O's of this FPGA.
> As result, I have 136 I/O's from each side of the FPGA (four sides in
> all)
> and leaving the FPGA on various layers.
>
> Following the Xilinx Board Routability Guidelines I chose 5 mil trace
> width for these I/O's traces.
>
> I plan to use 33 ohm series [ source ] termination resistors for half
> of these 544 lines (since I intend to use half of them for sending and
> half of them for receiving data ; and apparently the receivers do not
> need termination)
>
> Any suggestions on what is done in such a situation wherein one needs
> to put in "so many termination resistors " and very limited space
> [BGA part] is available ?
>
> How much leeway do I have in choosing these termination resistors ?
> Is 33 ohm acceptable as a series termination resistor for a wide
> range of trace characteristic impedances ?
>
> Further, I believe I need to use 5 mil trace width as they leave the
> FPGA BGA because the number of traces is huge considering the space
> between succesive balls in this BGA [ball grid array package].
>
> I am not clear about the width of these traces as they move away from
> the FPGA.
>
> Is the trace width changed along the length of the trace ,normally ?
> Say, the traces are on an average of length , 4 inches long ?
>
> Please reply with your suggestions/comments...
> I'd really appreciate it.
>
> thanks very much
> regards
> Anand Kulkarni
A few comments...
The termination resistance should match the impedance of the trace. The
impedance of a 5 mil trace can vary depending on construction (microstrip
vs. stripline) and dielectric thickness and dielectric constant.
Technically, the line can be terminated at either the source (in series with
the trace) or the load(in parallel with the load). If you use a load
termination (most common), the thevenin voltage of the source may be
important. For example, ECL logic uses a termination supply of about 1 volt
below the positive rail (if I recall correctly). Thus if you do not have a
termination supply, you might need 2 resistors for each line. There are
networks available with the proper values for a thevinin termination. I do
not know, but I suspect that an ideal termination voltage for a cmos system
would be VCC/2. Given the above constraints, the resistor network makes a
lot of sense. Also, Peter's comment about the Virtex2 is a very good point.
Peter usually knows what he is talking about. I think that Xilinx has some
sort of app note on PCB layout that might be useful. The best resource on
PCB layout is
High-Speed Digital Design: A Handbook of Black Magic
by Howard Johnson
Good luck,
Theron Hicks
Article: 49997
Skillwood wrote:
>
> ok,
> if i have f and 4095f , Can I generate 2f,3f,4f,.....
If you mean 4096f, then yes.
This is a code snippet, of a 10 bit RateMultipler.
RmC9..RmC0 is a straight forward 10 bit Sync binary counter,
and fSet9..fSet0 is the Frequency set vector.
You get a binary weighted sum of the frequency choices, selected by the
bits of the fSet
fSUM.d = (fSet0 & RmC9 & !RmC8 & !RmC7 & !RmC6 & !RmC5 & !RmC4 & !RmC3 &
!RmC2 & !RmC1 & !RmC0 )
# (fSet1 & RmC8 & !RmC7 & !RmC6 & !RmC5 & !RmC4 & !RmC3 & !RmC2 &
!RmC1 & !RmC0)
# (fSet2 & RmC7 & !RmC6 & !RmC5 & !RmC4 & !RmC3 & !RmC2 & !RmC1 &
!RmC0)
# (fSet3 & RmC6 & !RmC5 & !RmC4 & !RmC3 & !RmC2 & !RmC1 & !RmC0 )
# (fSet4 & RmC5 & !RmC4 & !RmC3 & !RmC2 & !RmC1 & !RmC0 )
# (fSet5 & RmC4 & !RmC3 & !RmC2 & !RmC1 & !RmC0 )
# (fSet6 & RmC3 & !RmC2 & !RmC1 & !RmC0 )
# (fSet7 & RmC2 & !RmC1 & !RmC0 )
# (fSet8 & RmC1 & !RmC0 ) /* 256 pickets -> 25% freq */
# (fSet9 & RmC0 ) /* 512 pickets -> 50% Freq */
;
-jg
Article: 49998
If you have a 4095f master clock to work with, you can use a phase accumulator
to generate N/2^k * the master clock where N is 0 to 2^(k-1).
Skillwood wrote:
> ok,
> if i have f and 4095f , Can I generate 2f,3f,4f,.....
>
> "Jim Granville" <jim.granville@designtools.co.nz> wrote in message
> news:3DE47276.41C9@designtools.co.nz...
> > > Skillwood wrote:
> > > > Hi all,
> > > Can somebody tell me how to generate a signal frequency based on a
> count
> > > input value.
> > > say I have a 12 bit i/p which can be used to give binary inputs. I want
> > > to generate an o/p signal frequency corresponding to each different
> > > i/p(2^12).
> > and
> > > How can i generate 2f,3f.. from the system clock f .
> >
> > You cannot generate arbitary multiples of a lower clock, without
> > something like a faster oscillator : be it VCO, DLL, etc.
> > So 2fi, 3fi..4095fi is not practical.
> >
> > However, I think what you are after is Fo = Fi * (N/4096), where
> > N is 0..4095. Fi can be in the 100's of MHz in modern silicon.
> >
> > For HW examples of this, look for Binary Rate Multipliers
> > CD4089 is one device number. There is some phase jitter on the
> > output.
> >
> > This same topology can make what we call a Picket Fence DAC.
> >
> > - jg
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 49999
We tried this route a number of years ago and found the costs to be quite
high and the yield to be in the basement. Unless things have improved
greatly, and/or you have no other alternatives, I'd recommend against it.
Bob Perlman wrote:
> Hi -
>
> On 26 Nov 2002 23:20:16 -0800, backhus@isms.hs-bremen.de (E. Backhus)
> wrote:
>
> >Hi,
> >
> >> I plan to use 33 ohm series [ source ] termination resistors for half
> >> of these 544 lines (since I intend to use half of them for sending and
> >> half of them for receiving data ; and apparently the receivers do not
> >> need termination)
> >>
> >> Any suggestions on what is done in such a situation wherein one needs
> >> to put in "so many termination resistors " and very limited space
> >> [BGA part] is available ?
> >
> >You should contact a high-end PCB manufacturer and ask for resistors
> >that can be integrated into the PCB tracks. These resistors are not
> >"long and thin copper wires", they are made from special resistor
> >material for PCBs. For 33 Ohms i expect those to consume not more
> >space than your copper tracks, but you have to produce an extra gerber
> >file that shows the geometry of these special tracks. On your PCB
> >layer The result will look like this for 2 parallel tracks:
> >
> >C = Copper track
> >R = Resistor Track
> >
> > CCCCCC
> > CCCCCCCCCCRRRRRRRRRRRRCCCCCCCC
> > CCCCCC
> > CCCCCCCCCCRRRRRRRRRRRRCCCCCCCCCC
>
> Before you do this, find out (a) what it will cost and (b) how many
> PCB fab houses support the process. I looked into this a couple of
> years ago, and unless things have changed, the answers are (a) a lot
> and (b) not many.
>
> Bob Perlman
> Cambrian Design Works
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
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