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Hello, i have changed the Xilinx-webpackversion from Xilinx Webpack 4.2i to Xilinx Webpack5.1i SP3. My operation system is win2000 and i use a spartan2-board. I want to create mcs-File for using Impact. This program asks me for this file everytime. If i use "Generate PROM File" on Webpack 4.2i, then the mcs-File will be created automatic.(This menu starts promfmtr.exe) If i use webpack5.1i SP3, this file won't be created automatic. I can create the bit-file and i can upload and run it on board. But i need it for creating a cdf-file, which works correctly and does not cause a software error later. Have i to activate a new option? Or i have to create it manually? Thanks in advance with best regards StefanArticle: 52776
Hello, I would like to plug a ISA (PC104) peripheral on the PC-CARD controler of an Intel Xscale PXA250 Processor. Is it easily possible with a CPLD or other ? Do i need more component ? Thank you for your help; Timothée GROSArticle: 52777
Stefan, See steps below 1. When iMPACT started, select prepare configuration. Or from the Gui, go to Edit, launch wizard and select prepare configuration. 2. Select PROM file. The rest are self explainatory. Regards, Wei Stefan Kulke wrote: > Hello, > > i have changed the Xilinx-webpackversion from Xilinx Webpack 4.2i to > Xilinx Webpack5.1i SP3. My operation system is win2000 and i use a > spartan2-board. > I want to create mcs-File for using Impact. This program asks me for > this file everytime. > > If i use "Generate PROM File" on Webpack 4.2i, then the mcs-File will be > created automatic.(This menu starts promfmtr.exe) > If i use webpack5.1i SP3, this file won't be created automatic. > > I can create the bit-file and i can upload and run it on board. But i > need it for creating a cdf-file, which works correctly and does not > cause a software error later. > > Have i to activate a new option? Or i have to create it manually? > > Thanks in advance > > with best regards > > StefanArticle: 52778
David,
In my opinion, take a close look at the spartan2 or spartan2e. There is a
free microcontroller (Pico-Blaze) available. There is also a free UART
available. We are using both of them in a project. We found them to be quite
simple and reliable to use. This particular project uses the Spartan2E. The
only concern would be the start-up current. The Spartan2 series chips are
available in a leaded package which might be of advantage in a thermally varying
environment. The potential difference in temperature coeficient of expansion
would seem to be much less critical than with BGA packages. Would these
packages also handle high vibration better? Is your environment a high
vibration environment? One negative would be the high start-up current. If I
recall correctly this applies to any Virtex derivatives including the
Spartan2(E) families, Virtex2(E) families and Virtex(E) familes. I have used
the SpartanXL with good success in my last project. However, Xilinx does not
support it in any of the current revisions of software.
Good luck,
Theron Hicks
David Brown wrote:
> We are going to be using an fpga in a future product, and are trying to
> decide which family to use. The most likely candidates seem to be Xilinx
> Spartan or Altera Cyclone. The application will involve a error checking
> and correcting for a communications link, plus a few other bits of control
> logic. There is nothing too complex in it, nor do we need very high speed
> (we are talking 100 kHz max), but it is more than I would like to fit into a
> small microcontroller, which would be the alternative solution. We also
> need a microcontroller on the board for a few other functions, so it could
> be very interesting to look at soft cpus. Speed is not really an issue, but
> temperature is - we would like components rated as high a temperature as
> possible.
>
> The price of the chips themselves is not a major issue, since we would only
> be looking at a few systems, but the price of development kits (simple demo
> card, programming cabel, basic developement tools) is correspondingly more
> relevant - especially since we will probably need two sets.
>
> I have had some experiance using a cpld (Mach 4), and would prefer to work
> in VHDL, with Verilog as a second choice. If we go for an embedded cpu,
> then I am quite happy working with gcc and gdb ports, as long as I can get
> some basic debugging access to the processor (via jtag, or a serial port) to
> start/stop the processor, read and write memory, and (hopefully) at least
> one hardware breakpoint.
>
> We can expect good support from our distributers for either Xilinx or
> Altera, but I would value any opinions others here may have about which we
> should choose, or pointers to any web pages that could help us decide.
>
> David Brown
> Norway
Article: 52779In article <3E565BD3.B6208076@egr.msu.edu>, Theron Hicks <hicksthe@egr.msu.edu> wrote: > One negative would be the high start-up current. If I >recall correctly this applies to any Virtex derivatives including the >Spartan2(E) families, Virtex2(E) families and Virtex(E) familes. I have used >the SpartanXL with good success in my last project. However, Xilinx does not >support it in any of the current revisions of software. The power-on-surge/start up current issue is with Virtex I family parts only (Virtex, Virtex-E, Spartan II, Spartan IIe), no the Virtex 2 (Virtex 2, Virtex 2 Pro) family of parts. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 52780
Does anyone can suggest me any tricks or workarounds to get postlayout best case timings data, in order to perform postlayout simulation with xilinx fpgas?Article: 52781
"Jacky Renaux" <renaux.jacky@wanadoo.fr> wrote in message news:2003215-192937-894018@foorum.com... > > oes somebody can give me where I can found details > on end-around-carry function which is recommended > for modulo (2^n)-1 conversion ? > This is normally a property of ones-complement arithmetic, so any references to that should do. As far as FPGA implementations, it would have to come through general routing instead of fast carry logic on the architectures I know about. Just take the carry out from the MSB and use it as the carry in for the LSB. -- glenArticle: 52782
Hi Paul, Thanks for the response. I have looked into this further and it seems that you are right. Gate boosting is a common practice in chips where there is a large number of switchbox-style structures and/or tri-state buses. The way it is commonly done is by just putting a capacitor between the drain and gate of the device that you want to gate-boost, so in effect you have a local charge pump for every gate boosted transistor. That way when the pass-transistor is activated, due to that cap having to preserve potential difference between its plates the voltage at the gate is 'boosted' to a value higher than the supply rail on the ic. Xilinx indeed appears to have used this technique in the past, but, from what I was able to find out they do not do so any more. From what I gather the area overhead due to the gate-boosting capacitors is comparable to that incured by using standard (complementary) pass-gates, but the speed of the circuit is considerably higher due to the higher Vgs on the transistor at switching time. I am also not a circuits guy. I found this new piece of info pretty cool. Regards, Ljubisa "Paul Leventis \(at home\)" <paul.leventis@utoronto.ca> wrote in message news:<pui5a.28516$UXa.8171@news02.bloor.is.net.cable.rogers.com>... > I'm not much of a circuits guy, so I can't answer your questions on charge > pumps and the like -- the bottom line is that you somehow have to > generate/supply Vcc + delta for gate boosting, and I imagine that could be a > challenge. > > The downside to fully CMOS transmission gates is that they burn area. So it > becomes an area/delay trade-off of how you build your transmission > gates/multiplexors/demultiplexors in your FPGA routing fabric. The FPGA has > oodles of transistors dedicated to switching functions, and you can pack > them pretty tight if you don't need wells -- the moment you throw some PMOS > devices into the mix, you (a) need more area for the second transistor and > (b) burn area for well spacing, etc. > > Regards, > > Paul > > > "Ljubisa Bajic" <eternal_nan@yahoo.com> wrote in message > news:9b0afb2c.0302201503.3c186dbf@posting.google.com... > > Hi Paul, > > > > Have you ever seen this done (even outside of a commercial setting) ? > > I would be interested in seeing the circuit that implements this. Charge > > pumps are switched cap circuits, so you would need to have a clock in > order > > to implement a transmition gate ? > > Anyhow why would anyone do this rather than just use a transmition gate > > (with a n-ch and p-ch transistor), or, if they really dont want to use a > pass- > > gate, use a pull-up/bleeder transistor like the ones used in some dynamic > logic > > circuits ? > > As far as I know charge-pumps are generally only used in digital circuits > > in order to generate the high(-er than supply) voltage necessary for > > programming (E)PROM, or maybe level shifting (like for interfacing to a > > computer serial port if you dont have 12v supply on your board). > > > > Ljubisa Bajic, > > VLSI Design Engineer, > > Oak Technology, Teralogic Group > > > > "Paul Leventis \(at home\)" <paul.leventis@utoronto.ca> wrote in message > news:<GC45a.21129$b8v1.5651@news04.bloor.is.net.cable.rogers.com>... > > > If I understand your question, then it's when you overdrive the gate a > pass > > > transistor to make sure it *really* turns on. > > > > > > The big problem with pass-transistor logic is that you get a Vth drop > across > > > an nmos pass transistor when you drive through it. This degrades the > signal > > > passing through the pass gate, causing reduced performance. There are > also > > > power implications. However the voltage drop is relative to the value > > > applied to the gate. By driving the gate with a higher voltage than you > use > > > for the signal that is passing through the pass gate, you reduce the > > > magnitude of the degradation -- potential completely removing it, if you > can > > > tolereate voltages that high. > > > > > > The cons are that you need to generate this higher gate voltage (you now > > > have two different Vcc values) off chip or on chip via charge pumps. > And > > > you need to route an extra power network. And most importantly, the > amount > > > you can overdrive your gates by depends on the process technology you > are > > > using -- the stronger your overdrive, the more likely you will run into > > > reliability issues with the transistor. > > > > > > Do companies do this? I don't know and/or can't say :-) > > > > > > Regards, > > > > > > Paul > > > > > > "digari" <digari@dacafe.com> wrote in message > > > news:e0855517.0302190344.5bce1783@posting.google.com... > > > > What is gate boosting? what are the pros and cons of the technology? > > > > Does is it being used in any FPGA device?Article: 52783
On 19 Feb 2003 03:44:36 -0800, digari@dacafe.com (digari) wrote: >What is gate boosting? what are the pros and cons of the technology? >Does is it being used in any FPGA device? One of the best ways to answer these questions, especially on how FPGAs are implemented, is to do a search on the public records. For example: www.uspto.gov I used the following search string ABST/pump AND AN/xilinx 5,574,634 Regulator for pumped voltage generator FIELD OF THE INVENTION The invention relates to integrated circuits, and to power supplies for driving portions of an integrated circuit structure. BACKGROUND OF THE INVENTION There are a number of applications in integrated circuits where an on-chip voltage which exceeds the value supplied by an external power supply is useful. Two such applications, shown in FIGS. 1 and 2 respectively, are (1) controlling pass transistors in field programmable gate array structures, and (2) controlling isolation transistors in antifuse-programmable gate array structures. Philip Freidin FliptronicsArticle: 52784
Phil, Aw, you spoiled the fun! It is so entertaining to listen to folks speculate how FPGAs are designed. A bit like listening to (....here is where I might get in trouble) Mechanical Engineers explain how to design a power supply. Austin Philip Freidin wrote: > On 19 Feb 2003 03:44:36 -0800, digari@dacafe.com (digari) wrote: > >What is gate boosting? what are the pros and cons of the technology? > >Does is it being used in any FPGA device? > > One of the best ways to answer these questions, especially > on how FPGAs are implemented, is to do a search on the > public records. > > For example: > > www.uspto.gov > > I used the following search string > > ABST/pump AND AN/xilinx > > > > 5,574,634 Regulator for pumped voltage generator > > FIELD OF THE INVENTION > > The invention relates to integrated circuits, and to power supplies for > driving portions of an integrated circuit structure. > > BACKGROUND OF THE INVENTION > > There are a number of applications in integrated circuits where > an on-chip voltage which exceeds the value supplied by an external > power supply is useful. Two such applications, > shown in FIGS. 1 and 2 respectively, are > > (1) controlling pass transistors in field programmable gate > array structures, and > > (2) controlling isolation transistors in antifuse-programmable > gate array structures. > > Philip Freidin > FliptronicsArticle: 52785
Before people draw too many conclusions: What companies patent and what they implement is not always the same thing. We use structures that are not patented, and we sometimes get something patented that we (for various reasons) never happen to implement. But I agree with Philip that patents can be a fascinating resource for high-level enlightenment. :-) Peter Alfke ============== Philip Freidin wrote: > > On 19 Feb 2003 03:44:36 -0800, digari@dacafe.com (digari) wrote: > >What is gate boosting? what are the pros and cons of the technology? > >Does is it being used in any FPGA device? > > One of the best ways to answer these questions, especially > on how FPGAs are implemented, is to do a search on the > public records. > > For example: > > www.uspto.gov > > I used the following search string > > ABST/pump AND AN/xilinx > > > > 5,574,634 Regulator for pumped voltage generator > > FIELD OF THE INVENTION > > The invention relates to integrated circuits, and to power supplies for > driving portions of an integrated circuit structure. > > BACKGROUND OF THE INVENTION > > There are a number of applications in integrated circuits where > an on-chip voltage which exceeds the value supplied by an external > power supply is useful. Two such applications, > shown in FIGS. 1 and 2 respectively, are > > (1) controlling pass transistors in field programmable gate > array structures, and > > (2) controlling isolation transistors in antifuse-programmable > gate array structures. > > Philip Freidin > FliptronicsArticle: 52786
In order for that IIR filter to maintain an oscillation, the placement of the poles has to be exact, and the
truncation of the feedback can't adversely affect the feedback term. It can be very difficult in a digital system to
maintain that balance thanks to truncation errors. Typically, if you use this method, you also need to provide an
error correction to keep the oscillation within bounds over the long term. It is possible that the oscillation is
either dying out, or going into saturation before you get a measurement of it. This may not show up in a relatively
short simulation.
Akshay wrote:
> Bassman59a@yahoo.com (Andy Peters) wrote in message news:<9a2c3a75.0302191641.7a06b3ef@posting.google.com>...
> > akshaymishra@rediffmail.com (Akshay) wrote in message news:<937606cb.0302170535.2347978a@posting.google.com>...
> >
> > 1) Does the synthesis tool give you any errors or warnings?
> >
> > 2) The multiplier may be eating up a lot of area, and you may not be
> > meeting timing. What's your clock speed? Have you set any timing
> > constraints? Are you meeting the constraints?
> >
> > -ap
>
> If I simplify as to what is desired:
>
> output<= coef1*y(1) - coef2*y(2);
> y(2)<=y(1);
> y(1)<=output;
>
> in other words an IIR Filter.
>
> giving the above sequence in a single process, i don't get anything.
> the synthesizer gives no warnings and says all constraints were met.
> the clock period was kept at 30ns.
>
> giving the code in two separate processes with the first process
> dependent upon clock and the second upon output also fails.
> the initializations are proper and i have got the vhdl simulation
> working fine.
>
> thanx,
> akshay.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 52787I've done this sort of thing for a long time to make parameterizable i/o ports on modules: module(a); parameter WIDTH=8; input[WIDTH-1:0] a; Now I'm transitioning to Verilog-2001, with ANSI-style declarations, like this: module(input [7:0] a); But how do I use a parameter with this style of declaration to make the width of 'a' parameterizable? I don't think I can insert a parameter before the module declaration. -KevinArticle: 52788
Hi, Does Xilinx offer a free 'Lpm style' function generator? In the ISE web edition, I can't seem to find anything comparable to what Altera offers for free. Thanks DavidArticle: 52789
I see some new spartan family on my latest Synplicity tools. I hear that its on 90nm IBM. Why would anyone try and build a low cost FPGA family on an aggressive new process technology? They can't make 0.13um VII pro, what hope do they have in building 90nm any time soon.Article: 52790
I read somewhere that in the absence of other information, Xpower assumes a data toggle rate of 12%. Since this does not correspond at all to my cases, I'm wondering if there is an easy way to tell it what the real cases are that does not involve generating huge .vcd files for different cases. For example, I would like it to estimate power for two cases: 1: inputs datain* change on every clock cycle, which will cause pretty much every node to change too. 2: inputs datain* change once every 500 clock cycles, leaving the device quiescent almost all the time. Is there some simple command I can give it to get more accurate data out of Xpower?Article: 52791
Time to OUT another TROLL :-) On 21 Feb 2003 16:33:13 -0800, jsmithconsultant@hotmail.com (jsmith) wrote: >I see some new spartan family on my latest Synplicity tools. I hear >that its on 90nm IBM. Why would anyone try and build a low cost FPGA >family on an aggressive new process technology? They can't make 0.13um >VII pro, what hope do they have in building 90nm any time soon. What a pointless posting. So "jsmithconsultant@hotmail.com" has never posted to this news group before. This was posted via google-groups to hide identity, but google reports the origin IP address. Here is the header of the posting (you can look it up for yourself) >>> Path: newssvr05.news.prodigy.com!newsmst01.news.prodigy.com!prodigy.com! >>> nntp.flash.net!iad-peer.news.verio.net!news.verio.net! >>> news.maxwell.syr.edu!newsfeed.stanford.edu! >>> postnews1.google.com!not-for-mail >>> From: jsmithconsultant@hotmail.com (jsmith) >>> Newsgroups: comp.arch.fpga >>> Subject: spartan III what is it? >>> Date: 21 Feb 2003 16:33:13 -0800 >>> Organization: http://groups.google.com/ >>> Lines: 4 >>> Message-ID: <f8039eeb.0302211633.7fdcb50c@posting.google.com> >>> NNTP-Posting-Host: 66.35.226.228 >>> Content-Type: text/plain; charset=ISO-8859-1 >>> Content-Transfer-Encoding: 8bit >>> X-Trace: posting.google.com 1045873993 6705 127.0.0.1 (22 Feb 2003 00:33:13 GMT) >>> X-Complaints-To: groups-abuse@google.com >>> NNTP-Posting-Date: 22 Feb 2003 00:33:13 GMT >>> Xref: newsmst01.news.prodigy.com comp.arch.fpga:54372 See that "NNTP-Posting-Host: 66.35.226.228" line, well that tells you who sent the posting via google. Here's what NSLOOKUP has to say about that IP address :-) === >nslookup 66.35.226.228 === Server: dns1.snfcca.sbcglobal.net === Address: 206.13.28.12 === === Name: ip66-35-226-228.altera.com === Address: 66.35.226.228 The 206.13.28.12 is the DNS server I use, but it could have been any DNS. Just trying to keep things clean here. To the more respectable Altera people who post here, I believe you make a valuable contribution. Maybe you should educate others about common courtesy and netiquette. Philip Freidin (and just to make it clean: Real Consultant, Ex Xilinx employee (exit 1995) Keeper and maintainer of the www.fpga-faq.com ) =================== Philip Freidin philip@fliptronics.com Host for WWW.FPGA-FAQ.COMArticle: 52792
Kevin, Verilog 2001 has ANSI-styleparam definition also, like this... module xyz # (parameter WIDTH=8, other param decls) (input [WIDTH-1:0]); endmodule Thanks , Abhijit "Kevin Neilson" <kevin_neilson@removethistextattbi.com> wrote in message news:<iiy5a.193221$tq4.3488@sccrnsc01>... > I've done this sort of thing for a long time to make parameterizable i/o > ports on modules: > > module(a); > parameter WIDTH=8; > input[WIDTH-1:0] a; > > Now I'm transitioning to Verilog-2001, with ANSI-style declarations, like > this: > > module(input [7:0] a); > > But how do I use a parameter with this style of declaration to make the > width of 'a' parameterizable? I don't think I can insert a parameter before > the module declaration. > > -KevinArticle: 52793
Philip, What's the problem? SpartanIII is a real thing. Also, I believe that the geometry he's cited is what it really is. ??? Bob "Philip Freidin" <philip@fliptronics.com> wrote in message news:1cmd5vobjuqsaiis1gmrdh4lm3pu7dfqo5@4ax.com... > > Time to OUT another TROLL :-) > > On 21 Feb 2003 16:33:13 -0800, jsmithconsultant@hotmail.com (jsmith) wrote: > >I see some new spartan family on my latest Synplicity tools. I hear > >that its on 90nm IBM. Why would anyone try and build a low cost FPGA > >family on an aggressive new process technology? They can't make 0.13um > >VII pro, what hope do they have in building 90nm any time soon. > > What a pointless posting. > > So "jsmithconsultant@hotmail.com" has never posted to this news group > before. > > This was posted via google-groups to hide identity, but google > reports the origin IP address. Here is the header of the posting > (you can look it up for yourself) > > >>> Path: newssvr05.news.prodigy.com!newsmst01.news.prodigy.com!prodigy.com! > >>> nntp.flash.net!iad-peer.news.verio.net!news.verio.net! > >>> news.maxwell.syr.edu!newsfeed.stanford.edu! > >>> postnews1.google.com!not-for-mail > >>> From: jsmithconsultant@hotmail.com (jsmith) > >>> Newsgroups: comp.arch.fpga > >>> Subject: spartan III what is it? > >>> Date: 21 Feb 2003 16:33:13 -0800 > >>> Organization: http://groups.google.com/ > >>> Lines: 4 > >>> Message-ID: <f8039eeb.0302211633.7fdcb50c@posting.google.com> > >>> NNTP-Posting-Host: 66.35.226.228 > >>> Content-Type: text/plain; charset=ISO-8859-1 > >>> Content-Transfer-Encoding: 8bit > >>> X-Trace: posting.google.com 1045873993 6705 127.0.0.1 (22 Feb 2003 00:33:13 GMT) > >>> X-Complaints-To: groups-abuse@google.com > >>> NNTP-Posting-Date: 22 Feb 2003 00:33:13 GMT > >>> Xref: newsmst01.news.prodigy.com comp.arch.fpga:54372 > > See that "NNTP-Posting-Host: 66.35.226.228" line, well that tells > you who sent the posting via google. > > Here's what NSLOOKUP has to say about that IP address :-) > > === >nslookup 66.35.226.228 > === Server: dns1.snfcca.sbcglobal.net > === Address: 206.13.28.12 > === > === Name: ip66-35-226-228.altera.com > === Address: 66.35.226.228 > > The 206.13.28.12 is the DNS server I use, but it could have > been any DNS. > > Just trying to keep things clean here. > > To the more respectable Altera people who post here, I > believe you make a valuable contribution. Maybe you should > educate others about common courtesy and netiquette. > > > > Philip Freidin > (and just to make it clean: > Real Consultant, > Ex Xilinx employee (exit 1995) > Keeper and maintainer of the www.fpga-faq.com > ) > > > =================== > Philip Freidin > philip@fliptronics.com > Host for WWW.FPGA-FAQ.COM >Article: 52794
Does anyone know of a FPGA design tool, that takes timing diagrams as an input, and produces VHDL (or something else) as an output? KrestenArticle: 52795
Bob wrote: > Philip, > > What's the problem? I think he's absolutely right. No need to start FUDding in this newsgroup. > SpartanIII is a real thing. Also, I believe that the > geometry he's cited is what it really is. Do you mean it's (un)officially announced then? On the Xilinx website I can't find anything more advanced than the Spartan IIE. Best regards, BenArticle: 52796
While such an approach could be used for stateless logic,
eg a few AND, OR, NOT gates, logic with internal states, such as
flipflops, counters cannot be described in a finite timing diagram
from a certain level up. { 'Finite' not in math sense math }
Rene
Kresten Nørgaard wrote:
> Does anyone know of a FPGA design tool, that takes timing diagrams as an
> input, and produces VHDL (or something else) as an output?
Article: 52797Ben Twijnstra <bentwijnstra@spam.me.not.hotmail.com> wrote: : Bob wrote: :> Philip, :> :> What's the problem? : I think he's absolutely right. No need to start FUDding in this newsgroup. :> SpartanIII is a real thing. Also, I believe that the :> geometry he's cited is what it really is. : Do you mean it's (un)officially announced then? On the Xilinx website I : can't find anything more advanced than the Spartan IIE. At least the Xilinx ISE/Webpack tools install a Spartan 3 directory, although almost empty at the moment ... Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 52798
> You mention Spartan and Cyyclone. These are the low-cost FPGA families from the > two vendors ( Is Cyclone really available?). Yes, I'm playing around with a board with Cyclone EP1C6 :-) MartinArticle: 52799
In article <b37qbq$939$1@news.tu-darmstadt.de>, Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> wrote: >At least the Xilinx ISE/Webpack tools install a Spartan 3 directory, although >almost empty at the moment ... Probably simply planning for the future, when (most likely), a Spartan 3 is a Virtex 2 in low cost form. And troll (initial questioner) forgot the observation that new processes, at least once the shakedown is complete and the yeild gets decent, end up being cheaper per transister than old processes. -- Nicholas C. Weaver nweaver@cs.berkeley.edu
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