Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Hi, I'm trying to set up some hardware to demonstrate some HDL with. I have the Cypress boards, but all they are is a chip and a JTAG port. Have any of you built an add-on card for these? Or anything similar that I could "borrow" the design of? Thanks, Gary gwhelbig-at-yahoo.comArticle: 51876
Just for the record, if you need a Byteblaster, check out www.logicblock.com . Their service is very prompt and good.Article: 51877
"Larry Doolittle" <ldoolitt@recycle.lbl.gov> wrote > >Why not: > > > >module foo( > > input clk, > > input reset, > > input [31:0] bar, > > output bletch); > > Why indeed? This would be my number one request for the > language standards body. As Muzaffer already pointed out, Verilog-2001 supports this "ANSI-style" port declaration, and many tools already support it. > The C language made this transition > what, 15 years ago? Yup. Sadly, not all the C programmers caught up yet :-) > And of course, VHDL is just as deficient > in this respect. It is? Perhaps you could exemplify. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 51878
Hello, i have got some problems with "configure Device (IMPACT)" (_impact.exe). The system is WinNT2000 and the tool is "ISE Webpack version 5.1". If i log in as normal user and i run a project on a spartan2 Board, then the cable connection will fail between board and pc (lpt1). Because cable device driver is not installed. I've got reading and writing access to the program directory and subdirectories from ISE. If an Adminstrator use this tool, then the connection will successfully establish between board and pc (lpt1). I don't know, which directories are necessary too. Thanks in advance with best regards Stefan KulkeArticle: 51879
Hi all, I have unit LFSR35 (this is LFSR on 35 taps and based on 2 SRL16 components). I need 30 such units for generation 30bits random numbers. But problem exist in SRL16 initialization. I want use string generic for passing attributes values to SRLs, but it seems that XST synthesizer accept only default string generic values.( I checked SRLs initialization content in FPGA editor). Any suggestions ? Best regards, Vladislav Vasilenko. Here part of code for explanation: srl35.vhd ------------------------------- entity SRL35 is Generic ( GENERIC_INIT1 : string:="FFFF"; GENERIC_INIT1 : string:="FFFF" ) port ( .. ) .... architecture rtl of SRL35 is attribute INIT: string; attribute INIT of SRL1: label is GENERIC_INIT1; attribute INIT of SRL2: label is GENERIC_INIT2; ...Article: 51880
In article <b0qjos$s2dd0$2@ID-159027.news.dfncis.de>, geeko <jibin@ushustech.com> wrote: >Hi all > > Anbody familier with the implementation of AES(Rijindal) --- CTR with CBC >MAC in FPGA ( a C implementation can be found at >http://fp.gladman.plus.com/cryptography_technology/ccm/index.htm ) >I have certain quries about the implementation of a block cipher >How the implemetation can be tested ? (a sample test setup) Best way is to create a monte-carlo test rig (take the output, encrypt again, use output to rekey/reencrypt), compare with the software version. If you have any little problem, it will show up. >How the perfomance ie throughput,latency etc can be measured? CBC-MAC will be inherantly sequential, so for a single stream of execution, you will be limited by the latency required to encrypt each block before starting the next one. However, you probably should use XCBC MAC instead of CBC-MAC, its a slight tweak but an improvement http://csrc.nist.gov/CryptoToolkit/modes/proposedmodes/xcbc-mac/xcbc-mac-spec.pdf Also, if you are going to use a MAC which is sequential, why use CTR mode? CTR mode is nice for parallelism, but is easy to screw up, and screw up BADLY, in practice. Latency can be measred by taking your clock rate (from static timing) * number of cycles to encrypt a single block. Due to your MAC choice, your throughput will be limited by single block latency. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 51881
Apply the Service Pack 2 or 3 to your WebPACK. It will solve your problem. Jan "Stefan Kulke" <kulke@informatik.tu-cottbus.de> wrote in message news:b0r6nj$6l8$1@Maust.bbone.tu-cottbus.de... > Hello, > > i have got some problems with "configure Device (IMPACT)" (_impact.exe). > The system is WinNT2000 and the tool is "ISE Webpack version 5.1". > > If i log in as normal user and i run a project on a spartan2 Board, > then the cable connection will fail between board and pc (lpt1). > > Because cable device driver is not installed. > I've got reading and writing access to the program directory and > subdirectories > from ISE. > > If an Adminstrator use this tool, then the connection > will successfully establish between board and pc (lpt1). > > I don't know, which directories are necessary too. > > Thanks in advance > > > > with best regards > > Stefan Kulke >Article: 51882
John_H wrote: > My apologies. "I infer them just fine." > As I'm sure I stated, it's just when you go to different clocks or advanced > features that the primitves are required. Otherwise, Synplify has done > great with my register memory elements (e.g., reg [7:0] byte_array > [511:0];). If you want distribute CLB SelectRAM, the read value can be used > asynchronously. If you use BlockRAM, the output must be synchronous. > Inference is fine. > To amplify a little: The problem with inferring a full dual-port with independent clocks is that, in Verilog terms, it needs an HDL template with a `reg' assigned to from 2 different synchronous `always' blocks. Unfortunately this is forbidden for synthesisable code - synth tools will error out if this is detected.Article: 51883
I'm doing a design for a 9536, it's basically a frequency divider with over-frequency detect. I've produced the design on ORCAD, exported it as edif, and built the chip with the Xilinx facilities. I'm used to doing similar stuff on the Altera s/w which gives me a sort of "edit the input waveforms and we'll simulate it and show you the output waveforms" simulator ( I prefer test vectors, but beggars can't be choosers ) I'm having real trouble understanding how to do the same with the Xilinx s/w. The help files all talk about simulation for VHDL, and something else. But they don't say how one starts with an idiot-level edif import. I asked the support email, and got a load of stuff back which I suppose I will eventually decode, but they have a language all of their own. So can anyone explain to me where to start, pretty please? David Collier Dexdyne Ltd see www.Dexdyne.comArticle: 51884
In article <b0qjos$s2dd0$2@ID-159027.news.dfncis.de>, geeko <jibin@ushustech.com> wrote: >Hi all > > Anbody familier with the implementation of AES(Rijindal) --- CTR with CBC >MAC in FPGA ( a C implementation can be found at >http://fp.gladman.plus.com/cryptography_technology/ccm/index.htm ) >I have certain quries about the implementation of a block cipher >How the implemetation can be tested ? (a sample test setup) >How the perfomance ie throughput,latency etc can be measured? For initial development and debug, refer to FIPS PUB 197, which gives step-by-step examples for both key expansion and the main algorithm. For system testing, download the known-answer and Monte-Carlo tests from the NIST web site. These tests can be modified to test the algorithm. The MCT runs 4 million operations per key size, so this test is best run in an FPGA emulation. You should not need to MEASURE performance and latency - these are qualities of the algorithm you implement and should be known once the implementation is complete.Article: 51885
Hi Guys Do any body know whether Xilinx Logicores can be used in Handel-C designs? As far as I know, free tool from Xilinx, "Code Generator", can create VHDL codes from ligocores. Is it true? Advance thanx for your kind reply. IMADArticle: 51886
Richard <gospod88@hotmail.com> wrote: > gospod88@hotmail.com (Richard) wrote in message news:<f7779f31.0301210415.57fe1c85@posting.google.com>... >> Dennis McCrohan <mccrohan@xilinx.com> wrote in message news:<3E2C70A3.929A348D@xilinx.com>... >> Not an option I'm afraid. I'm using v4.2. > > Duh. The option *is* in v4.2. You can get the .twx XML timing report from TRCE using the "-xml filename" switch. It should be easier to parse that than the text timing report (although I've never attempted it). Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 51887
Larry Doolittle <ldoolitt@recycle.lbl.gov> wrote:
> On 23 Jan 2003 14:19:34 -0800, Andy Peters <Bassman59a@yahoo.com> wrote:
>>module foo(
>> input clk,
>> input reset,
>> input [31:0] bar,
>> output bletch);
>
> Why indeed? This would be my number one request for the
> language standards body. The C language made this transition
> what, 15 years ago? And of course, VHDL is just as deficient
> in this respect.
Oh? Doesn't this legal VHDL snippet do exactly the same?
entity foo is
port (
clk : in std_logic;
reset : in std_logic;
bar : in std_logic_vector(15 downto 0);
bletch : out std_logic
);
end entity foo;
It has the other advantage of having more specific type information.
What was your bar - a std_logic_vector, an array of integers or what?
Hamish
--
Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>
Article: 51888Thank you! Now it works. with best regards StefanArticle: 51889
"Austin Franklin" <austin@da98rkroom.com> wrote in message news:v31ialjlc52sa4@corp.supernews.com... snip > > Oh, and the fact that so many books are written on HDL's to make you an > > 'expert' - doesn't that say that they are darn hard to use correctly and > > efficiently ?-) > > Agreed, but you can learn just enough to think you know what you are > doing...which for some makes them dangerous ;-) > > Regards, > > Austin > Which books would you recommend for a HDL newby ( I'm a C programmer, who also does hardware) Thanks PatArticle: 51890
f5 <f5inet@ya.com> wrote in message news:<b0put0$qud$1@news.ya.com>... > Michael wrote: > > hi guys, > > > > i am a student in hamburg and for my final thesis i want to experiment with > > a x86 compatible processor loaded into a fpga. > > > > can anybody tell me, if there is any free x86 compatible processor core? if > > yes, where can i get it? > > > > thank you > > > > micha > > > > > www.opencores.org is a good starting point, i think... Doing an x86 compatible would be a huge undertaking more in the order of hundreds man yrs of effort if the design was completed to a competetive VLSI level. The FPGA would be easier to the extent you won't have the ASIC issues, but the performance will be dreadfull. There is the option of designing in HDL & let the simulation stand as proof. A clean risc is more practical and there are a lot of FPGA hosted cores, see Jan Gray http://www.fpgacpu.org/ site, opencores etc. There was the Freedom cpu project as well. I believe there may have been some commercial IP for 6502/8080/z80/V80 at one time. If you insist on x86, maybe go back to the origins of the design 8086/8080 when it 1st became interesting. Alternatively look at writing a simple emulator for the instruction set, you will pretty soon see how much deep water you can get yourself into. Once you have an understanding of how to emulate x86 upto say 486 level, turning that to hw will still be intimidating. You might run your emulator on MicroBlaze, then you would have satisfied that condition. If someone absolutely had to run x86 on FPGA, I would look for some type of translator from x86 to xxx. I assume you are armed with the Hennesy & Patterson book and know the DLX design.Article: 51891
On 24 Jan 2003 14:02:13 GMT, hamish@cloud.net.au <hamish@cloud.net.au> wrote:
>>>[ Verilog-2001 allows: ]
>>>module foo(
>>> input clk,
>>> input reset,
>>> input [31:0] bar,
>>> output bletch);
>
>Oh? Doesn't this legal VHDL snippet do exactly the same?
>
>entity foo is
> port (
> clk : in std_logic;
> reset : in std_logic;
> bar : in std_logic_vector(15 downto 0);
> bletch : out std_logic
> );
>end entity foo;
VHDL's duplication of information is different.
In Verilog-pre-2001, the declaration of a port in
a single module is split into two or three (argument
list, input/output, register/wire).
In VHDL, you declare the ports twice - once in the
defining module, and once in the instantiating module.
Sure, they should match, you can cut-and-paste (all
but the component/entity keyword), and the compiler
will catch mismatches, but it's still duplication
and IHMO a distraction. When you change your mind
about a port, you have to change it in three places:
the defining module, the instantiating module's component
definition, and the instantiation itself. I'd like to
use a preprocessor to avoid this duplication (like
.h files in C), but that doesn't seem to be encouraged
in the style guides and language standardization.
There is no VHDL preprocessor that is halfway part
of the language, like there is in Verilog or C.
I'd love to be shown wrong again. If y'all teach
me enough cool features of VHDL, and some Free
(as in freedom) Software shows up that implements
it (as well as Icarus Verilog implements Verilog),
I might even start using it again.
- Larry
Article: 51892
hamish@cloud.net.au wrote:
> Larry Doolittle <ldoolitt@recycle.lbl.gov> wrote:
>
>>On 23 Jan 2003 14:19:34 -0800, Andy Peters <Bassman59a@yahoo.com> wrote:
>>
>>>module foo(
>>> input clk,
>>> input reset,
>>> input [31:0] bar,
>>> output bletch);
>>
>>Why indeed? This would be my number one request for the
>>language standards body. The C language made this transition
>>what, 15 years ago? And of course, VHDL is just as deficient
>>in this respect.
>
>
> Oh? Doesn't this legal VHDL snippet do exactly the same?
>
> entity foo is
> port (
> clk : in std_logic;
> reset : in std_logic;
> bar : in std_logic_vector(15 downto 0);
> bletch : out std_logic
> );
> end entity foo;
>
> It has the other advantage of having more specific type information.
> What was your bar - a std_logic_vector, an array of integers or what?
>
> Hamish
yes, and so does this one:
entity foo is
port (
clk,reset : in std_logic;
bar : in std_logic_vector(15 downto 0);
bletch : out std_logic);
end entity foo;
Article: 51893In article <qHaY9.10116$W3.1095061@news20.bellglobal.com>, David Jones <dej@inode.org> wrote: >> Anbody familier with the implementation of AES(Rijindal) --- CTR with CBC >>MAC in FPGA ( a C implementation can be found at >>http://fp.gladman.plus.com/cryptography_technology/ccm/index.htm ) >>I have certain quries about the implementation of a block cipher >>How the implemetation can be tested ? (a sample test setup) >>How the perfomance ie throughput,latency etc can be measured? > >For initial development and debug, refer to FIPS PUB 197, which >gives step-by-step examples for both key expansion and the main algorithm. > >For system testing, download the known-answer and Monte-Carlo tests >from the NIST web site. These tests can be modified to test the algorithm. >The MCT runs 4 million operations per key size, so this test is best run >in an FPGA emulation. You can also modify the MCT software to come up with a slight variant, if say changing the key with EVERY encryption makes your life easier. But that strategy is very good even for simulation (do a few hundred steps). The structure of the algorithms are such that, for functional testing, if you change the key and data on every encryption, based on the last encrption, if there is a bug, it will be found VERY quickly. Also, the NIST FIPS has a great example of encrypting a single block with a single key with all the steps. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 51894
On Fri, 24 Jan 2003 16:24:57 +0000 (UTC), ldoolitt@recycle.lbl.gov (Larry Doolittle) wrote: >On 24 Jan 2003 14:02:13 GMT, hamish@cloud.net.au <hamish@cloud.net.au> wrote: >>>>[ Verilog-2001 allows: ] >>>>module foo( >>>> input clk, >>>> input reset, >>>> input [31:0] bar, >>>> output bletch); >> >>Oh? Doesn't this legal VHDL snippet do exactly the same? >> >>entity foo is >> port ( >> clk : in std_logic; >> reset : in std_logic; >> bar : in std_logic_vector(15 downto 0); >> bletch : out std_logic >> ); >>end entity foo; > >VHDL's duplication of information is different. > >In Verilog-pre-2001, the declaration of a port in >a single module is split into two or three (argument >list, input/output, register/wire). > >In VHDL, you declare the ports twice - once in the >defining module, and once in the instantiating module. >Sure, they should match, you can cut-and-paste (all >but the component/entity keyword), and the compiler >will catch mismatches, but it's still duplication >and IHMO a distraction. When you change your mind >about a port, you have to change it in three places: >the defining module, the instantiating module's component >definition, and the instantiation itself. I'd like to >use a preprocessor to avoid this duplication (like >.h files in C), but that doesn't seem to be encouraged >in the style guides and language standardization. >There is no VHDL preprocessor that is halfway part >of the language, like there is in Verilog or C. > >I'd love to be shown wrong again. If y'all teach >me enough cool features of VHDL, and some Free >(as in freedom) Software shows up that implements >it (as well as Icarus Verilog implements Verilog), >I might even start using it again. It seems the committee agrees with you: since the 1993 edition of VHDL, it has been possible to instantiate entities directly, without using a component declaration. There is a minor loss of flexibility (can't use a configuration, etc.) but this doesn't seem to be a problem in practice. We (everyone in this division) use it almost exclusively in new code. It saves a *lot* of time and effort. It's supported in all the better tools. I think Synopsys tools may have a problem with it though, which might explain why it doesn't appear in the style guides. Regards, Allan.Article: 51895
Hi all, I'm working on a board that has a TI DSP processor, an Altera Flex10ke part that is being used for external bus control, and an associated configuration part, the EPC16, being used to program the Flex10ke and as normal processor accessible flash memory. The way everything interacts I'm having trouble keeping the DPS processor's buses tristated upon boot-up so that the EPC16's external flash interface is tristated allowing it to program the Flex. The problem would be easily solved if we used maybe an EPC8 to exclusively program the flex10ke since the EPC8's external flash interface wouldn't even be connected. However, I like the fact that it is easy to put the byteblaster on the EPC16 JTAG connection and download application code into it. So I'm thinking of using an EPC8 to program the PLD and an EPC16 as a flash memory chip. My question is whether there is any problem using the EPC16 as ONLY a flash memory with no need for the Flex10ke programming, or is there a more suitable flash memory that has an ISP capability via JTAG or another interface. It would just be a pain to have to use the processor and some separate utility to load application (booting) code into the flash memory if it had no external programmable interface. Does the EPC16 "expect" there to be a configuration file? I know you can use "leftover" space as processor memory, but can you just not load a configuration file at all and use the whole space as if it were processor memory and the EPC16 won't object? Thanks. SeanArticle: 51896
creon100@yahoo.com (Sean) writes: > programming, or is there a more suitable flash memory that has an ISP > capability via JTAG or another interface. It would just be a pain to It would be cheaper to use a plain AMD flash or similar. If you can control the pins of the processor attached to the flash using jtag you should be able to program your flash using some clever JTAG software. On the other hand, would it be possible to hold the processor in reset state (or some other state where the bus is tri-state) until config_done? Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 51897
FYI, Has anyone started designing with Altera Cyclone? I just learned that there are some pin changes made between what was in Quartus 2.1 and Quartus 2.2 for the EP1C12 device. Regards, WayneArticle: 51898
Only difference is in how the RAM is used. ROM is just RAM that was
initialized with data when the FPGA was initialized, and is never written
thereafter (the we pins are tied to '0'). LUT stands for look-up table.
I'm not sure of the context inyour source. Generally, LUTs in FPGAs refer
to the small look up tables that make up the FPGA fabric. In Xilinx, these
4 input single output tables can also be used as a 16x1 RAM, or if
preloaded with data as a ROM. For logic, they are loaded with a bit map
that corresponds to the desired logic function, so while they look like a
boolean function of 4 inputs they are actually a 16x1 ROM. In Virtex, the
LUT can also be configured as a 16 bit shift register with a 4:1 selector
on the output. This just adds some logic to the underlying cell that lets
you shift data through the RAM bits.
The Virtex also has block memories, which are synchronous dual port RAMs
(and much larger than the CLB LUTs..4K bits for virtex, 18Kbits for
virtex2). Those can also be used as ROM be preloading them. In some
circumstances, they might be used as a LUT to hold a boolean function with
7 to 12 inputs (virtex) and 1 to 16 outputs, which might be useful for a
state table or a complicated arithmetic function.
Kuan Zhou wrote:
> Hi,
> I am a newbie in Virtex.I found in Virtex the RAM can be LUT,RAM and
> ROM,what's the difference between these three?
>
> Thank you very much!
>
> sincerely
> -------------
> Kuan Zhou
> ECSE department
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 51899> Do any body know whether Xilinx Logicores can be used in Handel-C > designs? > > As far as I know, free tool from Xilinx, "Code Generator", can create > VHDL codes from ligocores. Is it true? Yes, external IP cores such as those generated by Xilinx's 'coregen' tool can be used in Handel-C designs. Take a look at following for details (beware of word wrap) http://www.celoxica.com/technical_library/files/CEL-ENGAPNDEMXilinx%20Corege n%20and%20Handel-C-01000.pdf Cheers, Steffan
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z