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I am using DK1&HandleC in school and it sucked! I was wasted so many hours because I expected too much from the product. The design suite uses up 200+MB memory when compiles even the simplest project, (e.g. something with source code size of 20KB). You would not want to run DK1 in a PC with less than 512M RAM because the compiler is so unoptimised that when your PC has not that much RAM you can look at the task manager during the 5+ minute compile time (EDIF, optimise on) CPU usage is below 5%, while the HDD keeps running because of swapping. The simulator is super-slow and buggy, everytime when you start debugging you have to find a background window and choose which clock to use, at the end you have to press Shift+F5 twice in order to end simulation(which is a apparent bug) The VGA simulator is simply useless because it's so slow (on Pentiume4 1.8G). Celoxica released a floating point library to bloast their "recursive macro" feature of HandleC, only to show how puny their product actually is. When you try to use the FloatAdd macro more than twice, it seems the "recursive macro"(like log2floor or lmo) are expanded so inefficiently that the compiler uses up so much memory(400+M) and it crashes itself. (i.e. that library is simply not practically usable no matter how many gates your target fpga has, because your HandleC code simply cannot compile unless your PC has several gigas of RAM)Article: 51901
Hi, I'm using FDN 3.1i for generating a PROM file to program XC18V02PC84C PROM with the configuration of XCS40XL-4PQ208C. I'm programming the PROM using IMPACT 4.2. PROm is programmed successfully, even verified and readback correctly. When I connect the FPGA which is in master serial mode to PROM, I get CCLK at 1.25MHz, but the data is constant at a pattern of "1111111100" continuously and thus the FPGA is not getting programmed. What can be the reason for this behaviour? Can anybody help me correct it? Thanks and regards SonaliArticle: 51902
Hi, Thank you for your answer.According to my understanding to your email, the LUT refers to the RAMs used for Boolean functions while RAMs refer to the memories for saving the data,am I correct? sincerely ------------- Kuan Zhou ECSE department On Fri, 24 Jan 2003, Ray Andraka wrote: > Only difference is in how the RAM is used. ROM is just RAM that was > initialized with data when the FPGA was initialized, and is never written > thereafter (the we pins are tied to '0'). LUT stands for look-up table. > I'm not sure of the context inyour source. Generally, LUTs in FPGAs refer > to the small look up tables that make up the FPGA fabric. In Xilinx, these > 4 input single output tables can also be used as a 16x1 RAM, or if > preloaded with data as a ROM. For logic, they are loaded with a bit map > that corresponds to the desired logic function, so while they look like a > boolean function of 4 inputs they are actually a 16x1 ROM. In Virtex, the > LUT can also be configured as a 16 bit shift register with a 4:1 selector > on the output. This just adds some logic to the underlying cell that lets > you shift data through the RAM bits. > > The Virtex also has block memories, which are synchronous dual port RAMs > (and much larger than the CLB LUTs..4K bits for virtex, 18Kbits for > virtex2). Those can also be used as ROM be preloading them. In some > circumstances, they might be used as a LUT to hold a boolean function with > 7 to 12 inputs (virtex) and 1 to 16 outputs, which might be useful for a > state table or a complicated arithmetic function. > > Kuan Zhou wrote: > > > Hi, > > I am a newbie in Virtex.I found in Virtex the RAM can be LUT,RAM and > > ROM,what's the difference between these three? > > > > Thank you very much! > > > > sincerely > > ------------- > > Kuan Zhou > > ECSE department > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > > > >Article: 51903
Hi,
I've done a similar thing, only with a block RAM. XST didn't complain
about it. Maybe it doesnt like your strings... try this:
entity uflow is
generic(
MyInit00: bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000003020202060500000302";
...
directoryA: RAMB4_S8
generic map (
INIT_00 => MyInit00,
...
Greetings,
Dennis from Germany
Article: 51904"geeko" <jibin@ushustech.com> wrote in message news:<b0qjos$s2dd0$2@ID-159027.news.dfncis.de>... > Hi all > > Anbody familier with the implementation of AES(Rijindal) --- CTR with CBC > MAC in FPGA ( a C implementation can be found at > http://fp.gladman.plus.com/cryptography_technology/ccm/index.htm ) > I have certain quries about the implementation of a block cipher > How the implemetation can be tested ? (a sample test setup) > How the perfomance ie throughput,latency etc can be measured? > > With regards > geeko Check out: http://www.opencores.org/projects/aes_core/ or my companies web page. We provide a free AES soft core written in Verilog. It might not be exactly what you are looking for, but might be a good starting point. Included with the distribution is a test bench. Regards, rudi ------------------------------------------------ www.asics.ws - Solutions for your ASIC needs - FREE IP Cores --> http://www.asics.ws/ <--- ----- ALL SPAM forwarded to: UCE@FTC.GOV -----Article: 51905
I'm trying to implement Rijndael using DK1. How can I organize the 16 instances of 8x256 bits SBoxes to perform 16 lookups simultaneously? I mean whether to use Distributed RAM or Block RAM? Any speed difference in both the approaches? I'm using Spartan-II Xc2S200. Any suggestion please? AstonishArticle: 51906
Davar Robdan wrote: > > Hi there all, > > I'm a VHDL learner, and looking for some VHDL source. > Is there anyone who have a 32bit ALU with floating point written in > VHDL? Or can you tell me where on the web I can find it? You're in luck. It turns out that I have been working on some packages for floating point in VHDL. Check out: http://www.eda.org/fphdl and you will find the VHDL (and Verilog) for these packages. The VHDL packages are ready for people to try out. Note that to synthesize, you need to comment out all of the packages which access the "real" type (I have already done this, and I can e-mail it to you if you like). -- NAME: David W. Bishop INTERNET: dbishop@vhdl.orgArticle: 51907
Hi, Can anyone explain why do fpgas have such a large number of pins? I understand that for very large design you might need those 150 pins but there are some applications where you need a lot of gates but only 10 I/O pins would be more than enough. The chip takes a lot of place on the pcb and it is a nightmare to do the layout. Why don't we have some mid-large fpgas in terms of gate, but say in a standard 40 pin package? Thanks DavidArticle: 51908
David wrote: > Can anyone explain why do fpgas have such a large number of pins? I > understand that for very large design you might need those 150 pins but > there are some applications where you need a lot of gates but only 10 I/O > pins would be more than enough. A design using a 64bit PCI, an intrface to a processor, a bank or two of SDRAM and a couple of 64 bit (+control and address) interface to custom hardware, plus another hundred plus for termination, reference levels, clocking, debug, plus powers and ground, and 1156 might not be enough. At the other end, once the package is about the same size as the die, there isn't much reason to make it smaller. And as such packages and die are cheap, there isn't much business case for a low pinout package. -- Phil HaysArticle: 51909
This is a general question, but directed at a Virtex 2 family device. I'm using the ISE 5.1i tools and I want to force a self- contained registered bi-directional IOB port, i know the IOBs are configurable in that manner, but I can't get the tools to give it to me with either HDL or Schematic entry attempts ( with the size of the design I cannot consider FPGA editor) . Yes, I've forced registers to IOB inputs & outputs. How do I make this happen? Thanks for any help CharlieArticle: 51910
Hi Don't get frustrated, I had the same problem. Using 512 MB RAM, I could not compile my project. Interestingly enough, I put all the codes in one main file, and it worked. For some reason, I got the EDIF file in this way... By the way, what tool did you use to place and route? I need one, but do not know what to use. IMAD "tsao" <feng_1955@no_spam_ybb.ne.jp> wrote in message news:<b0su3g$1q87$1@news.ecc.u-tokyo.ac.jp>... > I am using DK1&HandleC in school and it sucked! I was wasted > so many hours because I expected too much from the > product. > The design suite uses up 200+MB memory when compiles even > the simplest project, (e.g. something with source code size of 20KB). > You would not want to run DK1 in a PC with less than 512M RAM > because the compiler is so unoptimised that when your PC has not > that much RAM you can look at the task manager during the > 5+ minute compile time (EDIF, optimise on) > CPU usage is below 5%, while the HDD keeps running because of swapping. > > The simulator is super-slow and buggy, everytime when you start > debugging you have to find a background window and choose which > clock to use, at the end > you have to press Shift+F5 twice in order to end simulation(which > is a apparent bug) The VGA simulator is simply useless because it's > so slow (on Pentiume4 1.8G). > > Celoxica released a floating point library to bloast their "recursive macro" > feature of HandleC, only to show how puny their product actually > is. When you try to use the FloatAdd macro more than twice, it seems > the "recursive macro"(like log2floor or lmo) are expanded so inefficiently > that the compiler uses up so much memory(400+M) and it crashes itself. > (i.e. that library is simply not practically usable no matter how many > gates your target fpga has, because your HandleC code simply cannot compile > unless your PC has several gigas of RAM)Article: 51911
IF you don't need all the pins, you don't need to route the board to the pins
you aren't using. You can greatly simplify the layout for example, by using
only the I/O near the physical edge of the package and leaving the majority of
the interior pins either connected to ground, power or open. You can reduce
package ground bounce by wiring unused I/O to ground and then configuring those
pins as outputs permanently tied to a logic '0';
Phil Hays wrote:
> David wrote:
>
> > Can anyone explain why do fpgas have such a large number of pins? I
> > understand that for very large design you might need those 150 pins but
> > there are some applications where you need a lot of gates but only 10 I/O
> > pins would be more than enough.
>
> A design using a 64bit PCI, an intrface to a processor, a bank or two of
> SDRAM and a couple of 64 bit (+control and address) interface to custom
> hardware, plus another hundred plus for termination, reference levels,
> clocking, debug, plus powers and ground, and 1156 might not be enough.
>
> At the other end, once the package is about the same size as the die,
> there isn't much reason to make it smaller. And as such packages and
> die are cheap, there isn't much business case for a low pinout package.
>
> --
> Phil Hays
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 51912
That is more or less correct. A LUT and a ROM are physically the same thing
really, just that the LUT sort of implies a logic look up where a ROM sort of
implies data. The RAM is unique in that its contents are intended to be
rewritten.
Kuan Zhou wrote:
> Hi,
> Thank you for your answer.According to my understanding to your email,
> the LUT refers to the RAMs used for Boolean functions while RAMs refer to
> the memories for saving the data,am I correct?
>
> sincerely
> -------------
> Kuan Zhou
> ECSE department
>
> On Fri, 24 Jan 2003, Ray Andraka wrote:
>
> > Only difference is in how the RAM is used. ROM is just RAM that was
> > initialized with data when the FPGA was initialized, and is never written
> > thereafter (the we pins are tied to '0'). LUT stands for look-up table.
> > I'm not sure of the context inyour source. Generally, LUTs in FPGAs refer
> > to the small look up tables that make up the FPGA fabric. In Xilinx, these
> > 4 input single output tables can also be used as a 16x1 RAM, or if
> > preloaded with data as a ROM. For logic, they are loaded with a bit map
> > that corresponds to the desired logic function, so while they look like a
> > boolean function of 4 inputs they are actually a 16x1 ROM. In Virtex, the
> > LUT can also be configured as a 16 bit shift register with a 4:1 selector
> > on the output. This just adds some logic to the underlying cell that lets
> > you shift data through the RAM bits.
> >
> > The Virtex also has block memories, which are synchronous dual port RAMs
> > (and much larger than the CLB LUTs..4K bits for virtex, 18Kbits for
> > virtex2). Those can also be used as ROM be preloading them. In some
> > circumstances, they might be used as a LUT to hold a boolean function with
> > 7 to 12 inputs (virtex) and 1 to 16 outputs, which might be useful for a
> > state table or a complicated arithmetic function.
> >
> > Kuan Zhou wrote:
> >
> > > Hi,
> > > I am a newbie in Virtex.I found in Virtex the RAM can be LUT,RAM and
> > > ROM,what's the difference between these three?
> > >
> > > Thank you very much!
> > >
> > > sincerely
> > > -------------
> > > Kuan Zhou
> > > ECSE department
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930 Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> > "They that give up essential liberty to obtain a little
> > temporary safety deserve neither liberty nor safety."
> > -Benjamin Franklin, 1759
> >
> >
> >
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 51913In article <3E32D405.23F24096@attbi.com>, Phil Hays <SpamPostmaster@attbi.com> wrote: >At the other end, once the package is about the same size as the die, >there isn't much reason to make it smaller. And as such packages and >die are cheap, there isn't much business case for a low pinout package. This is especially true of the small chip-scale and slightly larger BGA packages. EG, the FT256 BGA package is 182 usable I/Os, with a footprint of 1.7 cm x 1.7 cm. At a 1mm ball pitch, you can fit a LOT of IOs in that footprint (16x16 grid for 256 pins, 182 usable I/Os). -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 51914
> A design using a 64bit PCI, an intrface to a processor, a bank or two of > SDRAM and a couple of 64 bit (+control and address) interface to custom > hardware, plus another hundred plus for termination, reference levels, > clocking, debug, plus powers and ground, and 1156 might not be enough. Let's say I want to design a PCM to PWM converter...I need 2 inputs, 5 outputs + 3 debug = 10 pins. I'm stuck with a 156 pin device....I also need the power of an fpga, since there are a lot of multiplications involving a lot of bits. Using a dsp would be a nightmare. David "Phil Hays" <SpamPostmaster@attbi.com> wrote in message news:3E32D405.23F24096@attbi.com... > David wrote: > > > Can anyone explain why do fpgas have such a large number of pins? I > > understand that for very large design you might need those 150 pins but > > there are some applications where you need a lot of gates but only 10 I/O > > pins would be more than enough. > > A design using a 64bit PCI, an intrface to a processor, a bank or two of > SDRAM and a couple of 64 bit (+control and address) interface to custom > hardware, plus another hundred plus for termination, reference levels, > clocking, debug, plus powers and ground, and 1156 might not be enough. > > At the other end, once the package is about the same size as the die, > there isn't much reason to make it smaller. And as such packages and > die are cheap, there isn't much business case for a low pinout package. > > > -- > Phil HaysArticle: 51915
Hi, Are you going for the ISFPGA next month? Where did you get so many details in hardware when you are a CS student? sincerely ------------- Kuan Zhou On Sat, 25 Jan 2003, Nicholas C. Weaver wrote: > In article <3E32D405.23F24096@attbi.com>, > Phil Hays <SpamPostmaster@attbi.com> wrote: > >At the other end, once the package is about the same size as the die, > >there isn't much reason to make it smaller. And as such packages and > >die are cheap, there isn't much business case for a low pinout package. > > This is especially true of the small chip-scale and slightly larger > BGA packages. > > EG, the FT256 BGA package is 182 usable I/Os, with a footprint of > 1.7 cm x 1.7 cm. At a 1mm ball pitch, you can fit a LOT of IOs in > that footprint (16x16 grid for 256 pins, 182 usable I/Os). > > -- > Nicholas C. Weaver nweaver@cs.berkeley.edu > >Article: 51916
In article <Pine.SOL.3.96.1030125212534.22826A-100000@vcmr-86.server.rpi.edu>, Kuan Zhou <zhouk@rpi.edu> wrote: >Hi, > Are you going for the ISFPGA next month? ISFPGA? Do you mean the ACM FPGA Conference in Monterey? > Where did you get so many details in hardware when you are a CS >student? Easy, my thesis is on a fixed-frequency FPGA architecture. I have to know these things. :) -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 51917
I got a poster in ACM FPGA.ISFPGA means International Symposium on .... It's the same thing.Where did you get the hardware information?From manuals? Why you want to set a fixed frequency for all the applications?I am curious. But I can't go to the conference next month.My boss will go instead of me. On Sun, 26 Jan 2003, Nicholas C. Weaver wrote: > In article <Pine.SOL.3.96.1030125212534.22826A-100000@vcmr-86.server.rpi.edu>, > Kuan Zhou <zhouk@rpi.edu> wrote: > >Hi, > > Are you going for the ISFPGA next month? > > ISFPGA? Do you mean the ACM FPGA Conference in Monterey? > > > Where did you get so many details in hardware when you are a CS > >student? > > Easy, my thesis is on a fixed-frequency FPGA architecture. I have to > know these things. :) > -- > Nicholas C. Weaver nweaver@cs.berkeley.edu > >Article: 51918
In article <Pine.SOL.3.96.1030125223015.12231A-100000@vcmr-86.server.rpi.edu>, Kuan Zhou <zhouk@rpi.edu> wrote: > I got a poster in ACM FPGA.ISFPGA means International Symposium on Most call it "FPGA", eg FPGA 2003. Just as IEEE Symposium on Field-Programmable Custom Computing Machines is "FCCM". What's your poster on? >.... It's the same thing.Where did you get the hardware >information?From manuals? Manuals, intuition, also a couple designs (The best being the AES core I built as a benchmark: 1.3 Gb AES core in 10 BlockRAMs and 800 slices, Spartan II-100-5 speedgrade (A $10 part). It's 1.7 Gb/s in a Virtex E. Remove the pipelining and it is still >500 Mbps regardless of feedback modes). I've developed a pretty good intuition for "Brand X" from doing a few designs, none at all for "Brand A". Also reading Ray Andraka's, Peter Alfke's, and other posts here. Ray Andraka especially is very informative. Also, I'm a bit of a luddite and think in terms of LUTs and flip flops and schematics. Which actually helps if you want to push the limits of the architecture. The difference between no pipelining and smart pipelining can be 2x or even more. You CAN have tools do that automatically (I'm presenting mine at FPGA), but the current systems don't really support that. Hand layout can easily buy another 20-30% or more. > Why you want to set a fixed frequency for all the applications?I am >curious. Higher throughput. Designs will ALWAYS meet the array's architectural throughput if feed-forward or have sufficient task-level parallelism. Not to mention pipelined interconnect to enable higher clock frequencies. Easier to integrate as a coprocessor or system-on-a-chip, as there are now only one clock to deal with, no design-dependant clock domains. Faster tools (route & retime a 6000 LUT design in ~1 minute, route and retime an AES core in 12 seconds). -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 51919
---- SNIP ------
> > > >* The other side of VHDL's strong typing is that usually VHDL
> > > >simulations are slower.
> > >
> > > Could you please say more? I think of strong typing as a compile time
> > > issue. The final circuit is going to be just wires and gates. Why
> > > does it take longer to simulate if they came from one language
> > > or another?
> >
> >
> > A lot of the checking must be done at simulation time. For example:
> > you have two signals, one defined as an integer range of 3 to 57 and
> > the other as an integer range of 5 to 55. Every time you assign a
> > value to each signal, the simulator must check if the signal is within
> > the valid range FOR THIS SIGNAL, and come to a screeching halt if it
> > is not.
>
> And that's a bad thing? I mean, really.
>
> Consider: you've got a state machine, and in one of the states, it
> increments a counter. If your state machine is broken, perhaps that
> counter will increment forever. With Verilog, the counter will simply
> roll over, or whatever. With VHDL, with the counter implemented as an
> unsigned with a specific range, once the code tries to increment past
> the range, the simulator barks at you. That's a Good Thing.
>
> > In Verilog, the simulator simply assigns a bit-vector of the
> > required width and sets the value as needed. This is also why VHDL
> > simulators require more memory - the data-structure representing each
> > signal must contain more information.
>
> OK, so there's some "simulation overhead." In this era of 2 GHz PCs
> with a gigabyte of RAM, that's a detail.
>
> Verilog gives you enough rope to hang yourself.
>
> Do this comparison in verilog and tell me what you expect:
>
> reg [1:0] foo;
>
> if (foo == 2)
> $display ("foo is two!");
> else
> $display ("foo ain't two!");
>
> -a
I never said it was bad: what I said was that it does take more CPU
cycles and memory - not trivial when simulating a large design, even
with a powerful PC (there are many simulations which will eat up any
amount of processing power, up to a 1000-processor super-computer).
When I moved from Verilog to VHDL, I moaned and bitched about its
syntax. I still hate VHDL syntax; I think it is too verbose,
inconsistent internally and I also think that the general syntax of
<do_somthing> when <condition> is ridiculous.
I also thought that the strong typing is limiting (and it is): I know
what I want to do, I don't want the compiler to get in way. HOWEVER,
for a large design involving a number of designers, all these checks
will save a lot of time searching for stupid errors in the design (oh!
this bus should be 43 bits and not 41! why didn't you say so!)
I don't remember Verilog enough to see what is the error in your
example; I do remember that I never understood Verilog's rules of
event propagation. Unlike VHDL, there was (then) no clear definition
of how events propagated through the design, and positioning of
statements in the code would change things. In addition, I could never
be sure when to use wire and when to use reg.
Bottom line: I prefer VHDL - I think it's better. But I was trying to
be objective, and I am aware that there are many people who prefer
Verilog, and think it's better. You can either treat it a "religious"
issue (and refuse to listen to the heretics), have preferences (and
may be convinced to switch), or admit that it doesn't really matter -
the job can be done by either language.
Article: 51920"Ray Andraka" <ray@andraka.com> wrote in message news:3E32F64E.73A27950@andraka.com... > That is more or less correct. A LUT and a ROM are physically the same thing > really, just that the LUT sort of implies a logic look up where a ROM sort of > implies data. The RAM is unique in that its contents are intended to be > rewritten. Last I knew (XC4000 days) it was not possible to initialize a LUT based RAM. The hardware couldn't guarantee against glitches on the R/W line at the end of initialization. So, in FPGA sense, LUT are ROM and not RAM. -- glenArticle: 51921
Hi! I need a 10 bits wide RAM. Unfortunately, Virtex-II RAMs are just 9 bits wide (or 18, but in this case it's only half as deep, and I waste much of it). Is there a way to extend a RAM by one bit? I thought of building a structure with slices. What do you think? Can I use the LUTs for this purpose, combined with a flipflop for synchronous reading? If so, how much logic does it take? 1024 bits needed, divided by 128 bits per CLB equals 8 CLBs, but I don't know how much I have to add for the multiplexing. And is it possible at all? Thanks, DennisArticle: 51922
Hi, Can some one point me to a bus models & test benches for PCI/ISA/ Serial ATA. If none of these are possible, point me to bus models & test benches for any communication protocols. Also please let me know there are any tutorials for writing bus models & test benches. Thanks EdisonArticle: 51923
Hi, Can anyone send me IEEE std 1149.1? Thank you, VladimirArticle: 51924
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