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Forgive me since this is an inch or two off topic. I was just curious about how big a N by M memory cell (i.e 2^N elements of M bits each) takes when build with custom logic. e.g 1 or 2 transistor gates like NOT, NOR, OR, AND and NAND. Just curious if there is a quick estimate [say this is a one-port memory cell too], obviously this esimate would have to take into account the I/O controller of the memory. For my purposes the estimate does not have to be exacting though. Thanks, TomArticle: 35776
Falk Brunner wrote: > Andy Peters schrieb: > > > > Falk Brunner wrote: > > > > > I mean, when the "Hello World" takes 100 Kb in C++, THIS IS REALLY CRAP. > > > > Aw, c'mon. You're talking about what happens when you use Visual C++ to > > write a WINDOWS version of "Hello, World." > > Ahhh, yes ;-) > > > Write a short hello.cpp for your linux box, that runs on the command > > line, and tell me how big it is. > > I aint got linux, yet ;-) > But using TurboPascal, it takes 4k. then your compiler has built-in HelloWorld optimizer!! utkuArticle: 35777
In article <3BCD5EDF.9060009@yahoo.com>, Tom St Denis
<tomstdenis@yahoo.com> writes
>Forgive me since this is an inch or two off topic.
>
>I was just curious about how big a N by M memory cell (i.e 2^N elements
>of M bits each) takes when build with custom logic. e.g 1 or 2
>transistor gates like NOT, NOR, OR, AND and NAND.
>
>Just curious if there is a quick estimate [say this is a one-port memory
>cell too], obviously this esimate would have to take into account the
>I/O controller of the memory. For my purposes the estimate does not
>have to be exacting though.
>
Which answer do you want? :-)
It depends what you mean by "custom logic". If you have only the
traditional gates available, then a single-bit cell essentially
requires two NOR or NAND gates. Then you need a means to set,
reset and access the cell. Some sort of 2-dimensional matrix
decoding is probably required. So you need perhaps three more
gates per cell to do the accessing. That gives us 5*M*(2^N)
gates, plus the decoding stuff round the edge which can be expected
to be roughly proportional to N*M.
Real memories don't work like this, though. They lean heavily
on the use of pass transistors. A "row line" drives the gates
of all the pass transistors on one row, 2^(N/2) cells; then
per-column bit lines are coupled through these pass transistors
to the memory cell itself. Using this technique you can build
a static RAM with either six transistors, or four transistors and
two resistors, per bit; two pass transistors, gated by the row
line, link appropriate points in the cell to "set" and "reset"
bit lines respectively; the other transistors form the bistable
memory cell. DRAM is even smaller; the cell is just a capacitor
and one transistor, gated by the row line, that links the bit
line to the capacitor.
The row lines are driven by a wide decoder that decodes N/2 bits
of address into 2^(N/2) row lines. Bit lines each have a sense
amplifier to read the addressed cell, and appropriate drive
circuitry for writing, all enabled by another N/2 to 2^(N/2)
decoder.
Exciting goodies like synchronous access, pipelining, fast
page mode and burst access are all organised in the row/bit
enabling circuitry round the edge, and have little impact
on the core memory cells.
So I suppose it goes like this:
* the core requires K1 * M *(2^N) elements, K1 per bit.
* the row drive requires K2 * (2^(N/2)) elements, K2 per row.
* the column gubbins requires K3 * M * (2^(N/2)),
K3 per column, replicated per bit in the word.
* decoding clobber related to row and column decoders
requires K4 * N elements.
Clearly K1 is likely to dominate; it's 6 transistors for SRAM,
1 transistor + 1 capacitor for SRAM, 5 gates for DIY logic memory.
The other "size factors" K2, K3, K4 are each likely to be quite
large because of the complexity of all the peripheral logic, but
they don't really matter for any N greater than about ten, because
the K1-related (per-bit) elements outnumber them by about 2^(N/2).
Identifying the cost of each part of the memory in this way also
makes it clear why it's crazy to build memory from scratch in
an FPGA for any but the very smallest memory arrays.
--
Jonathan Bromley
DOULOS Ltd.
Church Hatch, 22 Market Place, Ringwood, Hampshire BH24 1AW, United Kingdom
Tel: +44 1425 471223 Email: jonathan.bromley@doulos.com
Fax: +44 1425 471573 Web: http://www.doulos.com
**********************************
** Developing design know-how **
**********************************
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Article: 35778"Noddy" <g9731642@campus.ru.ac.za> wrote in message news:1003305510.531267@turtle.ru.ac.za... > Hi, > > Was wondering if anyone can recommend either (a.) a newsgroup, or (b.) an > answer to my question. I am trying to search for a fast (>50MHz) > microcontroller with about 256-512 kB SRAM on board and would like to know > if anyone has any ideas. Preferably quite cheap. I found the ATMEL > AT91FR40816 but unfortunately it is out of my price range - will be needing > quite a lot. Does anyone know if any cheaper alternatives. I will be using > the microcontroller as a backend to a Spartan II. Try comp.arch.embedded. Leon -- Leon Heller, G1HSM leon_heller@hotmail.con http://www.geocities.com/leon_heller Low-cost Altera Flex design kit: http://www.leonheller.comArticle: 35779
Jonathan Bromley wrote: > In article <3BCD5EDF.9060009@yahoo.com>, Tom St Denis > <tomstdenis@yahoo.com> writes > >>Forgive me since this is an inch or two off topic. >> >>I was just curious about how big a N by M memory cell (i.e 2^N elements >>of M bits each) takes when build with custom logic. e.g 1 or 2 >>transistor gates like NOT, NOR, OR, AND and NAND. >> >>Just curious if there is a quick estimate [say this is a one-port memory >>cell too], obviously this esimate would have to take into account the >>I/O controller of the memory. For my purposes the estimate does not >>have to be exacting though. >> >> > > Which answer do you want? :-) > > It depends what you mean by "custom logic". If you have only the > traditional gates available, then a single-bit cell essentially > requires two NOR or NAND gates. Then you need a means to set, > reset and access the cell. Some sort of 2-dimensional matrix > decoding is probably required. So you need perhaps three more > gates per cell to do the accessing. That gives us 5*M*(2^N) > gates, plus the decoding stuff round the edge which can be expected > to be roughly proportional to N*M. Gosh... arrg I forgot to mention its a ROM not RAM. Basically I want a one-port ROM where it outputs single words at a time [no pipeline burst reads here...]. > So I suppose it goes like this: > > * the core requires K1 * M *(2^N) elements, K1 per bit. > * the row drive requires K2 * (2^(N/2)) elements, K2 per row. > * the column gubbins requires K3 * M * (2^(N/2)), > K3 per column, replicated per bit in the word. > * decoding clobber related to row and column decoders > requires K4 * N elements. > > Clearly K1 is likely to dominate; it's 6 transistors for SRAM, > 1 transistor + 1 capacitor for SRAM, 5 gates for DIY logic memory. > The other "size factors" K2, K3, K4 are each likely to be quite > large because of the complexity of all the peripheral logic, but > they don't really matter for any N greater than about ten, because > the K1-related (per-bit) elements outnumber them by about 2^(N/2). > Identifying the cost of each part of the memory in this way also > makes it clear why it's crazy to build memory from scratch in > an FPGA for any but the very smallest memory arrays. Since this is a ROM I will assume that K1 is 5 so a rough guestimation is 5*M*2^N gates? TomArticle: 35780
Falk Brunner wrote:
> > What if multiple inputs are changing at the same time (i.e. within one
> > LUT delay)?
>
> I would be VERY carefull about this. Why? Because the LUTs and the FF
> inside the FPGA are DAMM fast.
> Just wait some days, I did some experiments and will publish them in a
> few days.
> You will be scared (I think).
I look forward to it, please post it.
Quicklogic had a similar guarantee (obviously not LUT-based logic) in
their old data book about the logic not glitching under certain
circumstances.
There is nothing like real data to f' up a great theory.
-- rk, circa 1995
--
rk
Just an OldEngineer
Article: 35781Seb wrote: > i'm looking for a pci-card with a large Virtex2 FPGA and memory on it, to > implement a signal processing design. The application has to receive its > data through an external connector and deliver its data to the host pc > system (using the pci bus). Look at www.x2e.de (Virtex/E/II up to 2Mio gates, two memory banks, two 96 pin connector, PLX PCI interface device, software for WinNT and Linux). Regards, ER!KArticle: 35782
I have what is a very simple question. Is there a way to write a long line of VHDL code on 2 or more lines? In particular, I am writing a test bench where a clock signal must be described. This signal is off for the first microsecond and the clocks eight times in the second microsecond at 50 ns per half cycle. Thanks, Theron HicksArticle: 35783
Dear All, I know what an analog mixer is and what it does. In some FPGA DSP documents I see that a mixer is a 8x8 (nxn) complex multiplier. I know the basics of multiplication (the Booth algo) and wonder if it is a real multiplication of 2 8 bit vectorsand the result is 16bit? Are there any adjustments before multiply? Any free VHDL description would be good. ThanksArticle: 35784
In article <3BCD90F5.B1307FD4@egr.msu.edu>, Theron Hicks
<hicksthe@egr.msu.edu> writes
>I have what is a very simple question. Is there a way to write a long
>line of VHDL code on 2 or more lines? In particular, I am writing a
>test bench where a clock signal must be described. This signal is off
>for the first microsecond and the clocks eight times in the second
>microsecond at 50 ns per half cycle.
>
How about
clk <= '0',
'1' after 1000 ns,
'0' after 1050 ns,
'1' after 1100 ns,
etc, etc? That's fine. VHDL is a free-form language; you can
have a new line in the source-code anywhere you could normally
have a space (except, of course, in the middle of a quoted string).
OTOH this is a gruesome way to describe your clock, isn't it?
Don't you prefer this?
ClockGenerator : process
constant Clock_Start_Delay: time := 1 us;
constant Period: time := 100 ns;
constant NumPulses: integer := 8;
begin
clk <= '0';
wait for Clock_Start_Delay;
for i in 1 to NumPulses loop
clk <= '1', '0' after Period/2;
wait for Period;
end loop;
wait;
end process; -- ClockGenerator
OK, it's longer (just!), but I know which I would prefer to write, and
(far more importantly) which I'd prefer to modify three months later.
HTH
--
Jonathan Bromley
DOULOS Ltd.
Church Hatch, 22 Market Place, Ringwood, Hampshire BH24 1AW, United Kingdom
Tel: +44 1425 471223 Email: jonathan.bromley@doulos.com
Fax: +44 1425 471573 Web: http://www.doulos.com
**********************************
** Developing design know-how **
**********************************
This e-mail and any attachments are confidential and Doulos Ltd. reserves
all rights of privilege in respect thereof. It is intended for the use of
the addressee only. If you are not the intended recipient please delete it
from your system, any use, disclosure, or copying of this document is
unauthorised. The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 35785Tim wrote: > What became of Ian? I met two guys of Celoxica this morning and they mentioned, that Ian Page is either very active in his company Celoxica (shareholder business...) and is also having some kind of visiting professorship at Imperial College in London, because most of the hardware research stuff moved from Oxford to Imperial College. But he will come back to Oxford after this visiting professorship... It was not clear, when exactly. Cheers, ER!KArticle: 35786
Hi - On Wed, 17 Oct 2001 16:47:20 +1300, Jim Granville <jim.granville@designtools.co.nz> wrote: > > We've done this in CPLD, not FPGA, but the concept is portable: > >- you can make glitch filters, from tapped delay lines, and a majority > vote scheme. You can build glitch filters with tapped delay lines and majority detection logic, but with an important caveat. These filters will eliminate pulses shorter than X ns and pass pulses longer than Y ns, but X and Y aren't the same number. In between X and Y, the circuit can misbehave; there's a range of pulse durations that can produce glitches at the output of the filter. If there were such a thing as a perfect glitch filter, we could build a metastable-proof flip-flop by filtering out runt pulses. Were it that it were. Bob Perlman >- When creating clocks from delay logic, it is possible, in theory, to > have more than one stable 'traveling-wave', so to avoid this we > Gate the osc to start from a known state > >- The tools need to be watched, sometimes they will optimise out > important delay element(s) :-) > >- We had one interesting bench setup, to self test a delay-osc, > and the LSB's of the display were in the femto-second region. > Of sourse, they moved around, but it was stable to < 10ps > which I thought was quite impressive. > ( at a given Temp/Vcc ) > > The 'delay' quantizer in these PLDs (ATF1504) was 2.7ns >- your FPGA numbers will be << 1ns > >-jgArticle: 35787
Hi,
Could somebody estimate would VirtexII Multiplier work faster if
to read output data with interleaving?
For example a following VHDL code:
(main idea is to use asynchrony working multiplier’s internal
pipeline.
Will VirtexII Multiplier gives correct output result
if input data will be changed before MSB is ready?)
library IEEE;
library Virtex2_Macro;
use IEEE.STD_LOGIC_1164.ALL;
use Virtex2_Macro.Components.ALL;
entity Pipe_Multiplier is
Port ( Clk : In std_logic;
--|^^^^^^^^^|_________|^^^^^^^^^|_________|^^^^^^^^^|______
Clk_120 : In
std_logic; --_______|^^^^^^^^^|_________|^^^^^^^^^|_________|^^^^^^^^^
Clk_240 : In
std_logic; --______________|^^^^^^^^^|_________|^^^^^^^^^|_________|^^
In_A : In std_logic_vector (11 downto 0);
In_B : In std_logic_vector (11 downto 0);
Out_Reg : Out std_logic_vector (23 downto 0) );
end Pipe_Multiplier;
architecture rtl of Pipe_Multiplier is
component MULT18x18
port (
A : in std_logic_vector (17 downto 0);
B : in std_logic_vector (17 downto 0);
P : out std_logic_vector (35 downto 0) );
end component;
signal A : std_logic_vector(17 downto 0);
signal B : std_logic_vector(17 downto 0);
signal P : std_logic_vector(35 downto 0);
signal Pipe_Reg : std_logic_vector(23 downto 0); --registr on output
of multiplier
begin
U1: MULT18x18
port map (
A => A,
B => B,
P => P
);
A(17 downto 12) <= "000000";
B(17 downto 12) <= "000000";
process (Clk)
begin
if rising_edge(Clk) then
A(11 downto 0) <= In_A;
B(11 downto 0) <= In_B;
Pipe_Reg(7 downto 0) <= P(7 downto 0);
end if;
end process;
process (Clk_120)
begin
if rising_edge(Clk_120) then
Pipe_Reg(15 downto 8) <= P(15 downto 8);
end if;
end process;
process (Clk_240)
begin
if rising_edge(Clk_240) then
Pipe_Reg(23 downto 16) <= P(23 downto 16);
end if;
end process;
process (Clk)
begin
if rising_edge(Clk) then
Out_Reg <= Pipe_Reg;
end if;
end process;
end rtl;
Article: 35788
Complex multiplication is needed only if mirror image is a problem.
When you multiply a complex (I & Q) signal with complex oscillator (LO) (
cos(wt),sin(wt) or exp(i*w*t). w = 2*pi*lo_freq ), then the result is
original signal sifted in frequency domain by lo_freq. If lo_freq is
negative, then frequency of original signal is decreased and vice a versa.
If you have complex signal and you multiply it with real local
(cos(wt),0), then you are actually multilplying it with two district local
signals lo_freq and -lo_freq.
(cos(wt),0) = 0.5*(cos(wt),sin(wt)) + 0.5*(cos(wt),-sin(wt))
And result is convolution of original signal with these two district local
signals, in frequency domain.
That is, result is (original signal shifted up by lo_freq) summed with
(original signal sifted down by lo_freq). Both in half amplitude.
If you have real signal and you multiply it with real local oscillator,
then result is of course real.
In complex base we can write this: [ (a,b) is written as a+b*i (i is
imaginary unit)]
sig_in(t) * cos(wt) = sig_in(t) * (cos(wt) + 0*i)
= sig_in(t) * (cos(wt) + (0.5*sin(wt) - 0.5*sin(wt))*i)
= sig_in(t) * 0.5*(cos(wt) + sin(wt)*i) + sig_in(t)*0.5*(cos(wt) -
sin(wt)*i)
= sig_in(t) * 0.5*(cos(wt) + sin(wt)*i) + sig_in(t)*0.5*(cos((-w)*t) +
sin((-w)*t)*i)
Which is sig_in(t) sifted up & down by 2*pi*w herzs.
BUT, because sig_in(t) is real, it is actually sum of positive and
negative version of itself. So in complex base result can be interpreted
to have 4 copies of sig_in(t) in different frequencies.
If we interpret only absolute value of frequency (real signal) then we
have only two different copies of sig_in(t), original_freq + 2*pi*w &
original_freq - 2*pi*w. The proof is left as home exercise.
If you can filter out unwanted mirror and other spurious signals, then the
local oscillator can be as small as one bit.
If we define that lo = '1' means value of one, and lo = '0' means value of
minus one, then multipliction is:
signal sig_in: std_ulogic_vector(7 downto 0);
signal end_sig: std_ulogic_vector(7 downto 0);
signal lo: std_ulogic;
...
end_sig <= sig_in when lo = '1' else -sig_in.
This works as following:
Symmetric square wave (+1 / -1) of frequency freq (our lo signal) is sum
of base frequency (freq), and all odd harmonic frequencies (3*freq,
5*freq, ...). Each with different amplituede (amplitude goes down as
harmonic number increases).
If we multiply sig_in with this square signal, then we are making
convolution in frequency domain with these two signals. It means that
original signal is copied to frequencies orig_freq + freq and orig_freq +
3*freq and orig_freq + 5*freq, etc. AND also copied to frequencies
orig_freq - freq and orig_freq - 3*freq etc...
If (when) your data is time quantised ( = samples), then frequencies going
over sample_rate/2 (or under -sample_rate/2) are aliased back to
-sample_rate/2...sample_rate/2. If these aliases are corrupting your
original data => tough luck (use more bits with local!).
[This is actually done in applications called undersampling. Let's say we
have analog signal in frequency range 100 MHz ... 101 MHz.. And other
frequencies are clean (zero).
Then we can do analog-to-digital conversion with sample rate of 7 MHz
(e.g.). This 7 MegaSamplesPerSecond contains original signal in frequncy
range 2 MHz ... 3 MHz.
2 MHz + 14*7 Mhz = 100 MHz.
This requires that ADC input frequency responce is upto at least 101 MHz.]
Outch, this come out as a quite long text. If you don't grasp something,
please fee free to ask for more explaining respond.
--
Topi
eas wrote:
> Dear All,
> I know what an analog mixer is and what it does. In some FPGA DSP
> documents I see that a mixer is a 8x8 (nxn) complex multiplier. I know
> the basics of multiplication (the Booth algo) and wonder if it is a
> real multiplication of 2 8 bit vectorsand the result is 16bit? Are
> there any adjustments before multiply? Any free VHDL description would
> be good.
>
> Thanks
Article: 35789Giving you a straight answer: If you are using an FPGA that has dedicated memories, these will be the best solution. On Xilinx at least they can be used as ROMs by sticking the initial values in the bitstream, although this is a little convoluted it works very well. Taking the question more seriously than it deserves: ( :) ) If your ROM has a small address space, and there is some order to the data, you may be able to express the relationship between the address and the data being output reasonably compactly in logic. This could potentially be relatively slow compared to a ROM as it may involve many layers of logic, muxes, etc. Try sticking the first 16 terms into a compiler as a case statement and see what pops out. |Gosh... arrg I forgot to mention its a ROM not RAM. Basically I want a |one-port ROM where it outputs single words at a time [no pipeline burst |reads here...]. -- Posted using Nographer - News in your Browser http://www.nographer.com - free, open source, and smartArticle: 35790
Will this include Max and Quartus or just Quartus? Any info at all
about how the licensing will work? Any idea when an official
announcement might be made?
Thanks
Tim
"James C. Schwalbe" <schwalbe@compuserve.com> wrote in message news:<9qe04d$f21$1@suaar1ab.prod.compuserve.com>...
> Altera will begin supporting the Linux operating system next year.
>
> Jim Schwalbe
> Sr. Field Apps Eng
> Altera Corp.
> jschwalb@altera.com
>
> "Rene Tschaggelar" <tschaggelar@dplanet.ch> wrote in message
> news:3BBC6DAA.B11075E6@dplanet.ch...
> > When I look at the rather complicated procedure concerning
> > MaxPlus2 of Altera, which only runs 3 month, I doubt it.
> > The commercial version requires a dongle.
> >
> > Rene
> > --
> > Ing.Buero R.Tschaggelar - http://www.ibrtses.com
> >
> > Zoltan Kocsi wrote:
> > >
> > > I was away for a while from the NG, is there any word on FPGA
> > > vendors offering (or planning to) Linux toolchains (in the same
> > > config and pricing as their Win tools) ?
> > >
> > > Thanks,
> > >
> > > Zoltan
> > >
> > > --
> > > +------------------------------------------------------------------+
> > > | ** To reach me write to zoltan in the domain of bendor com au ** |
> +--------------------------------+---------------------------------+
> > > | Zoltan Kocsi | I don't believe in miracles |
> > > | Bendor Research Pty. Ltd. | but I rely on them. |
> > > +--------------------------------+---------------------------------+
Article: 35791Look at TI and Analogue Devices DSP chips - you get the speed and you can get them with big RAMs. TI 5509 (not quite sampling yet) looks promising for your purpose. Or to get back on topic - how about Altera + NIOS or one of the new Altera's with built in ARM core. Michael Kellett "Noddy" <g9731642@campus.ru.ac.za> wrote in message news:1003305510.531267@turtle.ru.ac.za... > Hi, > > Was wondering if anyone can recommend either (a.) a newsgroup, or (b.) an > answer to my question. I am trying to search for a fast (>50MHz) > microcontroller with about 256-512 kB SRAM on board and would like to know > if anyone has any ideas. Preferably quite cheap. I found the ATMEL > AT91FR40816 but unfortunately it is out of my price range - will be needing > quite a lot. Does anyone know if any cheaper alternatives. I will be using > the microcontroller as a backend to a Spartan II. > > thanks > adrian > > >Article: 35792
On 16 Oct 2001 08:59:07 +0100, Martin Thompson <martin.j.thompson@trw.com> wrote: > "AH" <akha@home.com> writes: > <snpi> > > Can I declare open drain bidirs in verilog and let > > Altera take care of the rest? :) > > > > You should be able to. I've done it thusly in VHDL (using two > internal signals may not be strictly necessary). The signals are > std_ulogic and the pin is INOUT stdlogic. Perhaps a verilogger can > assist you further if required - sorry! > > SCL_IN_signal <= SCL_pin; > SCL_pin <= '0' when SCL_OUT_signal = '0' else 'Z'; > > This synthesises to a birdirectional pin with an open-drain driver. > Why should this not translate into a push-pull buffer. Or is this specified to become an OD in an altera device? As far as I know this becomes a normal LVTLL threestate pin on a Xilinx S2. regards, HenkArticle: 35793
Noddy wrote: > > Hi, > > Was wondering if anyone can recommend either (a.) a newsgroup, or (b.) an > answer to my question. I am trying to search for a fast (>50MHz) > microcontroller with about 256-512 kB SRAM on board and would like to know > if anyone has any ideas. Preferably quite cheap. I found the ATMEL > AT91FR40816 but unfortunately it is out of my price range - will be needing > quite a lot. > Does anyone know if any cheaper alternatives. The new AT91R40008 is a die shrink of their 128K SRAM device, and has 256K SRAM, and 66MHz spec. http://www.atmel.com/atmel/acrobat/1732s.pdf Anything with that much SRAM will not be 'cheap', but you should define what you mean by 'a lot' and 'quite cheap' ! -jgArticle: 35794
Thanx for the link, Ken. didn't know this company...but as far as i can see they're not using Virtex-2 devices. cheers, Seb "Erik Lins" <e.lins@hightronix.de> wrote in message news:9qjtvo$otn99$1@ID-112720.news.dfncis.de... > Seb wrote: > > i'm looking for a pci-card with a large Virtex2 FPGA and memory on it, to > > implement a signal processing design. The application has to receive its > > data through an external connector and deliver its data to the host pc > > system (using the pci bus). > > Look at www.x2e.de (Virtex/E/II up to 2Mio gates, two memory banks, two 96 > pin connector, PLX PCI interface device, software for WinNT and Linux). > > Regards, > ER!K >Article: 35795
I need an ~100 MHz SDRAM controller core for 64 bit/256 Mbytes SDRAM. Does anyone have any recommendations on using either the Xilinx references or acquiring 3rd party IP for the task? ThanksArticle: 35796
Seb wrote: > > Thanx for the link, Ken. didn't know this company...but as far as i can see > they're not using Virtex-2 devices. > > cheers, > Seb Nallatech make a board, the Ballynuey 3 with either an XC2V1000 or a 3000 on there. 4 Meg of RAM. For IO, you might need to make your own board to sit into the DIME slots they use. Here's a link ... http://www.nallatech.com/products/dime_professional/ballynuey3/index_en.htm Good luck Phil -- --------------------------------------------------------------------- __ / /\/ Dr Phil James-Roxby Direct Dial: 303-544-5545 \ \ Staff Software Engineer Fax: Unreliable use email :-) / / Loki/DARPA Email: phil.james-roxby@xilinx.com \_\/\ Xilinx Boulder ---------------------------------------------------------------------Article: 35797
> > > Write a short hello.cpp for your linux box, that runs on the command > > > line, and tell me how big it is. > > > > I aint got linux, yet ;-) > > But using TurboPascal, it takes 4k. > > then your compiler has built-in HelloWorld optimizer!! heh. funny. i use linux all day long, but let me clear this up. you go ahead and make your hello world app, but link it *static* and you won't see a nice little file. you'll be lucky to see hello world take less than 1-2MB. if you link it dynamic, it doesn't make it any smaller, it just means everyone gets that one copy of the libc. the linking system on linux/unix leaves much to be desired. (i remember those days in the 80's of turbo pascal... before kernel hacking... fun.)Article: 35798
Phil, seems to be what i need...do you have any experience yourself with this Ballynuey board? Can you give me an estimate of its price? cheers, Seb "Phil James-Roxby" <phil.james-roxby@xilinx.com> wrote in message news:3BCE0504.F6948DAD@xilinx.com... > Seb wrote: > > > > Thanx for the link, Ken. didn't know this company...but as far as i can see > > they're not using Virtex-2 devices. > > > > cheers, > > Seb > > Nallatech make a board, the Ballynuey 3 with either an XC2V1000 or a > 3000 on there. 4 Meg of RAM. For IO, you might need to make your own > board to sit into the DIME slots they use. > Here's a link ... > http://www.nallatech.com/products/dime_professional/ballynuey3/index_en.htm > Good luck > Phil > > -- > --------------------------------------------------------------------- > __ > / /\/ Dr Phil James-Roxby Direct Dial: 303-544-5545 > \ \ Staff Software Engineer Fax: Unreliable use email :-) > / / Loki/DARPA Email: phil.james-roxby@xilinx.com > \_\/\ Xilinx Boulder > ---------------------------------------------------------------------Article: 35799
Hi everyone. I'm a software engineer and graduating soon for my MSEE. I would like to make a career change to hardware design, since i'm more interested in hardware design now after taking advanced computer architecture courses, advanced logic design, and other hardware related courses. Also, I'm learning verilog and xilinx fpga now. What do you suggest me to learn specifically to land a job in fpga/asic designer, especially for new guy like me? (such as, pci bus design, risc machine, etc) or any advice what to start, roadmap, and everything you can advice. Thanks so much. I'd appreciate any help. Jack
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