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Hi, AME wrote: > "Brian Drummond" <brian@shapes.demon.co.uk> wrote in message > news:isc5ttcc4gtm1t2vko4jtcej5e0v2845o7@4ax.com... > > Not designed as a documentation language but derived from a type-safe > > language from a high-reliability environment, based on its own tried and > > true convention. The designers apparently thought such things might be > > important in hardware design. > > Well, hardware design has been done very succesfully for a long time with > schematic tools that don't have the "type-safe", "high-reliability" Yes, and I bet, you design only once in your life a 64bit-2to1-multiplexer with schematic entry If someone show you the singel line, that does this work in HDL (both Verilog and VHDL) Schematic entry ist fine to describe the toplevel (just drag and dropp ALU, FSM, RAM,..) And its fine to see what you do, describing very little parts of code(eg. 1-Bit addition) But if your familliar with a HDL you reach the same effort in dramatically less time. > gigahertz-processors-on-every-desktop there has to be a better way to go > from problem-space to solution-space than having to type things like > "begin", "end", "process", "register", (7 downto 0), etc. Well there are some ideas of codegenerators on the one hand and tools to support you on syntaxlevel on the other hand. I prefer emacs with VHDL-style (See the FAQ). you just need to type pro<tab>, enter the signals for sensitylist and get a ready process. > So far I'm leaning towards VHDL, even though, on first inspection, I don't > really like it. I don't know if you like Verilog, but I think you should use the one of the both you like more. In some cases Verilog is a better solution, in other VHDL saves time, but both language are similar in that you first learn the _real_ (TM) language, when your fammiliar with digital design. bye Thomas -- Thomas Stanka Bosch SatCom GmbH BC/EMD4 D-71522 Backnang Tel. +49 7191 930-1690 Gerberstr. 49 Fax. +49 7191 930-21690 Zi. 10/528 Thomas.Stanka@de.bosch.comArticle: 35876
Hello, I am using SpartanXL as a PCI bnridge. On some new main-boards I have following problem: when I power down computer and after about one second I switch power on Spartan's INIT goes high, but there is no CCLK and DONE is not going high. This happens often but not always. What could cause this problem? Regards, Piotr ForytArticle: 35878
Hello, I currently use FPGA-Express for VHDL synthesis and EDIF export and Altera MaxPlus2 or Xilinx M1 for implementation. In either tools I can specify an option, which implements statemachines as one-hot statemachines (one dedicated bit per state). So, should I use this option in FPGA-Express on MaxPlus2/M1 ? What will be the difference in implementation ? No difference ? What happens if I use the option in both tools ? Cheers, ER!KArticle: 35879
Hi everybody! I am looking for crowded FPGA bitstreams that can serve as worst case scenarios for a publication on reconfiguration techniques. I know that there are some people in this newsgroup that are quite good at sqeezing the last out of an FPGA. Please support my research by sending in your bitstreams with the highest deviceutilization that you have. You can find further instruction at the following page: http://www.sulimma.de/fpga/bitstreams/ Peter or Austin: Maybe Xilinx has some of theire own examples to prove that the days of 60% device utilization are over? Kolja Sulimma University of Kaiserslautern GermanyArticle: 35880
> [snip] > > I don't know if you like Verilog, but I think you should use the one of > the both you like more. In some cases Verilog is a better solution, in > other VHDL saves time, but both language are similar in that you first > learn the _real_ (TM) language, when your fammiliar with digital design. OTOH, at every advance of the standards of both languages tend to be alike so in the next 10 years probably there will be no significiant distinction between two languages. So choosing either of them won't harm IMHO. UtkuArticle: 35881
Problem Description: --------------------------------------- I tried to write data into text file (for simulation) using std.textio package. The most important part of code was: library IEEE; use IEEE.std_logic_1164.all; use std.textio.all; ... process(clock) variable TextLine: line; file TextFile : text is out "text.txt"; begin if(clock'event and clock='1') then write(TextLine, "HELLO WORLD"); writeline(TextFile, TextLine); end if; end process; ... At line 21 was: write(TextLine, "HELLO WORLD"); and that generated error message: "Expression is ambiguous" Is it possible to write into text file with Foundation 3.1i (and how to do it?) and when it isn't can you recommend some tool that I could use? Error Message: --------------------------------------- Checking...Error L21/C0 : #0 Error: D:/fndtn/active/projects/test2/test2.vhd line 21 Expression is ambiguous. (VSS-501) 1 error(s) 0 warning(s) found Thanks in advance.Article: 35882
IMHO there's a big difference between a computer language and a hardware description language. Although the syntax is quite similar, one should always keep in mind, what the meaning of the code is. In a HDL, the code is implemented as a hardware device, not as a series of instructions which are executed by a processor. This also influences the code writing style. As an example take the POINTER found in coputer languages, which is typical for an architecture based on a central memory. DanArticle: 35883
Hi, AME wrote: > <hamish@cloud.net.au> wrote in message > news:3bd27bb1$0$26089$afc38c87@news.optusnet.com.au... > > >>>... In some cases the same symbology is used for totally >>>differnt purposes. >>> >>Can you give an example of this last point? >> > > Sure. "<=" used for "assignment" as well as "less than or equal to". > > Of course, you might say that the context differntiates which is meant. > Well, take, for example: > > a <= b <= c; > > 1- Does this mean "evaluate b less-than-or-equal-to c and assign this to > a"? > 2- Or, does it mean, "c to both b and an"? > > As I understand the language now, you need to know whether a is a signal or > a variable. I could be wrong on this, but I think that if a is a signal > then then the above statement functions per 1 above. If a is a variable > then it works per 2 above. VHDL always "chooses" option 1. The first "<=" is a signal assignment operator while the second "<=" compares b and c. This code does not compile if a is a variable. -- EdwinArticle: 35884
pfor schrieb: > > Hello, > I am using SpartanXL as a PCI bnridge. On some new main-boards I have > following problem: > when I power down computer and after about one second I switch power on > Spartan's INIT goes high, but there is no CCLK and DONE is not going high. > This happens often but not always. What could cause this problem? Too big power supply decoupling, so that it does not fully discharge?? -- MFG FalkArticle: 35885
Very simply, digital circuit design is the art of designing electronic systems
which employ digital logic of any kind. This could be logic which is
implemented by analog circuits such as discrete transistors which are used to
form simple gates ("AND", "OR", etc). Or it could be logic which exists in a
state of the art microprocessor, like the P4. A motherboard for your PC is
considered an example of digital circuit design even though there are certain
to be analog issues.
On the other hand, digital IC design is literally the design of a digital IC
(a chip). Without confusing the issue with FPGAs, which are getting more like
ASICs every day, a digital integrated circuit, or digital IC, is composed of
analog circuits which implement digital functions. A good example is an old
standard 7400 series part which represents low scale integration. A 74XX00
contains analog circuits which implement 4 digital "NAND" gates in a physical
space far smaller than would be the case if discrete analog components were
used on a PCB.
I did not want to confuse you with references to analog, but at some level,
all circuitry is analog. When digital circuits were fairly slow, you did not
have to know much about analog circuits in order to be a digital designer. All
that has changed.
I hope this helps.
Tom Cipollone
Tomasz Brychcy wrote:
> Hello,
>
> What is a difference between digital circuit design and digital IC design?
>
> With sincerely,
>
> Tomek
Article: 35886Edwin Naroska wrote: > Hi, > > AME wrote: > > > <hamish@cloud.net.au> wrote in message > > news:3bd27bb1$0$26089$afc38c87@news.optusnet.com.au... > > > > > Well, take, for example: > > > > a <= b <= c; > > Even to reduce VHDL RSI I would not write something like this. Even if it is well defined from the synthesis and simulation aspects IMHO it's still a bad coding style. if (b <= c) then a <= '1'; else a <= '0'; is much clearer. In Verilog this would be (as a wire): assign a = (b <= c) ? 1 : 0; (as a reg) a <= (b <= c) ? 1 : 0;Article: 35887
Allan Aasma wrote: > > Problem Description: > --------------------------------------- > I tried to write data into text file (for simulation) using std.textio > package. The most important part of code was: > library IEEE; > use IEEE.std_logic_1164.all; > use std.textio.all; > ... > process(clock) > variable TextLine: line; > file TextFile : text is out "text.txt"; > begin > if(clock'event and clock='1') then > write(TextLine, "HELLO WORLD"); > writeline(TextFile, TextLine); > end if; > end process; > ... > > At line 21 was: write(TextLine, "HELLO WORLD"); and that generated error > message: "Expression is ambiguous" > Is it possible to write into text file with Foundation 3.1i (and how to do > it?) and when it isn't can you recommend some tool that I could use? > > Error Message: > --------------------------------------- > Checking...Error L21/C0 : #0 Error: D:/fndtn/active/projects/test2/test2.vhd > line 21 Expression is ambiguous. (VSS-501) 1 error(s) 0 warning(s) found Sounds like you're using a SYNTHESIS tool when you should be using a SIMULATION tool -- ModelSim, Aldec, Symphony, etc. -aArticle: 35888
Erik Lins wrote: > > Hello, > I currently use FPGA-Express for VHDL synthesis and EDIF export and Altera > MaxPlus2 or Xilinx M1 for implementation. In either tools I can specify an > option, which implements statemachines as one-hot statemachines (one > dedicated bit per state). So, should I use this option in FPGA-Express on > MaxPlus2/M1 ? What will be the difference in implementation ? No difference > ? What happens if I use the option in both tools ? I don't think there's an option in the P+R tools to select one-hot-or-not state machines. Set it at the synthesis stage. -aArticle: 35889
Kevin Brace wrote: > One thing I think is a problem of almost all HDL (Verilog and VHDL) > books out there is that the books don't clearly define which element > of the language is synthesizable by the synthesis tool and which is > not. > Instead, almost all books mixes up the stuff that no one uses, the > stuff that can't be synthesized, and the stuff that can be > synthesized. > A beginner has no idea of the concept of what is synthesizable, so > that person will waste time learning stuff no one uses, and less of > the stuff that is important now (the synthesizable part of the > language). I disagree. I have found that all of that so-called "useless" stuff becomes very useful indeed when you're trying to simulate and verify a design. The traditional approach to learning an HDL has been to learn the "whole" language, and at some point, learn the "synthesizable subset." The problem is that this subset varies among tools. Some tools do RAM and ROM inference, some don't. Some need "hints" and pragmas and non-language stuff to cajole the tool into doing what you want. --aArticle: 35890
Bob Perlman wrote: > Sons. If you're doing digital design, it deserves a place on your > bookshelf. But I don't think the software engineers are going to like > it much. I think anything that prevents the software guys from thinking that they can do hardware design is a Good Thing. -aArticle: 35891
Andy Peters wrote: > Erik Lins wrote: > > > > Hello, > > I currently use FPGA-Express for VHDL synthesis and EDIF export and Altera > > MaxPlus2 or Xilinx M1 for implementation. In either tools I can specify an > > option, which implements statemachines as one-hot statemachines (one > > dedicated bit per state). So, should I use this option in FPGA-Express on > > MaxPlus2/M1 ? What will be the difference in implementation ? No difference > > ? What happens if I use the option in both tools ? > > I don't think there's an option in the P+R tools to select > one-hot-or-not state machines. > > Set it at the synthesis stage. > > -a ... but only for FPGAs. For CPLDs, which are really no more than a bunch of PALs sharing inputs from some sort of switch matrix, the basic logic is an and/or array feeding an FF or output pin. In this case binary encoded SMs are better suited.Article: 35892
Hi,
I've synthesized a design for a SpartanXL 05-4vq100(I inherited much of
the design from another project, so I'm not that familiar with it yet), and
when I look at the functional schematic, I see all these extra symbols on
certain signals, mainly load signals going to registers. I don't know what
they are or where these elements came from. Here's a typical example of
elements that the load signal goes through now: c8(inv), c7(buf), c9(inv),
c0/c0(buf), c0/c2(buf), c0/c3(buf). What are these? Is this something that
is automatically insterted by the synthesis tool, or is this something that
is in the design (and I just haven't stumbled onto it yet?).\
Any help would be appreciated, thanks.
Dave
Article: 35893Hello, I'm a computer science student and a cryptography student. I'm working on a symmetric cipher designed for efficient hardware implementation. I know quite a bit about the software side but little about the hardware side. I am wondering if someone is willing to read the formal paper I am preparing and help provide insight into details about an actual implementation. If someone is willing to help they get to keep full rights to their implementation [i.e they can sell, give away, etc the design]. From the crypto side i've done quite a bit of analysis. My design is based around using only simple primitive operations such as XOR and AND. Please email me if you want to help and I will send you a copy of the paper in either .ps or .pdf format [you can ask for either one]. I'm not really looking for an exact implementation [although that would admitedly be more useful]. Just more insight into how big the thing would be [in either FPGA cells or custom hardware], how long the gate delay is of the round function [i.e round function is called 16 times so the delay of the round function is crucial] and ideas on how to speed up the core [i.e pipelining, multiple cores, etc..] If anyone is really ambitious they could provide substantial details and insight and could be a co-author of the paper for the conference. Thanks, TomArticle: 35894
One of the many features that VHDL has that Verilog lacks is generational constructs. This is a red herring raised all the time, in most Verilog teams there is usually some software skill that comes into play to boost the language. Before Synthesis was so prevalent it was very common for IC guys to write their own simple Silicon Compilers that were point tool generators. In C this could be a simple hello_world program with some printf statements writing a generated file that is also correct by construction x hdl. Changing a few #defs (or consts) can create all the versions you could ever want. The Verilog fragments can then be 'included into place in a hierarchy framework etc etc. In fact once a Verilog version is done, it is usually not so difficult to change the writer to do another output language as well such as the C version so that it can also be simulated as part of the main C model. I did this all the time before Synopsys, but the reasons for doing so still remain. Even if Verilog is improved with a generate, it will probably always be inferior to point tools that anyone can just knock up on any PC with any reasonable programming language C, Perl, Java.... My 2 centsArticle: 35895
Tomasz Brychcy wrote: > > What is a difference between digital circuit design and digital IC design? > Here is my practical definition: When you do "digital circuit design" you use available digital ICs ( or in the old days transistors, resistors, etc) to build a system on a pc-board. When you do "digital IC design", you design circuitry inside a chip. Usually you would be working for an IC company. The discipline is similar, but the digital IC designer has to worry about additional issues that the IC user can safely ignore. Peter AlfkeArticle: 35896
Check the behavior of the SpartanXL Vcc (3.3 V). How fast does it go down when you turn off the computer? Maybe you should put a bleed resistor across the regulator... Peter Alfke pfor wrote: > Hello, > I am using SpartanXL as a PCI bnridge. On some new main-boards I have > following problem: > when I power down computer and after about one second I switch power on > Spartan's INIT goes high, but there is no CCLK and DONE is not going high. > This happens often but not always. What could cause this problem? > > Regards, > Piotr ForytArticle: 35897
Yes, I do agree with you that the element of HDL that doesn't
synthesize becomes important when someone has to do verification on
the design.
But from a beginner's point (I knew practically nothing about HDL
about a year ago now) who knows nothing about HDL, and wants to design
digital circuits using HDL, the first thing they will like to know
will be the stuff that synthesizes, not the stuff that is used in
verification.
After the beginner gets the design up to the point of it can be
synthesized, I do think that the part of HDL that is used in
verification becomes more important.
About two years ago, I tried to learn HDL in a way what you
described as "The traditional approach" of learning the whole
language, but it just didn't work.
Learning the whole language is just too much because that I had no
idea how to apply it in a actual design.
Eventually I got discouraged, and quit.
I tried to learn HDL again about a year ago, but this time, my main
objective was not to learn HDL, but to design something, and learn HDL
through the design process.
It worked pretty well, and now I reached to a point where I have to do
verification on the design.
During that process, I only worried about the stuff that synthesized,
and didn't pay much attention to the stuff that is used in
verification.
Now I am realizing that the importance of non-synthesizable part of
HDL, but again, a beginner who knows nothing shouldn't worry too much
about the non-synthesizable stuff initially.
In retrospect, the reason I wasn't able to learn HDL two years ago was
not only because the books I read weren't that interesting (used a
Verilog book called Verilog Digital System Design by Navabi (ISBN
0-07-047164-9), and a VHDL book called VHDL for Programmable Logic (I
don't remember the exact name) by a guy who works at Cypress
Semiconductor), but also because I didn't have a clear goal of what I
wanted to design, and therefore, I tried to learn the whole language.
Regards,
Kevin Brace (don't respond to me directly, respond within the
newsgroup)
Andy Peters <andy@exponentmedia.deletethis.com> wrote in message news:<3BD47664.BDDA6CA3@exponentmedia.deletethis.com>...
> Kevin Brace wrote:
>
> > One thing I think is a problem of almost all HDL (Verilog and VHDL)
> > books out there is that the books don't clearly define which element
> > of the language is synthesizable by the synthesis tool and which is
> > not.
> > Instead, almost all books mixes up the stuff that no one uses, the
> > stuff that can't be synthesized, and the stuff that can be
> > synthesized.
> > A beginner has no idea of the concept of what is synthesizable, so
> > that person will waste time learning stuff no one uses, and less of
> > the stuff that is important now (the synthesizable part of the
> > language).
>
> I disagree. I have found that all of that so-called "useless" stuff
> becomes very useful indeed when you're trying to simulate and verify a design.
>
> The traditional approach to learning an HDL has been to learn the
> "whole" language, and at some point, learn the "synthesizable subset."
> The problem is that this subset varies among tools. Some tools do RAM
> and ROM inference, some don't. Some need "hints" and pragmas and
> non-language stuff to cajole the tool into doing what you want.
>
> --a
Article: 35898
I don't have anything to say about VHDL comments you made (I don't
know much about VHDL, so I cannot compare the two languages).
But besides the lack of `if (not `ifdef), I am happy with Verilog
right now.
Regarding the gate count, I used only LUTs and FFs in my
design, and didn't used any of the stuff that may be proprietary
(BlockRAM, DLL, etc.) because in my design, design portability (i.e.,
porting my design from a Xilinx device to an Altera device without
modifying the HDL code) is important.
Also, I didn't see the need to use the Xilinx proprietary stuff to
complete the design.
The synthesis tool I used was XST Verilog that came with ISE WebPack
4.1, and the design with a small user module consumed about 35% of the
Slices of XC2S150.
P&R (Place & Route) tool told me that the equivalent gate count was
about 10,000 gates.
Okay, I suppose that will equate to a little less than 30,000 gates,
but certainly, far less than the 150,000 "system" gates Xilinx always
claims about.
Yes, I do realize that the term "system gates" really means nothing,
and counts BlockRAM as gates, but should RAM really be called gates?
I personally think storage elements like RAM or ROM shouldn't be
counted as gates.
Regards,
Kevin Brace (don't respond to me directly, respond within the
newsgroup)
Ray Andraka <ray@andraka.com> wrote in message news:<3BD391CB.1D6D7E6E@andraka.com>...
> Personally, I found VHDL to be more useful for a full range of design capability. The big
> thing at this point is that Verilog does not have an equivalent to the VHDL generate
> statement. This is extremely useful for building macros or anywhere else you have
> replicated logic. In my case, I have built up a library of macros built by instantiation
> of primitives so that I get exactly what I want every time. Even for those not inclined
> to build macros, a generate facility is often a welcome tool for such mundane things as
> building memory banks from block RAMs. As I understand it, the next generation Verilog
> will have a generate statement. VHDL also knows about attributes, so you can modify
> attributes as a function of iteration in a generate statement (step and repeat placement
> for example). Verilog's attributes are comments which are quite inflexible, and appear to
> be an afterthought. They are not natural to the language. These two items make verilog
> very awkward to use in designs where you are doing some low level design to attain
> performance or density.
>
> By what measure are you determining gate count? I typically see "equivalent gates"
> reported by PAR to be 1.5 to 3 times the "system gates" size of the device. For example,
> on a recent XC2S100, I got an "equivalent gate count" reported by PAR as 184,328 gates, or
> 1.8x. That has 57% of the LUTs, 68% of the slice flip-flops and 90% of the block RAM is
> used. In another recent example, an XCV2000e design reports 4,722,511 "equivalent gates",
> or almost 2.4x the nominal device size. In that case, 57% of the luts, 68% of the
> flip-flops, and 100% of the block ram is used. If you are not converting to ASICs
> however, those "gates" don't have much bearing on the device capacity. A much better
> measure is a count of the number of LUTs and flip-flops you have available.
>
> Kevin Brace wrote:
>
> > Although I have less than a year experience using Verilog, I will like
> > to chip in my two cents.
> > A little less than a year ago, I also had to decide whether or not I
> > wanted to use Verilog or VHDL.
> > I picked Verilog because the language seemed somewhat simpler than
> > VHDL, and seemed like there is less unnecessary writing than VHDL to
> > do the same thing.
> > Although I do have three things I don't like about Verilog.
> > The first thing will be that keywords "begin" and "end."
> > I think they should instead be "{" and "}" like in C language.
> > The second thing will be that Verilog has weak conditional compilation
> > support.
> > For example, compiler directive "`ifdef" can only check to if a text
> > macro is defined, and can't check a value (in other words, "`if"
> > doesn't exist in Verilog).
> > The third thing will be type checking.
> > Yes, VHDL has stricter type checking, and Verilog's is less
> > restrictive.
> > I personally think type checking should be strict.
> > Regardless of what Aldec says about Verilog from what I read
> > (like EE Times), most ASIC designs done in the US uses Verilog, not
> > VHDL.
> > Aldec claims that Verilog "lacks the constructs needed for system
> > level specification," but if so, is VHDL any better? (I don't know. I
> > don't use VHDL.)
> > There seems to be more VHDL books out there compared to
> > Verilog (for example, in Borders or Barns & Noble).
> > One thing I think is a problem of almost all HDL (Verilog and VHDL)
> > books out there is that the books don't clearly define which element
> > of the language is synthesizable by the synthesis tool and which is
> > not.
> > Instead, almost all books mixes up the stuff that no one uses, the
> > stuff that can't be synthesized, and the stuff that can be
> > synthesized.
> > A beginner has no idea of the concept of what is synthesizable, so
> > that person will waste time learning stuff no one uses, and less of
> > the stuff that is important now (the synthesizable part of the
> > language).
> > Although I don't know if you have the hardware (prototype
> > board with an FPGA) already, but if you don't have any, I recommend
> > visiting Insight Electronics' Xilinx prototype board website
> > (http://www.insight-electronics.com/solutions/kits/xilinx/index.shtml).
> > Especially the ones that use Spartan-II are pretty affordable (I own
> > Insight Electronics Spartan-II PCI board which costs only $145).
> > One thing you should have in mind that PLD vendors lie about
> > the gate count the chip has.
> > For example, Xilinx calls its Spartan-II XC2S150 part as 150,000
> > "system gates", but if you drop the "system" part of it, the
> > realistically achievable gate count will drop to about 25,000 gates
> > from my experience using that part.
> > The Xilinx's "system gates" inflates the realistically achievable gate
> > count by 6 times, so before selecting a device for your application,
> > you should know the gate count that the device can achieve
> > realistically.
> >
> > Regards,
> >
> > Kevin Brace (don't respond to me directly, respond within the
> > newsgroup)
> >
> > "
>
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930 Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
>
> "They that give up essential liberty to obtain a little
> temporary safety deserve neither liberty nor safety."
> -Benjamin Franklin, 1759
Article: 35899OK. Let's try it. I think I can help concerning FPGA implementation, so if You want, send it in .pdf format to fethulah.smailbegovic@thales-ee.com. Best regards Smailbegovic Fethulah Tom St Denis schrieb: > > Hello, > > I'm a computer science student and a cryptography student. I'm working > on a symmetric cipher designed for efficient hardware implementation. > > I know quite a bit about the software side but little about the hardware > side. > > I am wondering if someone is willing to read the formal paper I am > preparing and help provide insight into details about an actual > implementation. If someone is willing to help they get to keep full > rights to their implementation [i.e they can sell, give away, etc the > design]. > > From the crypto side i've done quite a bit of analysis. My design is > based around using only simple primitive operations such as XOR and AND. > > Please email me if you want to help and I will send you a copy of the > paper in either .ps or .pdf format [you can ask for either one]. > > I'm not really looking for an exact implementation [although that would > admitedly be more useful]. Just more insight into how big the thing > would be [in either FPGA cells or custom hardware], how long the gate > delay is of the round function [i.e round function is called 16 times so > the delay of the round function is crucial] and ideas on how to speed up > the core [i.e pipelining, multiple cores, etc..] > > If anyone is really ambitious they could provide substantial details and > insight and could be a co-author of the paper for the conference. > > Thanks, > Tom
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