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> > be outdated, since Ian Page resigned from the institute. > > What became of Ian? The new Oxford university homepage mentioned, that he left in order to have more time for his company Celoxica. ER!KArticle: 35626
"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:3BC5CF71.3163801F@gmx.de... > > I mean, when the "Hello World" takes 100 Kb in C++, THIS IS REALLY CRAP. > You can't be seriously saying "Hello World" is an appropriate use of C++ methodology. Yeah - so it takes a lot to write a very small program, but large programs are easier to develop and maintain. You ever tried writing a flop in VHDL - far too much typing for the application - verilog everytime. But VHDL is a very structured language which should make larger designs easier. (lets not start he VHDL/verilog war here). A.Article: 35627
> similar, though I have given up on FPGA Express for serious work. Why ? What instead ? Design Compiler? (COST!!!!!) ER!KArticle: 35628
Andrew Brown wrote: > This is the sort of case that should be fed directly to synplicity to allow > them to improve their tools. If we don't tell them about it how can they > fix it! > > A. The problem here is that o post IPO, Synplicity's support and response time has gone to the dogs. They're spending their time on a fool's chase after the ASIC synth market. o Unlike Xilinx there is no publicly accessible ``bug list''. o I have had a case outstanding for a long time on a related issue where ``register replication'' works or doesn't depending on the type of set/reset specified. Synplicity have admitted its a bug but I cannot get the slightest info as to when it will be fixed. I think I've just given up.Article: 35629
Hello, How can I make a simple PWM Signal in VHDL ? With two counters for the high and low width ? Thanks Martin.Fischer@fzi.deArticle: 35630
thao wrote: > Hi All, > > I'm using Virilog based on Foundation ISE 3.1i from Xilinx. I have problem with the divide operand as FPGA Express can not accept variable divide (i.e. f= a/b b can not be variable) but only constant. Is there any body met this problem and can help me to solve it so that the number of occupied gates by the divide operand is minimum. > > Thao If you pause for the shortest while and think what a divider circuit means in h/w terms you will understand why its *not synthesisable!*. Verilog is not `C' The F'Exp Verilog manual describes the synthesisable subset it can accept. H/w implementation of digital arithmetic is a large subject in its own right.Article: 35631
Erik, have a look at http://www.celoxica.com/products/technical_papers/index.htm There is a language reference manual and a whole load of Apps. Notes. We downloaded the Eval version to do some algo dev. (simulation only this this Eval version), - it was fast and efficient. You get the Floating and Fixed Point libraries manual. have a look too at a site from Imperial College. Lots of cool graphics stuff http://www.doc.ic.ac.uk/~wl/papers/ "Erik Lins" <erik@lins.de> wrote in message news:<e1f3b22cbdd449172317ca554d736f16.31374@mygate.mailgate.org>... > Hello, > does anybody use this Handel-C stuff from Celoxica / Oxford University ? > Where can one find some detailed information about the language? Does a > specification exist? The info on Celoxica website is not very detailed (or my > look was not detailed enough...) and the info on Oxford homepage seem to be > outdated, since Ian Page resigned from the institute. > I need to implement some high level 3D image processing algorithms as fast as > possible and thought this Handel-C stuff could be suitable or at least more > comfortable then VHDL encoding (argl...). What about floating point? It was > mentioned, that it is supported. Do they really have floating point libs for > their compiler ? Would be cool! > > Thanks in advance, > ER!KArticle: 35632
Most people in the group seem to agree that synplify is one of the best tools available (not too hard when there are only a handful). But i'd much rather work with a tool when the company are happy to publish known issues - tells me about problems instead of making me spent months debugging their tool for them to say they knew :( Every tool on the market has bugs - we expect that, but i'd rather know the impact then pretend it isn't there. Perhaps they should pay more attention to their bread-and-butter market (FPGA) before they start trying to get the big-beef ASIC world. The only problem i've ever had personally with synplify was a sensitivity list issue. It was claiming that there was a problem when there blatently wasn't - they admitted it was an 'issue' and thats the last i heard. A. "Rick Filipkiewicz" <rick@algor.co.uk> wrote in message news:3BC6C30D.B609644D@algor.co.uk... > > The problem here is that > > o post IPO, Synplicity's support and response time has gone to the dogs. > They're spending their time on a fool's chase after the ASIC synth market. > > o Unlike Xilinx there is no publicly accessible ``bug list''. > > o I have had a case outstanding for a long time on a related issue where > ``register replication'' works or doesn't depending on the type of set/reset > specified. Synplicity have admitted its a bug but I cannot get the slightest > info as to when it will be fixed. > > I think I've just given up. > >Article: 35633
Maybe like this. I haven't tested it, though. Cnt_up is the counter for the
high part and cnt_low is the counter for the low part.
process( clk, rst )
begin
if rst = '0' then
cnt_up_max <= UP_TIME_IN_CYCLES;
cnt_low_max <= DOWN_TIME_IN_CYCLES;
pwm <= '0';
cnt_up <= 0;
cnt_low <= 0;
elsif clk'event and clk = '1' then
if cnt_up = cnt_up_max then
pwm <= '0';
cnt_up <= 0;
elsif pwm = '1' then
pwm <= '1';
cnt_up <= cnt_up + 1;
elsif cnt_low = cnt_low_max then
pwm <= '1';
cnt_low <= 0;
else
pwm <= '0';
cnt_low <= cnt_low + 1;
end if;
end if;
end process;
-- Panu
Article: 35634
Martin Fischer wrote:
>
> Hello,
>
> How can I make a simple PWM Signal in
> VHDL ? With two counters for the high
> and low width ?
For a real PWM I wolud use one counter with a comparelogic
PWM<='0' when counter>pwmlength else
'1';
bye Thomas
--
Thomas Stanka
Bosch SatCom GmbH BC/EMD4
D-71522 Backnang Tel. +49 7191 930-1690
Gerberstr. 49 Fax. +49 7191 930-21690
Zi. 10/528 Thomas.Stanka@de.bosch.com
Article: 35635
Hi all:
I have tried to compile the VHDL file in Leonardo spectrum and generate
a *.edf file and import into the Altera maxplus II and compile it create a
default symbol. every step worked without problem. But when I use the symbol
in the graphic design and try to compile it I encounter the following
problem:
Warning " I/O error can't open file *.lmf "
Error "Can't find design file 'dffe' "
I can't find any setting the *.lmf (library mapping) setting in Altera
MaxPlus II (PC version).
Could anybody help me? Thank you very much!
best regards!
email: jameshq@liv.ac.uk
Article: 35636Hello, as I read in comp.arch.embedded most i186 and i486 derivates build by AMI are discontinued. Now we got an announcement that this is the case also for a great bunch of MACH circuits produced for LATTICE in AMDs FAB 14 (which is intended to be closed). The list of devices in the PDF document spans 8 pages and contains PALCE PALLV devices, MACH1xx, MACH 2xx, MACH4xx M4-xx and M5-xxx devices! Last order is 31 dec 2001 and last delivery 31 dec 2002!!!! I have posted this using another mail server a day ago, but I havent seen it up to now. I apologize if this message is reaching you twice. Perhaps we are the only ones around using this old-fashioned programmable devices.... BTW: On http://www.latticesemi.com/products/mature/index.cfm you cannot read **anything** about this up to now (12 oct 2001, 11:20 UT)Article: 35637
With one counter (assuming that the counter rolls over to zero when the maximum value is reached): if cnt = pwm_width then pwm <= '0'; elsif cnt = 0 then pwm <= '1' else pwm <= pwm; end if; cnt <= cnt + 1; -- PanuArticle: 35638
Hi, I'm after a small (credit card size or not a lot larger) FPGA prototype board with a VirtexE or Virtex-II part, some SDRAM and I/Os. Can anyone suggest anything ? I saw that Nallatech has something like that but they are amazingly expensive. Thanks, ASArticle: 35639
Rick Filipkiewicz <rick@algor.co.uk> wrote in message > > This is very much in the spirit of the `C' vs. Assembler debate of > >long ago. > husby_d@yahoo.com (Don Husby) wrote: > It's similar, but not the same thing. For an FPGA design, there is > usually a hard performance limit. There is a fixed clock rate, and a > fixed number of resources. When the design violates those limits, it > doesn't work. Software has soft limits. It has nearly unlimited > virtual memory, and time limited only by the user's patience. A > factor of 2 performance hit doesn't break the software. > That wouldn't be embedded software then? Much more like FPGA design, hard real-time limit - very real limits on code and data space... a factor of 10% can break a highly tuned embedded software solution. Cheers, Martin -- martin.j.thompson@trw.com TRW Automotive Technical Centre, Solihull, UKArticle: 35640
Right. Did you also have an explicit global reset? If so, the synthesis
won't infer an FDR (sync reset) because it gives you an FDC (async reset)
with the global reset connected to the clear input. With an implied global
reset, it depends on what the tools did with the synthesis. If they left
the global reset in the edif netlist, then they probably also used FDCs,
and therefore excluded FDRs. The synthesis responds by implementing the
synchronous reset using an additional layer of gates between the carry
chain logic and the flip-flop. That construction is (rightly so) not
optimized out by the mapper.
The correct behavior, IMHO, would be for the synthesis to recognize an
explicit global reset, remove it from the netlist, but then put the proper
INIT=attributes on the inferred FF's to properly initialize those that are
set by global reset. The global reset has to be there for the simulation
to match the hardware. The base of this problem is that the global reset
is an invisible net (ie it is not on the primitives), which makes it
impossible to correctly simulate without artifices built around the pins
that are there.
Don Husby wrote:
> On 11 Oct 2001 19:57:59 -0700, vitaliyt@xillix.com (Vitaliy Tkachenko)
> wrote:
> >The tool does precisely what you ask for - it implements a synchronous
> >reset since R is not in the sensitivity list.
> >If you need to reset the counter asynchronously, you must use "an
> >always statement whose event list contains edge events representing
> >the clock and asynchronous control variables".
>
> Apparently, more than 1 person is under the impression that I wanted
> an asynchronous reset. What I wanted (and what I got) was a
> synchronous reset. Unfortunately, the synchronous reset was
> implemented using 57 LUTs and an extra level of logic instead of
> simply routing the reset signal to the synchronous reset input of the
> flip flops.
>
> Sorry I didn't make this clear the first time.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 35641
The timig analysis is worst case timing, which happens with high temperature and low supply voltage. In my experience,
Xilinx FPGAs will genarally work up to about 40% above the max frequency listed in the timing report in a lab environment
(watch that temperature though). I wouldn't go pushing these for something that is going to go out of the lab though.
Kevin Brace wrote:
> No one seem to make any comments about this topic, so I will chip in
> my two cents.
> OpenCores.org (http://www.opencores.org) seems to be working on a PCI
> IP core of their own (http://www.opencores.org/cores/pci/), but it
> doesn't look like it is done, and it is written in Verilog.
> According to the OpenCores.org PCI IP core project page under "Links
> to related sites and documents"
> (http://www.opencores.org/cores/pci/pci_links.shtml) a company called
> MaxLock (http://www.maxlock.com) used to offer a free PCI IP core in
> VHDL, but it seems like it no longer does.
> So, in my opinion, there is no free lunch in this world.
> From my own experience developing (still not done completely)
> a PCI IP core in Verilog using Xilinx ISE WebPack, it takes some time
> (several months working part-time on this) to do the RTL part of it.
> After the RTL part is done, you have to do Place & Route (P&R) to fit
> the design into the chip, but I think that is where things get tough.
> In 33MHz PCI, Tsu (setup time) has to be within 7ns, and Tval
> (Clock-to-Output Valid) has to be within 11ns.
> For P&R, I only used only User Constraint File (.UCF), and didn't use
> Floorplanner.
> After P&R, the input pin that had the worst Tsu was around 9ns, and
> the output pin that had the worst Tval was around 15ns.
> Those results were for Xilinx Spartan-II 150K system gates part speed
> grade -5, and if I used speed grade -6 (which is not an option in my
> case), the input pin that had the worst Tsu came down to around 7.7ns,
> and the output pin that had the worst Tval came down to around 12ns.
> Speed grade -5 violated about 75 constraints compared to about 58 for
> speed grade -6.
> So, at least in my case, my HDL-based PCI IP core cannot meet the
> timings of 33MHz PCI for Spartan-II speed grade -5 or -6 with only
> automatic P&R.
> Therefore, from my experience, just because you got a synthesizable
> PCI IP core from somewhere doesn't mean that such IP core can meet PCI
> timings.
> I used Insight Electronics Spartan-II PCI development board which has
> Xilinx Spartan-II 150K system gates part (XC2S150, speed grade -5, 208
> pin PQFP package) on it with 8MB of SDRAM on board for only $145
> without Xilinx PCI LogiCORE license.
> Very nice board considering the price, but I guess I wish they used
> speed grade -6 instead of -5.
> Although, I keep emphasizing that it is hard to meet timings
> of 33MHz PCI, and I am sure other people will say something similar,
> what I have noticed was that violation of up to 5ns doesn't seems to
> matter that much if the objective is to just to get the PCI board to
> "barely" work.
> I tested my own PCI IP core with Insight Electronics Spartan-II PCI
> development board, and the board worked fine at PCI running at 33MHz
> with both Intel 430TX chipset and SiS 5598 chipset.
> The user logic I attached to the PCI IP core was a very simple one
> that responds only to I/O cycles, and not memory cycles because I can
> access I/O ports through real or V86 mode, but I will have to do a lot
> of software writing to access a memory-mapped device that is located
> near the top of the 4GB memory space.
> Of course, the PCI IP core supported configuration cycle, too.
> The worst Tsu was I think around 10 or 11ns, and the worst Tval was
> around 15.5ns, and I think it was TRDY#.
> I do understand that a lot of people reading comp.fpga.arch will
> criticize me for writing something like, "my design worked fine even
> though I didn't meet the timings required by the specification," but
> the board somehow worked.
> I don't have the money to buy an oscilloscope or a logic analyzer, or
> know someone who will let me use them, so I really don't know what is
> going on the PCI bus.
> The most accurate data I got was from post-place & route simulation I
> did with ModelSim XE-Starter.
> I have absolutely no intention to advocate violating timing
> specification, and if someone were to sell a PCI card, that person has
> to make sure that timings are met.
> But I suppose for a student project (I am guessing), barely working
> (not meeting timings) is probably acceptable since the student never
> has enough time to complete the project.
> So, my conclusion here will be that you may have to develop
> your own PCI IP core which can take months, and it will be tough for a
> synthesizable PCI IP core without using Floorplanner to meet 33MHz PCI
> timings, but if your objective is to make it barely work somehow, then
> violating 33MHz PCI timings may not be a big issue.
>
> Regards,
>
> Kevin Brace (don't respond to me directly, respond within the
> newsgroup)
>
> "Ras Sim" <simsek@rhrk.uni-kl.de> wrote in message news:<49a92f681fea693317ee5a82213a3519.32396@mygate.mailgate.org>...
> > Hi folks!
> > I'm a student and i need a free PCI-Core wich is written in vhdl.
> > Where could I download it ?
> >
> > Greets
> > Rasit
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 35642
A comparator is relatively slow, and uses nearly as many LUTs as a
counter. For FPGAs, a better solution is to use two counters: a frame
counter to set the period (constant) and a second duty cycle counter. The
TC on the frame counter loads the duty cycle counter and sets an RS
flip-flop. The TC on the duty cycle counter (a downcounter) resets the RS
flip-flop. The TC is the carry out on both counters, so uses no additional
logic. If both counters are downcounters, you can program the period as
well as the duty cycle.
Panu H wrote:
> With one counter (assuming that the counter rolls over to zero when the
> maximum value is reached):
>
> if cnt = pwm_width then
> pwm <= '0';
> elsif cnt = 0 then
> pwm <= '1'
> else
> pwm <= pwm;
> end if;
> cnt <= cnt + 1;
>
> -- Panu
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 35643
Annapolis Micro has one too(PCMCIA). Hold onto your wallet though.
Arthur Sharp wrote:
> Hi,
>
> I'm after a small (credit card size or not a lot larger) FPGA prototype
> board
> with a VirtexE or Virtex-II part, some SDRAM and I/Os.
>
> Can anyone suggest anything ?
> I saw that Nallatech has something like that but they are amazingly
> expensive.
>
> Thanks,
>
> AS
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 35644I think synplify and all other vendors should have a simple process for improving synthesis aldorithms. If we can provide them with source - the output from their tool and a 'structural' source which is a 'better' implementation, they should ensure future versions of their tool can optomise the design. Granted this is complicated by design requirements such as GSR and other resets in this case - but if we supply simplified example code they should beable to improve their engine. To be fair to them - it's damn hard to imagine situations your engine isn't good at off the top of your head so you can improve it. Anyone from synplify out there??? A.Article: 35645
Thank you, Fred. There is a thing I have to add. In case1, in my VHDL code it says Clk2 <= not Clk1; -- period 8 ns, duty cycle 50% So the tools do know exactly about the relation of Clk2 and Clk1. They will know, that from rising edge Clk1 to rising edge Clk2 there are only 4 ns (positive duty cycle of Clk1)! This will very likely generate errors, when the tools are not able to satisfy a path delay Reg1_out to Reg3_in of less than 4 ns. How do I specify constraints for the tools or guide the tools to avoid Reg3_in changing state in the setup/hold window of Reg3 or violating its setup/hold time? Is there a MINDELAY constraint, if I accept that Reg1_out arrives at Reg3_in shortly after rising edge of Clk2? Kind regards, LeoArticle: 35646
byrne@ddc-web.com (Stephen Byrne) writes: > Hello All, > > I've inherited a design from a departed employee who was kind enough > to route all of his 23 (yes, 23!!!) FPGA clock signals on general > routing resources in an Altera FLEX 10KA. Of course, I saw this and > attempted to re-architect the clocking scheme and place all clocks on > GLOBAL buffers. Apparently, the use of a GLOBAL in 10KA requires > availability of the associated pin. Unfortunately, all 4 of the pins > associated with GLOBALs are already being used for standard I/O. I've > been told board-level mods are out of the question for the features > I'm adding to the FPGA, so swapping pins at this point is not an > option. My question is this: Does placing an internal signal on a > GLOBAL macro cause the associated pin to be driven by that internal > signal or is the pin just tri-stated and unavailable for use? > Sounds like a fun task! Unfortunately, page 33 of the 10K datasheet says: "When a global signal is driven by internal logic, the dedicated input pin that drives that global signal cannot be used. The dedicated input pin should be driven to a known logic state (such as ground) and not be allowed to float." HTH! Martin -- martin.j.thompson@trw.com TRW Automotive Technical Centre, Solihull, UKArticle: 35647
You may want to look at: Xilinx Application Brief: Pulse-Width Modulation in Xilinx Programmable Logic, application note, v0.2 (4/95) The design presented in this brief uses a register to store the desired 'mark' value, which is automatically loaded into a down counter upon reaching its terminal count. The PWM Frame Period is the product of the counter's clock period an... http://www.xilinx.com/appnotes/pwm.pdf (89632 bytes, Modified 10-03-2000) Hope this helps. Its not a VHDL design, but the block diagram on the last page should be easy to describe using VHDL. -ManfredArticle: 35648
Hi everibody, Has anyone some experience with programming MAX3000/MAX7000 devices using the free max+Plus2 baseline software from Altera under winNT? I built a ByteBlaster Programmer and a testboard, which worked fine under win2000. Now I have a machine with winNT SP6, and it won't work. I always get the 'Programming hardware not installed' message. I installed the ByteBlaster Driver. On the other side the Sentinel driver wasn't installed automatically (I heard that it is necessary for programming). I can't install it manually because the installation kit is a selfextracting .exe. I got though the sentinel driver from www.rainbow.com but it still doesnt work. My LPT is OK, I also tried it on another machine with the same OS. Is there any trick? How should the LPT settings in BIOS be? Is there a chance that it'll work better under win95? I'm allready thinking that my Programmer is broken (little chance, cause it worked fine till now). Thanks, danArticle: 35649
"Andrew Brown" <andrewbr@nortelnetworks.com> wrote > I think synplify and all other vendors should have a simple process for > improving synthesis aldorithms. If we can provide them with source - the > output from their tool and a 'structural' source which is a 'better' > implementation, they should ensure future versions of their tool can > optomise the design. Granted this is complicated by design requirements > such as GSR and other resets in this case - but if we supply simplified > example code they should beable to improve their engine. To be fair to > them - it's damn hard to imagine situations your engine isn't good at off > the top of your head so you can improve it. > > Anyone from synplify out there??? > Ken McElvain reads this list, at least sometimes...
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