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Ray Andraka <ray@andraka.com> wrote: > You want the primitives black-boxed at synthesis to keep the tools from > trying to go inside the behavoral models found in unisim. Sure; at synthesis time, compile in unisim_vcomp.vhd but not unisim_vital.vhd. Actually, I use a perl script to generate a more Synplify-friendly unisim package; it changes all of Xilinx's black box attributes to syn_black_box to reduce the number of warnings from Synplify. regards, Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 35226
No, in fact, with 3.3, i was seeing runtimes around 30 minutes, with 4.1, it took well over an hour. I'm am very dissatisfied with 4.1. I have downloaded the service pack and am still seeing bad timing results. Alan Nishioka wrote: > But did it get this result twice as fast (as advertised)? > > Alan Nishioka > alann@accom.com > > > Tom Brooks wrote: > > >> So, I installed Xilinx 4.1i software today and >> my results were much worse than with Xilinx >> 3.3i. I have a 5 ns path that was turned into >> a 7 ns path with the new software. So, I'm >> going back to 3.3i.Article: 35227
seems like alot of work. I just put the translate off pragmas around the
library delarations and put a syn_black_box atttribute on each unisim
component declaration. no warnings, no compiling libraries.
hamish@cloud.net.au wrote:
> Ray Andraka <ray@andraka.com> wrote:
> > You want the primitives black-boxed at synthesis to keep the tools from
> > trying to go inside the behavoral models found in unisim.
>
> Sure; at synthesis time, compile in unisim_vcomp.vhd but not
> unisim_vital.vhd.
>
> Actually, I use a perl script to generate a more Synplify-friendly
> unisim package; it changes all of Xilinx's black box attributes
> to syn_black_box to reduce the number of warnings from Synplify.
>
> regards,
> Hamish
> --
> Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 35228Please let us know 1) synthesis tool, 2) coding language Jens-Christian Lache wrote: > Hi! > To reduce the fanout of a tristate signal leading to 64 iobs I > tried dublicate this signal. How do I tell > the synthesis tool now not to remove my dublicated logic? > ( I tried to use a BUFG as well, but that didn't work at all) > thanks for your help, > -jc-Article: 35229
hooiwai@yahoo.com (J.Ho) wrote in message news:<cc8c8331.0109251103.1a811921@posting.google.com>... > Hi all, > > I am trying to instantiate specific elements inside a Virtex 2 slice > in verilog, such as XORG, GYMUX. Does anyone know if that is possible > with synthesis and PAR tools? > > For example, if I want a 8-input xor gate, Synplicity would just map > it across 3 LUTs. But if you look at the virtex slice, there is an > XOR gate that you can route the output of the 2 4-input LUTS to. If I > can force the tool to use those resources, then I can fit a 8-input > XOR in one slice instead of two. > > I know this is really low level, but if the hardware is there, why > waste it? This works. The trick is to also use the MUXCY to implement an xor. This coaxes the mapper to put everything in a single slice. module XXOR8(O,I); // 8-input XOR in a single slice input [7:0] I; output O; wire XRH, XRL, XRC; LUT4 #(16'h6996) xrh(XRH, I[7],I[6],I[5],I[4]); LUT3 #(8'h96) xrl(XRL, I[3],I[2],I[1]); XORCY xorx(.O(O), .CI(XRC), .LI(XRH)); MUXCY xmux(.O(XRC), .CI(~I[0]), .DI(I[0]), .S(XRL)); endmoduleArticle: 35230
John_H wrote: > Please let us know > 1) synthesis tool, > 2) coding language > > Jens-Christian Lache wrote: > > > Hi! > > To reduce the fanout of a tristate signal leading to 64 iobs I > > tried dublicate this signal. How do I tell > > the synthesis tool now not to remove my dublicated logic? > > ( I tried to use a BUFG as well, but that didn't work at all) > > thanks for your help, > > -jc- Hi! 1) foundation 3.1i 2) vhdl In the "Libraries Guide 3.3.06i -- Online" under Design Elements, BUF is a comment about this problem: .. the buffer is preserved by attaching an X (explicit) attribute to both the input and output nets of the BUF." I tried it, but it didn't work. This is the code: http://d6.design.chalmers.se/jctmp/jctmp/specache.vhd I would like to tell the synthesis tool a max fanout for the readBuffer0Pipeline1: FDCE FF and to have it generate several nets with smaller fan out automatically. Thanks a lot!!!!!!!!!!!!! -jc-Article: 35231
Martin Thompson wrote:
>
> All on a current design of mine which is 64% of LEs and ~50% of EABs
> in a FLEX10K100E.
I wonder if this is pushing the tools hard enough to
see distinct differences in compilation times?
>
> The two test systems were:
> System 1: Pentium 3, 800MHz, 512MB PC100 SDRAM
> System 2: Pentium 4, 1700MHz, 1024MB PC800 RDRAM
>
> Results, all times in hours:minutes:seconds
> Benchmark System 1 System 2 % increase {=(2-1)/1}
> PCB fanout 0:00:49 0:00:37 124%
> PCB route 0:13:08 0:12:04 108%
> HDL compile 0:02:23 0:01:43 128%
> HDL simulate 0:04:31 0:03:38 120%
> Synthesis 0:01:19 0:01:16 104%
> P&R 0:06:25 0:05:54 108%
> Mean 115%
>
> Certainly isn't much on the synth/P&R times, or my PCB routing.
> Interestingly, system 1's processor meter was pegged at 100% all
> through the routing, but system 2 dropped to 98% or 99% occasionally -
> maybe due to the CPU having to wait for data due to RAMBUS latency?
I wonder if the tools don't run much better on a P4 because
they're not optimised for it? That seems to be the general
excuse for P4 performance against Athlons running slower.
If you can, what about trying the same tests on a
1.4G Althlon with >512M DDRam?
Nial.
Article: 35232Eric, Yes, a Spartan II-E is the newest member of the Spartan family. It is the 1.8 volt core version of Spartan II. Less expensive, or cost reduced, or low cost specific application targeted, or ASIC/ASSP replacement device I believe are the politically correct descriptors. Austin Eric Smith wrote: > WebPACK 4.1 supports the Spartan-IIE family up to XC2S300E. I'd > never heard of Spartan-IIE. Is it just a cheaper Virtex-E, > as Spartan-II is a cheaper Virtex?Article: 35233
Tom Brooks wrote: > No, in fact, with 3.3, i was seeing runtimes > around 30 minutes, with 4.1, it took well over > an hour. > > I'm am very dissatisfied with 4.1. I have downloaded > the service pack and am still seeing bad timing > results. > > There's one bug mentioned in the release document where, in contrast to 3.3i just giving a warning, 4.1i gives up if it thinks it can't meet timing. There's some env flag you can set to restore the old behaviour. The second thing you might want to check is your memory useage. If the 4.1i tools follow the historical pattern they will use more memory than the previous generation; if your NT box has started paging the performance will plummet. However this result degradation seems to have happened to somebody on every early Xil s/w release. I think what happens is that each s/w release relates to increasingly big devices so their 1st priority is to claim, or even actually get, reduced run times to persuade customers that routing e.g. a 90% used XC2V6000 can be done within the span of a human's working life.Article: 35235
Austin Lesea wrote: > > Part 1.1 Type: Plain Text (text/plain) > Encoding: 7bit When ?Article: 35236
Forgotten your Latin!
I am less expensive
you are cost reduced
he/she/it is cheap
"Austin Lesea" <austin.lesea@xilinx.com> wrote in message
news:3BB21168.14127535@xilinx.com...
> Eric,
>
> Yes, a Spartan II-E is the newest member of the Spartan family. It is
> the 1.8 volt core version of Spartan II.
>
> Less expensive, or cost reduced, or low cost specific application
> targeted, or ASIC/ASSP replacement device I believe are the politically
> correct descriptors.
>
> Austin
>
> Eric Smith wrote:
>
> > WebPACK 4.1 supports the Spartan-IIE family up to XC2S300E. I'd
> > never heard of Spartan-IIE. Is it just a cheaper Virtex-E,
> > as Spartan-II is a cheaper Virtex?
>
Article: 35237"Noddy" <g9731642@campus.ru.ac.za> wrote in message news:1001422449.269338@turtle.ru.ac.za... > Hi, > > I was wondering how/if it were possible to make a distributed memory LUT > created as an RPM to be placed within the RAM memory blocks of a Spartan II. > Each LUT is 128 deep, 8 bit wide. > > adrian If you use the Coregen tool to create your memory, there is an option to generate an RPM. If you select this option, the individual distributed RAM blocks will be nicely arranged to form your larger memory. It is also possible to create your own RPM in the UCF file, but this is somewhat complicated. See this page for instructions: http://toolbox.xilinx.com/docsan/xilinx4/data/docs/lib/chap12/lib12008.htm Cheers, JamieArticle: 35238
"Jens-Christian Lache" <lache@tu-harburg.de_removeTheUnderscore> wrote in message news:3BB19589.B9651F29@tu-harburg.de_removeTheUnderscore... > I tried to dublicate the driver, but I don't know > how to tell the synthesis toll not to remove the duplicate logic) In Synplify, use the "syn_preserve" attribute. Cheers, JamieArticle: 35239
Soon, That is all I can say for now. Austin emanuel stiebler wrote: > Austin Lesea wrote: > > > > Part 1.1 Type: Plain Text (text/plain) > > Encoding: 7bit > > When ?Article: 35240
Why are the Spartan derivatives of Virtex always late? Because they represent an additional engineering challenge. They must not only offer the advanced Virtex functionality and speed, they must also have much lower manufacturing cost, to allow the aggressive pricing that Spartan is famous for. Usually, that means die shrinks, larger wafers ( 300 mm!) , more advanced fabrication methods, all to reduce the cost. That tends to takes time... Peter Alfke, Xilinx Applications ================================== Austin Lesea wrote: > Soon, > > That is all I can say for now. > > Austin > > emanuel stiebler wrote: > > > Austin Lesea wrote: > > > > > > Part 1.1 Type: Plain Text (text/plain) > > > Encoding: 7bit > > > > When ?Article: 35241
Dear recruiting team,
• you are looking for a highly-motivated digital
design/systems/CAD/FPGA/ASIC/hardware engineer?
• you need an engineer who is fascinated of
computer technology, especially parallel/vector
architectures, System-On-a-Chip and high-speed
datacommunications?
• you ask for an employee who's motivation to study
electrical engineering was generated by Seymour
Cray and his machines?
• you are searching for a creative mind combined
with strong problem solving capabilities?
• you want a new member for your team, who is
committed to excellence and success?
• you desire an open-minded person who is
programmed to reach the goal, increasing your
efficiency and pushing the limits?
Try this.....
=> http://www.asic.cc
Best regards,
Dipl.-Ing. Andreas Schmidt
P.S.: Everything is possible,
if you really want it...
Resume for Andreas Schmidt
Personal
Dipl.-Ing. Andreas Schmidt (MSEE)
Fremont, CA, USA
Phone: +1-408-768-1088, +1-510-687-1611
em@il: as@asic.cc
homesite: http://www.asic.cc
Objective
Digital Design/Systems/CAD/ASIC/FPGA/Hardware Engineer
in an innovative, industry-leading company
Summary
• Experience with VHDL/Verilog - synthesis /
simulation tools since 1994
• Gate level simulation experience since
1992
• Experience with XILINX FPGA technology and
tools since 1990
• Circuit design experience since 1984
• Computer experience since 1983
(AppleII, UCSD-Pascal)
Experience
September 2000 – present:
Blue Iguana Networks (Nuvation spin-off),
Fremont, CA, USA /
Nuvation Labs Corporation, San Jose, CA,
USA
Senior Hardware Engineer
• coauthor of the initial Blue Iguana
patent (ethernet packet processing)
• system architecture and development of
the BI technology on the target side
• development of future BI technology
Technical Lead
• design and integration of a Voice-over-
IP design for an optical network device
• mentoring, in-house education and
consulting
• CAD/EDA tool support, license
administration and support
1994 – August 2000:
Andreas Schmidt ASIC-Design, Technical
Consulting, Hard- & Software,Bochum,
Germany
Entrepreneur
• Project work concerning digital
circuit/system-design
(using Xilinx Foundation, ALDEC Active-HDL, Synplicity,
Synopsys, Mentor tools, etc...)
• computer solutions for spezialized
enviroments (medical technology)
• Authorized SUN-VAR, Apple-, Microsoft-,
Microsoft education-dealer
• System administration of heterogenous
networks (SUN/Apple/WinNT-Platforms)
• Technical Consulting concerning
networking, computer solutions,
system design
1992 – 1996: Institute Electron Devices and
Integrated Circuits,
Ruhr-Universität Bochum,
Germany
Assistant to Systemadmistrator (1 year)
• Administration of SunOS 4.1.3,
Solaris 2.4, ULTRIX, Linux, MicroVMS
• Programming of SunOS, Solaris, ULTRIX
• Installing and configuring of
development systems
Teaching Assistant: IC-design II design
course (Digital circuits) (3 years)
• Xilinx FPGA, Xilinx XACT,
Synopsys tools, SunOS 4.1.3,
SUN SPARC 10/20
• Mietec CMOS standardcells(1.2µ),
Cadence ASIC design tools, ULTRIX, DECstation5000
• MMI CMOS-Gate-Arrays,
Silvar-Lisco SL2000, MicroVMS,
MicroVAXII
1991 – 1994: NEUROTECH GmbH, Oberhausen,
Germany
Developer of Digital circuits/systems
• Design of interfaces to Hell/Linotype
Reprograhic Scanner/Recorder
using INMOS Transputer and XILINX FPGA
technology (XC3090, XC4010, XACT),
Dash, Workview
• Project management of the schematic-
converter Dash2View (Dash -> Workview)
• Developing testprograms using Pascal
Education
Ruhr-Universität Bochum, Germany:
Dipl.-Ing. Elektrotechnik 1999/2000
(MSEE degree)
Master-Thesis:
„Realization of an efficient
acquisition of measurement-data
and control of a halfbridge-current-
inverter for the operation
of a Superconducting Magnetic Energy
Storage system“.
VISA status/ US: H1B
citizenship EU: german citizen
References available on request.
Please visit my homesite:
http://www.asic.cc
for the latest news...
Article: 35242
Dear recruiting team,
• you are looking for a highly-motivated digital
design/systems/CAD/FPGA/ASIC/hardware engineer?
• you need an engineer who is fascinated of
computer technology, especially parallel/vector
architectures, System-On-a-Chip and high-speed
datacommunications?
• you ask for an employee who's motivation to study
electrical engineering was generated by Seymour
Cray and his machines?
• you are searching for a creative mind combined
with strong problem solving capabilities?
• you want a new member for your team, who is
committed to excellence and success?
• you desire an open-minded person who is
programmed to reach the goal, increasing your
efficiency and pushing the limits?
Try this.....
=> http://www.asic.cc
Best regards,
Dipl.-Ing. Andreas Schmidt
P.S.: Everything is possible,
if you really want it...
Resume for Andreas Schmidt
Personal
Dipl.-Ing. Andreas Schmidt (MSEE)
Fremont, CA, USA
Phone: +1-408-768-1088, +1-510-687-1611
em@il: as@asic.cc
homesite: http://www.asic.cc
Objective
Digital Design/Systems/CAD/ASIC/FPGA/Hardware Engineer
in an innovative, industry-leading company
Summary
• Experience with VHDL/Verilog - synthesis /
simulation tools since 1994
• Gate level simulation experience since
1992
• Experience with XILINX FPGA technology and
tools since 1990
• Circuit design experience since 1984
• Computer experience since 1983
(AppleII, UCSD-Pascal)
Experience
September 2000 – present:
Blue Iguana Networks (Nuvation spin-off),
Fremont, CA, USA /
Nuvation Labs Corporation, San Jose, CA,
USA
Senior Hardware Engineer
• coauthor of the initial Blue Iguana
patent
• system architecture and development of
the BI technology on the target side
• development of future BI technology
Technical Lead
• design and integration of a Voice-over-
IP design for an optical network device
• mentoring, in-house education and
consulting
• CAD/EDA tool support, license
administration and support
1994 – August 2000:
Andreas Schmidt ASIC-Design, Technical
Consulting, Hard- & Software,Bochum,
Germany
Entrepreneur
• Project work concerning digital
circuit/system-design
(using Xilinx Foundation, ALDEC Active-HDL, Synplicity,
Synopsys, Mentor tools, etc...)
• computer solutions for spezialized
enviroments (medical technology)
• Authorized SUN-VAR, Apple-, Microsoft-,
Microsoft education-dealer
• System administration of heterogenous
networks (SUN/Apple/WinNT-Platforms)
• Technical Consulting concerning
networking, computer solutions,
system design
1992 – 1996: Institute Electron Devices and
Integrated Circuits,
Ruhr-Universität Bochum,
Germany
Assistant to Systemadmistrator (1 year)
• Administration of SunOS 4.1.3,
Solaris 2.4, ULTRIX, Linux, MicroVMS
• Programming of SunOS, Solaris, ULTRIX
• Installing and configuring of
development systems
Teaching Assistant: IC-design II design
course (Digital circuits) (3 years)
• Xilinx FPGA, Xilinx XACT,
Synopsys tools, SunOS 4.1.3,
SUN SPARC 10/20
• Mietec CMOS standardcells(1.2µ),
Cadence ASIC design tools, ULTRIX, DECstation5000
• MMI CMOS-Gate-Arrays,
Silvar-Lisco SL2000, MicroVMS,
MicroVAXII
1991 – 1994: NEUROTECH GmbH, Oberhausen,
Germany
Developer of Digital circuits/systems
• Design of interfaces to Hell/Linotype
Reprograhic Scanner/Recorder
using INMOS Transputer and XILINX FPGA
technology (XC3090, XC4010, XACT),
Dash, Workview
• Project management of the schematic-
converter Dash2View (Dash -> Workview)
• Developing testprograms using Pascal
Education
Ruhr-Universität Bochum, Germany:
Dipl.-Ing. Elektrotechnik 1999/2000
(MSEE degree)
Master-Thesis:
„Realization of an efficient
acquisition of measurement-data
and control of a halfbridge-current-
inverter for the operation
of a Superconducting Magnetic Energy
Storage system“.
VISA status/ US: H1B
citizenship EU: german citizen
References available on request.
Please visit my homesite:
http://www.asic.cc
for the latest news...
Article: 35243I would suggest putting this big LUT in one of the available BlockRAMs, each of which is 4096 bits, organized any way you want ( and dual-ported, although that feature may not be any advantage in your case). Saves area and routing, and will most likely be faster. Remember, you can obviously use any Virtex/SpartanII 4096 bit dual-ported RAM or ROM=LUT also as two totally independent single-port 2048 bit RAMs or ROMs. Peter Alfke, Xilinx Applications ================================== Jamie Sanderson wrote: > "Noddy" <g9731642@campus.ru.ac.za> wrote in message > news:1001422449.269338@turtle.ru.ac.za... > > Hi, > > > > I was wondering how/if it were possible to make a distributed memory LUT > > created as an RPM to be placed within the RAM memory blocks of a Spartan > II. > > Each LUT is 128 deep, 8 bit wide. > > > > adrian > > If you use the Coregen tool to create your memory, there is an option to > generate an RPM. If you select this option, the individual distributed RAM > blocks will be nicely arranged to form your larger memory. > > It is also possible to create your own RPM in the UCF file, but this is > somewhat complicated. See this page for instructions: > > http://toolbox.xilinx.com/docsan/xilinx4/data/docs/lib/chap12/lib12008.htm > > Cheers, > JamieArticle: 35244
I have known this guy for the past 8 or 10 years. Let me assure you that he is an exceptionally bright and very dedicated engineer. Give him a challenge, and he will live up to it. Peter Alfke ================================== Andreas Schmidt wrote: > Dear recruiting team, > > • you are looking for a highly-motivated digital > design/systems/CAD/FPGA/ASIC/hardware engineer? > • you need an engineer who is fascinated of > computer technology, especially parallel/vector > architectures, System-On-a-Chip and high-speed > datacommunications? > • you ask for an employee who's motivation to study > electrical engineering was generated by Seymour > Cray and his machines? > • you are searching for a creative mind combined > with strong problem solving capabilities? > • you want a new member for your team, who is > committed to excellence and success? > • you desire an open-minded person who is > programmed to reach the goal, increasing your > efficiency and pushing the limits? > Try this..... > > => http://www.asic.cc > > Best regards, > Dipl.-Ing. Andreas Schmidt > > P.S.: Everything is possible, > if you really want it... > > Resume for Andreas Schmidt > > Personal > Dipl.-Ing. Andreas Schmidt (MSEE) > Fremont, CA, USA > Phone: +1-408-768-1088, +1-510-687-1611 > em@il: as@asic.cc > homesite: http://www.asic.cc > > Objective > Digital Design/Systems/CAD/ASIC/FPGA/Hardware Engineer > in an innovative, industry-leading company > > Summary > • Experience with VHDL/Verilog - synthesis / > simulation tools since 1994 > • Gate level simulation experience since > 1992 > • Experience with XILINX FPGA technology and > tools since 1990 > • Circuit design experience since 1984 > • Computer experience since 1983 > (AppleII, UCSD-Pascal) > > Experience > September 2000 ? present: > Blue Iguana Networks (Nuvation spin-off), > Fremont, CA, USA / > Nuvation Labs Corporation, San Jose, CA, > USA > > Senior Hardware Engineer > • coauthor of the initial Blue Iguana > patent (ethernet packet processing) > • system architecture and development of > the BI technology on the target side > • development of future BI technology > Technical Lead > • design and integration of a Voice-over- > IP design for an optical network device > • mentoring, in-house education and > consulting > • CAD/EDA tool support, license > administration and support > > 1994 ? August 2000: > Andreas Schmidt ASIC-Design, Technical > Consulting, Hard- & Software,Bochum, > Germany > Entrepreneur > • Project work concerning digital > circuit/system-design > (using Xilinx Foundation, ALDEC Active-HDL, Synplicity, > Synopsys, Mentor tools, etc...) > • computer solutions for spezialized > enviroments (medical technology) > • Authorized SUN-VAR, Apple-, Microsoft-, > Microsoft education-dealer > • System administration of heterogenous > networks (SUN/Apple/WinNT-Platforms) > • Technical Consulting concerning > networking, computer solutions, > system design > > 1992 ? 1996: Institute Electron Devices and > Integrated Circuits, > Ruhr-Universität Bochum, > Germany > Assistant to Systemadmistrator (1 year) > • Administration of SunOS 4.1.3, > Solaris 2.4, ULTRIX, Linux, MicroVMS > • Programming of SunOS, Solaris, ULTRIX > • Installing and configuring of > development systems > Teaching Assistant: IC-design II design > course (Digital circuits) (3 years) > • Xilinx FPGA, Xilinx XACT, > Synopsys tools, SunOS 4.1.3, > SUN SPARC 10/20 > • Mietec CMOS standardcells(1.2µ), > Cadence ASIC design tools, ULTRIX, DECstation5000 > • MMI CMOS-Gate-Arrays, > Silvar-Lisco SL2000, MicroVMS, > MicroVAXII > 1991 ? 1994: NEUROTECH GmbH, Oberhausen, > Germany > Developer of Digital circuits/systems > • Design of interfaces to Hell/Linotype > Reprograhic Scanner/Recorder > using INMOS Transputer and XILINX FPGA > technology (XC3090, XC4010, XACT), > Dash, Workview > • Project management of the schematic- > converter Dash2View (Dash -> Workview) > • Developing testprograms using Pascal > Education > Ruhr-Universität Bochum, Germany: > Dipl.-Ing. Elektrotechnik 1999/2000 > (MSEE degree) > Master-Thesis: > „Realization of an efficient > acquisition of measurement-data > and control of a halfbridge-current- > inverter for the operation > of a Superconducting Magnetic Energy > Storage system“. > > VISA status/ US: H1B > citizenship EU: german citizen > > References available on request. > > Please visit my homesite: > http://www.asic.cc > > for the latest news...Article: 35245
Austin Lesea wrote: > Soon, > > That is all I can say for now. > > Austin > > emanuel stiebler wrote: > > > Austin Lesea wrote: > > > > > > Part 1.1 Type: Plain Text (text/plain) > > > Encoding: 7bit > > > > When ? Austin, What sort of speed grades are we looking for the S2E parts in comparison with the Virtex-E -6/7/8 ?Article: 35246
Rick, I don't know. Once I see them in the lab, I'll be able to better answer that question. The FPGA Lab is the first customer, before the material is even pronounced 'ES'. So, like any other customer, our attitude is "show me." Generally speaking, Spartan pushes process towards lower power, which means less leakage, and slower transistors, as Spartan customers usually fall into the lower power/performance category. Sometimes the process is advanced enough that the speed is not much less, or even equal to the larger cousins in the advanced product line. Austin Rick Filipkiewicz wrote: > Austin Lesea wrote: > > > Soon, > > > > That is all I can say for now. > > > > Austin > > > > emanuel stiebler wrote: > > > > > Austin Lesea wrote: > > > > > > > > Part 1.1 Type: Plain Text (text/plain) > > > > Encoding: 7bit > > > > > > When ? > > Austin, > > What sort of speed grades are we looking for the S2E parts in comparison > with the Virtex-E -6/7/8 ?Article: 35247
Akshay, also have a look at their Eval product. It lasts for 30 days and gives you full simulation capabilities. http://downloads.celoxica.com/dk1eval/ Good luck. akshaymishra@rediffmail.com (Akshay) wrote in message news:<937606cb.0109252011.6aef0bf4@posting.google.com>... > Hi, > I have no idea of implentation on FPGA's but am interested to > undertake a small project. I have heard about Handle C being an easy > to use HDL (kind of if not exactly a HDL). > I plan to make a turbo encoder with Handle C. Will it be possible > using Handle C. Can you suggest a good tutorial on Handle C ? > > Thanx in advance, > Akshay Mishra. > SPANN Lab. > IIT Bombay. > URL: www.ee.iitb.ac.in/uma/~akshay/Article: 35248
Hi,
Hmm, Gated clocks.......
I have two examples where this "warning" arises,
firstly,
assign out = enable && clk;
The enable may go high while clk is high and give a shortened pulse.
secondly, this one I found recently,
wire reset = (counter ==6);
always @(.....clk or ......reset)
begin
if (reset) counter =0; else counter = counter +1;
end
The counter is reset if the output equals 6, but during transactions there
is an undetermined state so a reset may occur sxporadically !!
IMHO obvioously
Dave
"Harjo Otten" <h.otten@rohill.geen.spam.nl> wrote in message
news:a21so9.pm9.ln@svr004.rohill.nl...
> Hi,
>
> We're creating an PCI interface card that hold 8 serial ports. In my FPGA
> desing (Spartan II) I've created two (for every port) three processes. One
> that shifts data in, one that shifts data out and one that gets data from
> and sends data to the PCI core (Xilinx).
>
> These shifter processes use a clock frequency divided from the 'master
> clock'. Now here's my problem: I get a lot of gated clocks when I
implement
> it like this, but since the frequency is very low (128K max )every thing
> works fine. When I try to remove these gated clocks (I'm still not sure on
> how to do this, but usually I try to implement clock buffers) I get the
> message that there are not enough clock buffers available. I must say that
> sounds pretty logical to me since there are only 4 clockbuffers in our
> Spartan and at least 9 clocks (one for every port, and one for the master
> clock).
> Does anybody have any idea on how to remove the gated clocks in this
desing,
> or should I just ignore them ?? I've seen different comments on gated
clock
> questions lately, so I'm a bit confused.....
>
> thanx,
>
> H.
>
>
>
Article: 35249Are the I/O buffers of Spartan-IIE 5V tolerant? I know that Virtex and Spartan-II's I/O buffers are 5V tolerant, but Virtex-E isn't. Since it looks like Spartan-IIE is a derivative of Virtex-E, I guess Spartan-IIE may not support 5V tolerant I/O buffers. Regards, Kevin Brace (don't respond to me directly, respond within the newsgroup) Austin Lesea <austin.lesea@xilinx.com> wrote in message news:<3BB21168.14127535@xilinx.com>... > Eric, > > Yes, a Spartan II-E is the newest member of the Spartan family. It is > the 1.8 volt core version of Spartan II. > > Less expensive, or cost reduced, or low cost specific application > targeted, or ASIC/ASSP replacement device I believe are the politically > correct descriptors. > > Austin > > Eric Smith wrote: > > > WebPACK 4.1 supports the Spartan-IIE family up to XC2S300E. I'd > > never heard of Spartan-IIE. Is it just a cheaper Virtex-E, > > as Spartan-II is a cheaper Virtex? > > --
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