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What you are trying to do can only be done with a phase-locked-loop, or by dividing down from a very high frequency. Digital circuits do not work in the frequency domain, they work in the time domain. If you look at the 16 different period you want to generate, you see that they do not share edges. Why do you want to do this? Thre may be a simpler way to achieve you goal... Peter Alfke Ted Moreno wrote: > I want to design unusual clock dividers in a Virtex FPGA. I have a > slow clock (in couple of Hz) and I want to make 16 clock dividers <br> with equal increments. For example if the input clock in 4Hz, I want to have clock dividers from 0.25Hz, 0.5Hz, 0.75Hz, 1Hz, 1.25Hz ..........3.25Hz, 3.5Hz, 3.75Hz. > > I can use binary counter 16 for 0.25, 0.5, 1, 2 Hz clocks. What would be the best way for other freq.? > > It would be easy if I can get 50% duty cycle, but if not what are the other ways of doing this? > Any advice would be greatly appreciated > > -TedArticle: 35151
Ted Moreno schrieb: > > I want to design unusual clock dividers in a Virtex FPGA. I have a > slow clock (in couple of Hz) and I want to make 16 clock dividers <br> with equal increments. For example if the input clock in 4Hz, I want to have clock dividers from 0.25Hz, 0.5Hz, 0.75Hz, 1Hz, 1.25Hz ..........3.25Hz, 3.5Hz, 3.75Hz. > > I can use binary counter 16 for 0.25, 0.5, 1, 2 Hz clocks. What would be the best way for other freq.? > > It would be easy if I can get 50% duty cycle, but if not what are the other ways of doing this? > Any advice would be greatly appreciated Use a "high speed clock", lets say 1 MHz. Count the number of pulses between the rising edges of your super-low-speed clock. Now you can easyly calculate how much high-speed cycles it takes to create the 0.25, 0.75 .... Hz. -- MFG FalkArticle: 35152
hamish@cloud.net.au wrote > Don Husby <husby_d@yahoo.com> wrote: > > For the following code, synplify will merge the two instances > > of Shift into the same net: > > > wire [1:0] Shift /* synthesis syn_keep=1 */; > > assign Shift[0]= Sending & !Stall | !Ready; // > > assign Shift[1]= Sending & !Stall | !Ready; // Replicated > > Use syn_preserve on the signal. syn_keep won't do it, I think. > I don't know what the syntax for that is in Verilog. Unfortunately, with Synplicity this only works for registers. With Exemplar, the "preserve" attribute works on wires. Which is a good thing, because Exemplar takes way more of this kind of mapping control to make optimal designs.Article: 35153
Like Peter says, you need a PLL or an input frequency that is a higher multiple of the 4Hz you were looking at. What exactly is the application for the outputs, there may be a better way to come at it? You can readily generate any integer multiple of the input clock period though, for example you could count three input clocks keeping the output high then two more keeping the output low to get input input/5... would that be good enough? -- Posted using Nographer - News in your Browser http://www.nographer.com - free, open source, and smartArticle: 35154
"Tim" <tim@rockylogic.com.nospam.com> wrote : > "Don Husby" <husby_d@yahoo.com> wrote > It seems that what we really want is something like: > > signal a,b,c,d,x : std_logic; > x <= LUT((a and b) xor ( c and (not d))); And this would be so simple for a synthesizer to implement. > but that is beyond the language. The nearest I have managed is: > > LU1: VLut4 generic map ( ExprStr => "((I0*I1)@(I2*~I3))" ) > port map (I0=>a, I1=>b, I2=>c, I3=>d, O=>x ); I wish I could use VHDL. In addition to this, it's a lot more friendly for algorithmic instantiation of components and attributes.Article: 35155
My question is simple and rather important for me ..if i have written some Custom Primitive Model (in Generic C) that i'm using in cossap ....is it possibile to translate them directly to VHDL or Verilog using Cossap? (eg. to export them to Xilinx Foundation) or i have to write down the translation of every single Model (from generic C to v_arc file ) and then the VCG is able to mix them into a VHDL project? If not there's any tool that can help me to do this translation ?? Really Really thanks in advance Luca lukecc@tin.itArticle: 35156
A brute-force solution starts with a frequency of 90 090 Hz ( i.e. 90.090 kHz) to generate by division all frequencies from 0.25 Hz, 0.50 Hz...3.50 Hz, 3.75 Hz. So, it can be done... Peter Alfke =========== Ted Moreno wrote: > I want to design unusual clock dividers in a Virtex FPGA. I have a > slow clock (in couple of Hz) and I want to make 16 clock dividers <br> with equal increments. For example if the input clock in 4Hz, I want to have clock dividers from 0.25Hz, 0.5Hz, 0.75Hz, 1Hz, 1.25Hz ..........3.25Hz, 3.5Hz, 3.75Hz. > > I can use binary counter 16 for 0.25, 0.5, 1, 2 Hz clocks. What would be the best way for other freq.? > > It would be easy if I can get 50% duty cycle, but if not what are the other ways of doing this? > Any advice would be greatly appreciated > > -TedArticle: 35157
Peter, Thanks for the prompt response but how did get the number 90 0090 Hz? I can have a clock with this freq (90.0090 khz) but how would I generate 0.25 Hz, 0.5 Hz....3.75 Hz clocks? Can you please elaborate? -TedArticle: 35158
Either I misread this, or you guys misunderstood his question. I think he wants to be able to generate various output frequencies lower than his input at frequencies in 0.25 Hz steps. He can use direct digital synthesis for frequencies less
than half his input. A DDS is simply an accumulator that is incremented on each clock cycle. It can be visualized as a phase accumulator with the msb weighted pi, so adding phase increments on each clock brings you part of the way around the
phase circle. Using just the MSB as an output you get a square wave, although it will have jitter on is for output frequencies that are not a submultiple of the input clock. THe jitter can be reduced by increasing the input clock.
The output frequency is Fo=Fc * n/(2^k) where n is the increment value and k is the number of bits in the accumulator. For example, say he has a 4Hz input and wants 1.25 Hz out. A 4 bit accumulator will give him 0.25 resolution on the set
frequency. 1.25 is 5x 0.25, so increment it by 5. The accumulator and corresponding outputs over 16 input clock cycles will be:
0000 0
0101 0
1010 1
1111 1
0100 0
1001 1
1110 1
0011 0
1000 1
1101 1
0010 0
0111 0
1100 1
0001 0
0110 0
1011 1
0000 0
Note that in 16 clocks, the accumulator goes through 5 cycles, so the output frequency is 5/16 * 4 = 1.25 Hz. Also note that there is jitter of +/-1 cycle of the input (4Hz) clock. The increment value can only go up to half the input
frequency, beyond that the step becomes a negative phase angle, so you step the other direction through the sequence. Increasing the master clock will provide less jitter, while extending the length of the accumulator provides more frequency
resolution for the frequency selection. You'll need at least a 2x clock to get the steps higher than 2 Hz. You could use Peter's clock doubler circuit to get that 2x clock if you can't supply a 2x or greater clock. It won't help the jitter
much, but it will give you the top half of your frequency list.
Peter Alfke wrote:
> A brute-force solution starts with a frequency of 90 090 Hz ( i.e. 90.090 kHz)
> to generate by division all frequencies from 0.25 Hz, 0.50 Hz...3.50 Hz, 3.75 Hz.
> So, it can be done...
>
> Peter Alfke
> ===========
> Ted Moreno wrote:
>
> > I want to design unusual clock dividers in a Virtex FPGA. I have a
> > slow clock (in couple of Hz) and I want to make 16 clock dividers <br> with equal increments. For example if the input clock in 4Hz, I want to have clock dividers from 0.25Hz, 0.5Hz, 0.75Hz, 1Hz, 1.25Hz ..........3.25Hz, 3.5Hz, 3.75Hz.
> >
> > I can use binary counter 16 for 0.25, 0.5, 1, 2 Hz clocks. What would be the best way for other freq.?
> >
> > It would be easy if I can get 50% duty cycle, but if not what are the other ways of doing this?
> > Any advice would be greatly appreciated
> >
> > -Ted
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 35159
In synplicity you can force separate luts by copying one of the inputs to the LUT
to a vector and putting syn_keep on the vector. In VHDL this would be done as:
signal lut_out: std_logic_vector(3 downto 0);
signal signal_vector : std_logic_vector(3 downto 0);
attribute syn_keep of signal_vector:signal is true;
begin
signal_vector<=(others=> lut_in_a);
for i in 0 to 3 generate
lut_out<=<lut function(lut_in_a(i),...)>;
Don Husby wrote:
> hamish@cloud.net.au wrote
> > Don Husby <husby_d@yahoo.com> wrote:
> > > For the following code, synplify will merge the two instances
> > > of Shift into the same net:
> >
> > > wire [1:0] Shift /* synthesis syn_keep=1 */;
> > > assign Shift[0]= Sending & !Stall | !Ready; //
> > > assign Shift[1]= Sending & !Stall | !Ready; // Replicated
> >
> > Use syn_preserve on the signal. syn_keep won't do it, I think.
> > I don't know what the syntax for that is in Verilog.
>
> Unfortunately, with Synplicity this only works for registers.
> With Exemplar, the "preserve" attribute works on wires. Which
> is a good thing, because Exemplar takes way more of this kind
> of mapping control to make optimal designs.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 35160Can someone briefly explain the benefits between registered and non-registered outputs on a LUT (using Distributed Memory core). Right now I am using non-registered... could I get better performance with a registered output? The extra latency doesn't matter. thanks adrianArticle: 35161
Let me answer two questions: Why did I suggest operation from such a high starting frequency? Because it is the only way to generate the requested output frequencies 100% purely, without substantial jitter. But Ray is of course right ( as usual ) that you can generate the frequency averages much more simply. How to generate the requested frequencies from 90.090 kHz? Just divide by the appropriate integer. Use your trusty pocket calculator to find the divide ratio. 90090 divided by 3.75 = 24,024. Therefore you have to divide by 24024 to get 3.75 Hz. Takes a 15-bit binary counter... Peter Alfke ============================= Ray Andraka wrote: > Either I misread this, or you guys misunderstood his question. I think he wants to be able to generate various output frequencies lower than his input at frequencies in 0.25 Hz steps. He can use direct digital synthesis for frequencies less > than half his input. A DDS is simply an accumulator that is incremented on each clock cycle. It can be visualized as a phase accumulator with the msb weighted pi, so adding phase increments on each clock brings you part of the way around the > phase circle. Using just the MSB as an output you get a square wave, although it will have jitter on is for output frequencies that are not a submultiple of the input clock. THe jitter can be reduced by increasing the input clock. > > The output frequency is Fo=Fc * n/(2^k) where n is the increment value and k is the number of bits in the accumulator. For example, say he has a 4Hz input and wants 1.25 Hz out. A 4 bit accumulator will give him 0.25 resolution on the set > frequency. 1.25 is 5x 0.25, so increment it by 5. The accumulator and corresponding outputs over 16 input clock cycles will be: > > 0000 0 > 0101 0 > 1010 1 > 1111 1 > 0100 0 > 1001 1 > 1110 1 > 0011 0 > 1000 1 > 1101 1 > 0010 0 > 0111 0 > 1100 1 > 0001 0 > 0110 0 > 1011 1 > 0000 0 > > Note that in 16 clocks, the accumulator goes through 5 cycles, so the output frequency is 5/16 * 4 = 1.25 Hz. Also note that there is jitter of +/-1 cycle of the input (4Hz) clock. The increment value can only go up to half the input > frequency, beyond that the step becomes a negative phase angle, so you step the other direction through the sequence. Increasing the master clock will provide less jitter, while extending the length of the accumulator provides more frequency > resolution for the frequency selection. You'll need at least a 2x clock to get the steps higher than 2 Hz. You could use Peter's clock doubler circuit to get that 2x clock if you can't supply a 2x or greater clock. It won't help the jitter > much, but it will give you the top half of your frequency list. > > Peter Alfke wrote: > > > A brute-force solution starts with a frequency of 90 090 Hz ( i.e. 90.090 kHz) > > to generate by division all frequencies from 0.25 Hz, 0.50 Hz...3.50 Hz, 3.75 Hz. > > So, it can be done... > > > > Peter Alfke > > =========== > > Ted Moreno wrote: > > > > > I want to design unusual clock dividers in a Virtex FPGA. I have a > > > slow clock (in couple of Hz) and I want to make 16 clock dividers <br> with equal increments. For example if the input clock in 4Hz, I want to have clock dividers from 0.25Hz, 0.5Hz, 0.75Hz, 1Hz, 1.25Hz ..........3.25Hz, 3.5Hz, 3.75Hz. > > > > > > I can use binary counter 16 for 0.25, 0.5, 1, 2 Hz clocks. What would be the best way for other freq.? > > > > > > It would be easy if I can get 50% duty cycle, but if not what are the other ways of doing this? > > > Any advice would be greatly appreciated > > > > > > -Ted > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759Article: 35162
If you build a synchronous, clocked design, you will implement combinatorial logic between registers. The longer the combinatorial delay, the lower the clock frequency. So, for highest throughput, you want to keep the LUT delay as short as possible, and use "pipeline" registers generously. High performance, but longer latency. If you don't use the CLB register, you have to add the longest series of LUT delays to figure out the max clock rate. Peter Alfke ================================ Noddy wrote: > Can someone briefly explain the benefits between registered and > non-registered outputs on a LUT (using Distributed Memory core). Right now I > am using non-registered... could I get better performance with a registered > output? The extra latency doesn't matter. > > thanks > adrianArticle: 35163
Peter Alfke <peter.alfke@xilinx.com> writes: > How to generate the requested frequencies from 90.090 kHz? Just > divide by the appropriate integer. Use your trusty pocket calculator > to find the divide ratio. 90090 divided by 3.75 = 24,024. Therefore > you have to divide by 24024 to get 3.75 Hz. Takes a 15-bit binary > counter... I think the question was more a matter of "how did you pick the value 90.090 kHz from the numbers in the original problem". Without thinking too hard about it or getting out my calculator, I suspect that you computed the least common multiple of the desired output frequencies.Article: 35165
Eric Smith wrote: > I think the question was more a matter of "how did you pick the > value 90.090 kHz from the numbers in the original problem". > > Without thinking too hard about it or getting out my calculator, > I suspect that you computed the least common multiple of the > desired output frequencies. Yes. Seems like those high-school hours were not entirely worthless. Peter > >Article: 35166
... and as usual Xilinx' attempt at super-fancy Javascript works poorly
in my browser. Fortunately it is possible to download it without
using their download manager. From Linux, this command will download
everything:
wget http://username:password@www.xilinx.com/webpack/41wp0/{WebPACK,MXE}_41wp00_full_install.exe
Obviously you'll have to register and put your own username and password in the
command.
Too bad they still don't have a version that runs on Linux. These days
Xilinx software is the only thing keeping me from abandoning Windows
entirely. Maybe Microsoft is giving them a kickback? :-)
Article: 35167WebPACK 4.1 supports the Spartan-IIE family up to XC2S300E. I'd never heard of Spartan-IIE. Is it just a cheaper Virtex-E, as Spartan-II is a cheaper Virtex?Article: 35168
I need to do some version specific stuff with fe_shell, and I'd like to maintain only one version of our synthesis script and do conditional execution via Tcl based on the version of foundation express I'm using at runtime. I couldn't find a variable I could get this from , and the lack of good docs from Xilinx on fe_shell is really annoying. Do any of you wiser souls know the tcl magic for this?Article: 35169
As for the scaling: If you want absolutely no overflow you can scale the coefficients so that their magnitude sum is one. For interpolating filters, you would scale so that largest sum of the coefficients of one phase is 1. That is, you multiply all the coefficients by the inverse of the largest sum of the magnitude of the coefficients from one phase of the polyphase filter. Then the magnitude of the filter output can be no larger than 1. This case would occur when each positive coefficient is multiplied by a sample of 1.0 and each negative coefficient is multiplied by a sample of -1.0. This gets you the best dynamic range without overflowing. Since this case happens rarely, usually you can, with little reduction in quality, scale the coefficients again by some constant like 1/sqrt(2). In this case, there will be an occasional overflow, so you will need a "clipper" which clips the filter output to 1 (actually slightly less than 1) or -1 if the filter overflows. This gives you more dynamic range at the expense of occasional clipping. This also gives you a better peak-to-average ratio, which allows you to operate more within the linear range of a linear filter. So sometimes it's a wash: the clipping adds noise, but allows you to work more within the linear range of the filter, reducing noise. The clipper might be a pain to implement because you have to check each adder in the FIR for overflow (the sign bit of the adder output is not the same as the sign of either input). I think there are also soft clippers, which squash the larger samples like a voice compander, reducing noise a bit. If you clip too hard you can get spurs and exceed your mask. -Kevin "Antonio" <dottavio@ised.it> wrote in message news:fb35ea96.0109232317.5650b3b6@posting.google.com... > Good Morning > I'm developing a QPSK passband modulator for my thesis, on it I use a > 37 taps polyphase SRRC filter for each branch of the transmission > > delay = 3 ; > roll_off = 0.35 ; > input_rate_SRRC = 27.5e6 ; > output_rate_SRRC = 165e6 ; > num_fir = rcosine( input_rate_SRRC , output_rate_SRRC, 'fir/sqrt', > roll_off, delay); > data_out_SRRC_tx_I = rcosflt(data_in_SRRC_tx_I, input_rate_SRRC , > output_rate_SRRC , 'filter' , num_fir); > data_out_SRRC_tx_Q = rcosflt(data_in_SRRC_tx_Q, input_rate_SRRC , > output_rate_SRRC , 'filter' , num_fir); > > > on the receiving pat I use the same 37 taps SRRC filter but without > interpolate nor decimate, simply > data_out_SRRC_rx_I = filter(num_fir, 1 , data_in_SRRC_rx_I); > data_out_SRRC_rx_Q = filter(num_fir, 1 , data_in_SRRC_rx_Q); > > > My problem is that when I compare the simbol transmitted to the symbol > received, the first symbols are not good, > this is due to the answers of the filters, looking at the two sequence > I can see that the shift between them is > of 10 bits so 5 symbols for a QPSK modulator but how I can determine > this in a not empirical way ?? > > > > By the way another question, with this code matlab produce a 37 taps > filter that is not well suited for an FPGA > implementation of the polyphase filter, it is better to have 36 for an > SRRC that have to interpolate 6 otherwise > I've to put inside other coefficients of value zero until I arrive to > a total number of taps that is multiple of 6. > How I can do it with Matlab ?? > > I also try to use systolix to design this filter and it seems OK, the > only problem is that the coefficients are > between about -0.2 and +0.2 , in my design I use 2's complement, 1 bit > for the sign and 11 bits for the fractional part, > no bit for the integer part, to better use this range can I scale the > coefficients ?? This could give me some problem ?? > > > > Thanks in any case ... > > Antonio D'OttavioArticle: 35170
On Mon, 24 Sep 2001 19:42:41 GMT, Ray Andraka <ray@andraka.com> wrote: >Either I misread this, or you guys misunderstood his question. I think he wants to be able to generate various output frequencies lower than his input at frequencies in 0.25 Hz steps. He can use direct digital synthesis for frequencies less >than half his input. A DDS is simply an accumulator that is incremented on each clock cycle. It can be visualized as a phase accumulator with the msb weighted pi, so adding phase increments on each clock brings you part of the way around the >phase circle. Using just the MSB as an output you get a square wave, although it will have jitter on is for output frequencies that are not a submultiple of the input clock. THe jitter can be reduced by increasing the input clock. > >The output frequency is Fo=Fc * n/(2^k) where n is the increment value and k is the number of bits in the accumulator. For example, say he has a 4Hz input and wants 1.25 Hz out. A 4 bit accumulator will give him 0.25 resolution on the set >frequency. 1.25 is 5x 0.25, so increment it by 5. The accumulator and corresponding outputs over 16 input clock cycles will be: > >0000 0 >0101 0 >1010 1 >1111 1 >0100 0 >1001 1 >1110 1 >0011 0 >1000 1 >1101 1 >0010 0 >0111 0 >1100 1 >0001 0 >0110 0 >1011 1 >0000 0 > >Note that in 16 clocks, the accumulator goes through 5 cycles, so the output frequency is 5/16 * 4 = 1.25 Hz. Also note that there is jitter of +/-1 cycle of the input (4Hz) clock. The increment value can only go up to half the input >frequency, beyond that the step becomes a negative phase angle, so you step the other direction through the sequence. Increasing the master clock will provide less jitter, while extending the length of the accumulator provides more frequency >resolution for the frequency selection. You'll need at least a 2x clock to get the steps higher than 2 Hz. You could use Peter's clock doubler circuit to get that 2x clock if you can't supply a 2x or greater clock. It won't help the jitter >much, but it will give you the top half of your frequency list. Here are the jitter figures from simulation: For an 8Hz clock, using the standard NCO that Ray so eloquently described: fout jitter 0.250 0 ms 0.500 0 ms 0.750 83.333334 ms 1.000 0 ms 1.250 100 ms 1.500 83.333333 ms 1.750 107.142858 ms 2.000 0 ms 2.250 111.111112 ms 2.500 100 ms 2.750 113.636363 ms 3.000 83.333334 ms 3.250 115.384615 ms 3.500 107.142857 ms 3.750 116.666666 ms 4.000 0 ms Note that in no case does the jitter actually get as high as one period of the input clock. For a 16Hz clock, the jitter amplitude is halved: fout jitter 0.250 0 ms 0.500 0 ms 0.750 41.666667 ms 1.000 0 ms 1.250 50 ms 1.500 41.666666 ms 1.750 53.571429 ms 2.000 0 ms 2.250 55.555556 ms 2.500 50 ms 2.750 56.818181 ms 3.000 41.666667 ms 3.250 57.692307 ms 3.500 53.571428 ms 3.750 58.333333 ms 4.000 0 ms A 1MHz clock would take way too long to simulate on my little laptop, but you can be pretty sure that the jitter will be about 1us. Regards, Allan > >Peter Alfke wrote: > >> A brute-force solution starts with a frequency of 90 090 Hz ( i.e. 90.090 kHz) >> to generate by division all frequencies from 0.25 Hz, 0.50 Hz...3.50 Hz, 3.75 Hz. >> So, it can be done... >> >> Peter Alfke >> =========== >> Ted Moreno wrote: >> >> > I want to design unusual clock dividers in a Virtex FPGA. I have a >> > slow clock (in couple of Hz) and I want to make 16 clock dividers <br> with equal increments. For example if the input clock in 4Hz, I want to have clock dividers from 0.25Hz, 0.5Hz, 0.75Hz, 1Hz, 1.25Hz ..........3.25Hz, 3.5Hz, 3.75Hz. >> > >> > I can use binary counter 16 for 0.25, 0.5, 1, 2 Hz clocks. What would be the best way for other freq.? >> > >> > It would be easy if I can get 50% duty cycle, but if not what are the other ways of doing this? >> > Any advice would be greatly appreciated >> > >> > -Ted > >-- >--Ray Andraka, P.E. >President, the Andraka Consulting Group, Inc. >401/884-7930 Fax 401/884-7950 >email ray@andraka.com >http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 35171
Hell all,
I got a lot of hold time violations when I finished P&R with
QuartusII1.1 .
The major reason to cause so many timing violations is that I have too
many clocks in this design but APEX20KE series only afford 8 (4
dedicate clock and 4 global route). I've already tried hard to reduce
the number of clocks but it's impossible to reduce them less than 8. I
really need help to resolve this problem.
Two methods in ASIC flow will fix hold time violation, but I don't
know if FPGA tools support these functions.
1. Under the ASIC design flow, when there is a hold violation, we can
add some "delay cells" in the data path to balance the data skew and
data path delay. Does QuartusII support this function? ( Automatic add
delay cells in the data path which cause hold time violations. )
2. Another method in ASIC design flow to avoid hold time violations is
to set clock uncertainty. Are there any FPGA synthesis tools support
this feature?
(Set the clock uncertainty so that the synthesis tool will add delay
cells in the data path to avoid possible hold time violations)
Any help is greatly appreciated.
Ivor
Article: 35172
_______________________________________________________________________
Call For Papers
The 9th Reconfigurable Architectures Workshop (RAW 2002)
Fort Lauderdale, Florida, April 15, 2002
Workshop Web Page: http://www.ee.lsu.edu/vaidy/raw02/
_______________________________________________________________________
The 9th Reconfigurable Architectures Workshop (RAW 2002) is associated
with the 16th Annual International Parallel & Distributed Processing
Symposium (IPDPS 2002) and is sponsored by the IEEE Computers Society's
Technical Committee on Parallel Processing. It will be held at the
Marriot Marina, Fort Lauderdale, Florida, on April 15, 2002. RAW 2002 is
one of the major meetings for researchers to present ideas, results, and
on-going research on both theoretical and industrial/practical advances
in
Reconfigurable Computing.
Main Focus of the Workshop:
Run-Time Reconfiguration: Foundations, Algorithms, Tools
Reconfiguration of circuitry at runtime, also called run-time
reconfiguration (RTR), is a new dimension in computing that blurs
traditional boundaries between hardware and software components. As a
consequence, neither the systems architectures nor the hardware/software
design methodologies and tools that are available today can fully reveal
or
exploit the possibilities created by this new computing paradigm.
Algorithms
and systems designers alike are challenged to harness the potential of
innovative devices for the design and application of effective
reconfiguration strategies. This goal requires design tools based on
robust, formal descriptions of the concepts underlying reconfiguration
in
order to gain independence from the frequently changing properties of
commercially available devices. An appropriate combination of knowledge
about the foundations of dynamic reconfiguration, the various models of
reconfigurable computing, efficient algorithms, and the tools to support
the
design and implementation of run-time reconfigurable systems is
required.
RAW 2002 aims to provide a forum for creative and productive interaction
between these disciplines.
Topics of Interest:
Authors are invited to submit manuscripts of original unpublished
research
in all areas of run-time reconfiguration (foundations, devices, systems,
algorithms, software tools, and applications). The topics of interest
include, but are not limited to:
Reconfigurable Computing Systems & Applications Tools
* Models (R-Mesh, * Devices and *
High level design
Optical models,
reconfiguration methods
etc.)
techniques * Compilation
* RTR architectures * Dynamic instruction
techniques
* Algorithmic set
architectures * Virtual machine
techniques * Adaptive
and support
* Bounds and evolvable hardware *
Methodologies and
complexity issues * Wireless
and tools
* Mapping parallel distributed systems
algorithms * Mobile circuitry
* Fault tolerance * Systems support
* Configurable
resource management
Submission Guidelines:
Authors should submit an electronic version of their work for review to
Oliver Diessel, University of New South Wales, Australia,
(odiessel@cse.unsw.edu.au).
All manuscripts will be reviewed by at least three members of the
program
committee. Submissions should be a complete manuscript (not to exceed 8
pages of single spaced text, including figures and tables) or, in
special
cases, may be a summary of relevant work. Submissions should be in
Postscript (level 2) format. Authors should make sure that the
submission
can be viewed using ghostscript and will print on a Postscript printer
that
uses standard letter size paper (8.5" x 11"). Submissions must be
received
by October 19, 2001.
IEEE CS Press will publish the IPDPS symposium and workshop abstracts as
a
printed volume. The complete symposium and workshop proceedings will
also be
published by IEEE CS Press as a CD-ROM disk.
Important Dates:
* Manuscript due October 19, 2001
* Notification of acceptance/rejection December 5, 2001
* Final version due January 18, 2002
Organization:
Workshop Chair: Gordon Brebner, University of Edinburgh (UK)
gordon@dcs.ed.ac.uk
Steering Chair: Viktor K. Prasanna, University of Southern California
(USA)
prasanna@ganges.usc.edu
Program Chair: Oliver Diessel, University of New South Wales
(Australia)
odiessel@cse.unsw.edu.au
Publicity Chair: Ramachandran Vaidyanathan, Louisiana State University
(USA)
vaidy@ee.lsu.edu
Program Committee:
* Jeff Arnold, Adaptive Silicon Inc. (USA)
* Peter Athanas, Virginia Tech (USA)
* Gordon Brebner, Univ. Edinburgh (UK)
* Carl Ebeling, Univ. Washington (USA)
* Hossam ElGindy, Univ. New South Wales (Australia)
* Reiner Hartenstein, Univ. Kaiserslautern (Germany)
* Brad Hutchings, Brigham Young Univ. (USA)
* Mohammed Khalid, Quickturn Design Systems (USA)
* Hyoung Joong Kim, Kangwon National Univ. (Korea)
* Rainer Kress, Infineon Technologies (Germany)
* Ron Lin, SUNY Geneseo (USA)
* Wayne Luk, Imperial College (UK)
* Patrick Lysaght, Univ. Strathclyde (UK)
* Margaret Marek-Sadowska, Univ. California, Santa Barbara (USA)
* Liam Marnane, Univ. College Cork (Ireland)
* John McHenry, National Security Agency (USA)
* Alessandro Mei, Univ. Rome "La Sapienza" (Italy)
* Martin Middendorf, Univ. Karlsruhe (Germany)
* George Milne, Univ. Western Australia (Australia)
* Koji Nakano, Japan Advanced Inst. of Science & Tech. (Japan)
* Bernard Pottier, Univ. Bretagne Occidentale (France)
* Hartmut Schmeck, Univ. Karlsruhe (Germany)
* Juergen Teich, Univ. Paderborn (Germany)
* Jerry Trahan, Louisiana State Univ. (USA)
* Ramachandran Vaidyanathan, Louisiana State Univ. (USA)
* Peixin Zhong, Lucent (USA)
Workshop Web Page: http://www.ee.lsu.edu/vaidy/raw02/
Article: 35173Good morning everybody, I'm developping a PC card with 2x XC2V1000 (optionally XC2V3000) on it. I extrapolated the results of an old run of XILINXs power estimator excel sheet which results in a rather high current for the 1.5V core supply of roughly 16A (8Amps each). If anybody has experience on powering these devices, could you confirm such a high current consumption? Thanks a lot. JonasArticle: 35174
You should enable the Global Signal option for your clock signals. You can also insert some buffers in order to add delay in your clock path. jb "Ivor" <ivor@icplus.com.tw> a écrit dans le message news: b60e531a.0109242157.1d326806@posting.google.com... > Hell all, > I got a lot of hold time violations when I finished P&R with > QuartusII1.1 . > The major reason to cause so many timing violations is that I have too > many clocks in this design but APEX20KE series only afford 8 (4 > dedicate clock and 4 global route). I've already tried hard to reduce > the number of clocks but it's impossible to reduce them less than 8. I > really need help to resolve this problem. > > > Two methods in ASIC flow will fix hold time violation, but I don't > know if FPGA tools support these functions. > 1. Under the ASIC design flow, when there is a hold violation, we can > add some "delay cells" in the data path to balance the data skew and > data path delay. Does QuartusII support this function? ( Automatic add > delay cells in the data path which cause hold time violations. ) > > 2. Another method in ASIC design flow to avoid hold time violations is > to set clock uncertainty. Are there any FPGA synthesis tools support > this feature? > (Set the clock uncertainty so that the synthesis tool will add delay > cells in the data path to avoid possible hold time violations) > > Any help is greatly appreciated. > > Ivor
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