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On Mon, 19 Jan 2004 09:12:42 GMT, "Jean Nicolle"
<j.nicolle@sbcglobal.net> wrote:
>That makes sense.
>Terminating the receiver is just a matter of putting a resistor across the
>wire pair.
>
>Now, the question is, how to terminate the transmitter?
>
>If I assume cat5 cables (100ohms differential impedance?), my first thought
>is to put two 50ohms series resistors on the transmitter side. The downside
>is, it is going to cut in half the incident wave.
>Any better way?
14.3.1.2.2 indicates that the return loss has to be at least 15dB
(between 5.0MHz and 10MHz).
Most approaches for driving terminated lines with good output return
loss will lose half the output power in the driver. There's not too
much you can do about this if using an FPGA.
You don't say whether the FPGA I/O is powered from 2.5V or 3.3V. This
makes a difference.
|
FPGA|
| R1 .---o
| ___ TD+ | |
|----------|___|-------. ,-----------' .-.100 ohm
| )|( | |test load
| ___ )|( TD- | |
|----------|___|-------' '-----------. '-'
| 1:N | |
| R2 .---o
|
|
|
created by Andy´s ASCII-Circuit v1.24.140803 Beta www.tech-chat.de
For best output return loss, (R1 + R2) * N^2 = 100 ohm.
(You should include the output resistance of the FPGA drivers in R1
and R2 - see the IBIS models.)
The (single sided, not peak to peak) output amplitude will be
Vcc * (100ohm / (100 ohm + (R1 + R2)/N))
E.g. Vcc = 3.3.V,
N = 1 (i.e. it's a 1:1 transformer, a very common type)
then to get the right output amplitude, R1 and R2 will need to be at
most 25 ohms each (including the FPGA output resistance).
This gives an output impedance of 50 ohms though, which is equivalent
to a return loss of only about 9.5dB.
Hmmm. The only thing to do (apart from violating the specs) is to use
a stepup transformer. This is actually what most PHYs do (more or
less).
A 1:2 transformer would work well with a Vcc of 2.5V. R1 and R2 would
still be 25ohm, but the output amplitude would be 2.5V, with a good
return loss.
However, the current in the FPGA output pins would be 50mA. This
probably isn't practical without using multiple drivers in parallel.
A 1:1.3 transformer would work well with a Vcc of 3.3V. R1 and R2
would need to be about 30 ohm, and the FPGA output current would come
down to about 32mA.
Note that 14.3.1.2.1 says "[the] transmitter shall provide
equalization such that the output waveform shall fall within the
template shown in Figure 14–9 for all data sequences"
as well as
"any harmonic measured on the TD circuit shall be at least 27 dB below
the fundamental."
There is no simple way of providing equalisation when using such a
simple driver.
Regards,
Allan.
Article: 65026"hamilton" <hamilton@deminsional.com> wrote in message news:400b2ce4$1_1@omega.dimensional.com... > I have found a tube of these AMD parts from on old project. > AMD no longer manufactures these parts. Does anyone know who > picked up these parts from AMD ? AMD spun-out its PLD lines as Vantis. Before too long, Vantis was taken over by Lattice. As far as I know, Lattice still offers these parts (or something very similar). > I am also looking for a simple programmer for these parts. > I have found $500+ programmers out on the net, but I would like > to keep it cheap. ISTR that the programming algorithm for PALCE devices was reasonably straightforward, so you could probably do something home-grown - maybe using some of your newly- found PALs in its logic :-) But in general, programmers for PLDs were expensive with good reason - getting the programming algorithms right is pretty tough. You may find it's better to junk the old parts and get some newer Lattice in-system=programmable (ISP) parts, which can be programmed much more simply and cheaply using a simple download cable that you can easily build from information in their data sheets. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 65027
> > A friend told me that the 50,000 piece price on the slowest XC3S400 in > the FG456 package would be around $20. The press releases are talking > about the "smallest" package and 250,000 quantities giving a price > around $5. I don't know what the "smallest" package is, but I would > like to meet the guy who is getting the $5 price. And from my last insight quote for the xc3s200 the smallest package is three Euro more expensive than the FT256 (VQ100 is smaller both in dimension and in pincount than FT256) Kolja SulimmaArticle: 65028
FYI, The Altera DMA block has bugs if "Use ESB/EABs" is selected in its GUI on Stratix. I don't know about other architectures. The default option works properly in this scenario. I'm guessing ESBs have different timing than TriMatrix and therefore FIFO draining does not work properly. -- Pete > Hi, > > I have a very simple Stratix SOPC system: An Avalon DMA block whose > read and write masters both connect to a MegaRAM. The DMA control bus > is mastered by Nios. > > My DMA blocks registers are set up as: > > np_dmareadaddress = 0x10000; // base of MegaRAM > np_dmawriteaddress = 0x11000; // 1024 words in > np_dmalength = 32; // xfer 32 bytes > np_dmacontrol = 0x8C; // do 32-bit xfer, end when length=0 and GO! > > I verified the registers by reading them back, and the status reg > indicates operation just as I would expect. > > When I simulate this system in Active-HDL everything works as > expected. On actual hardware, unfortunately, I must always run the DMA > operation twice to get the right data into MegaRAM - the first time > always writes data to the destination address that is from the > PREVIOUS time that I ran the DMA operation. It always write 4 words of > old data; after these 4 words, the written data is current and > correct. > > The only way I can rationalize this is that the FIFO inside the DMA > block is writing data to the destination before the source data has > been read into it. > > My questions are: > - Can I use the Avalon DMA block to DMA to/from MegaRAMs? Or do the > source and/or destination resources have to be streaming slaves? (ie. > can a streaming master such as DMA work with non-streaming slaves such > as MegaRAMs? > - Why does simulation give me the correct results? Does it have to do > with me running on Stratix, whereas Active-HDL may assume I'm running > on Apex, etc? > - Is there a bug with the DMA block, or am I doing something stupid?Article: 65029
"Amontec Team, Laurent Gauch" <laurent.gauch@amontecDELETEALLCAPS.com> wrote in message news:<3FF94EAF.7070305@amontecDELETEALLCAPS.com>... > chi wrote: > > Hello, > > > > > > I need to program CoolRunner CPLD using an embedded controller. How to > > set the CPLD registers to work in the ISP mode? > > > > Please explain how to do. > > > > Regards, > > Chi > just put PORT_EN pin to '1' ! > > Laurent Gauch > www.amontec.com 1. In My design PORT_EN pin is connected to ground. Is it possible to enable ISP mode through instruction ISPEN command? thanks and regards ChiArticle: 65030
In XAPP058.pdf(v3.0) in page 23 CoolRunner Programming Algorithm is given. This programming algorithm doesn't match with code in eisp_pc.zip file. Please explain.Article: 65031
Hi all, Has anybody tried Chipscope Pro with a MicroBlaze based system? I am using JTAG-Uart for debugging purposes and now I want to use ChipScope Pro at the same time, but when I try to implement it generates an error with BSCAN. I know that JTAG-Uart uses a BSCAN and ChipScope also needs another one. If I take out the JTAG-Uart from the design it works. So is there any possible solution to this? I am using a 1000 million gate Virtex II FPGA. Any help would be welcome. Thanks in advance, Arkaitz.Article: 65032
Mike Treseler <mike.treseler@flukenetworks.com> wrote in message news:<400AEBF5.6030006@flukenetworks.com>... > Nick Suttora wrote: > > > the simulation time required, however it still takes about 1 hour per > > millisecond of simulation time. Other than getting a faster computer > > are there any other things that can be done to reduce the simulation > > time? I have already removed high frequency signals (clocks) from the > > simulator waveform window and used variables where possible. > > > Consider siming your source level before gate level. > That's about ten times faster. > > -- Mike Treseler I am using a core in the part which was delivered as a gate level netlist so I have no choice.Article: 65033
Hi, I am trying to simulate a receiver using the Xilinx Virtex 2 Pro Rocket IO transceiver, but after the reset, the LOSS_OF_SYNC signal goes high and stays there. I use the 8b/10b decoding but even after detecting a K character, the transceiver does not get byte synchronized with the incoming serial stream. Is there any other logic I will need to achieve the sync ? Does anyone have any examples ? Thanks in advance for any help. Cheers, AdarshArticle: 65034
Doesn't Xilinx need to pay a per-seat royalty for the libraries that provide the capabilities you're lamenting? Lets all get something free from someone who has to pay for it !!! "Kelvin @ SG" <kelvin8157@hotmail.com> wrote in message news:bucl4a$vm4$1@reader01.singnet.com.sg... > sighhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh :-( > > > "Stephen Williams" <spamtrap@icarus.com> wrote in message > news:a36f$40086bdb$40695902$18612@msgid.meganewsservers.com... > > Kelvin @ SG wrote: > > > Hi, there: > > > > > > I am using ise WebPack for learning purpose. I am learning modular > design > > > while > > > I can't live without the FPGA Editor...even if a viewer is okie... > > > > > > I used ISE w6.1.03, but there is no editor on it. > > > > > > May I know which version has this functionality on it? > > > > No versions of WebPack have FPGA Editor. You need a for-money > > version to get it. > > > > (My other gripe: No versions of WebPack support Linux native. Grumble.) > > > > > > -- > > Steve Williams "The woods are lovely, dark and deep. > > steve at icarus.com But I have promises to keep, > > http://www.icarus.com and lines to code before I sleep, > > http://www.picturel.com And lines to code before I sleep." > > > >Article: 65035
Hello, I am relatively new to Xilinx and VHDL programming for that matter. I have currently concluded certain sections of my final design, however I need to test it by imposing signals at inputs to this design. Currently I have had to design vhdl parts that would generate these signals however I would like to these to not be synthesised with the rest of the design. Is there any method by which I can impose more complex signals on the testbench or modelsim? Thanks CArticle: 65036
Hi everyone, 1. Where can i find a free Version of Quartus on Linux OS. I would like to test it. 2. is there any chance to apply QUIP's softwares on architectures that are other than Altera's devices.( Academic tools SIS+VPR allow this) Thanks in advance --Article: 65038
Just to confirm it officially: In frequency synthesis mode, M/D is done as a combined mathematical operation. Therefore it is irrelevant that the multiplication by itself might exceed the max frequency. I remember publishing this in several places, but cannot find it right now. It is one of the major nice features of the DCM. Peter Alfke, Xilinx Applications ================ Antti Lukats wrote: > > " > RTFM, RTFM, RTFM > there is somewhere a notice in datasheets that the DCM can be used > in such situation where the virtual CLK is way beyound operating > frequency, the DCM will still work. > > So you should be safe, using the DCM with those parameters as given. > >Article: 65039
chuk wrote: > Hello, I am relatively new to Xilinx and VHDL programming for that > matter. I have currently concluded certain sections of my final > design, however I need to test it by imposing signals at inputs to > this design. Currently I have had to design vhdl parts that would > generate these signals however I would like to these to not be > synthesised with the rest of the design. Is there any method by which > I can impose more complex signals on the testbench or modelsim? Modelsim is your simulator. A testbench is a text file: a vhdl architecture. containing an instance of your uut entity code. A testbench process can generate any waveform you like, either algorithmically or from a table. Poke around in here to clarify your question. http://groups.google.com/groups?q=treseler+testbench+example -- Mike TreselerArticle: 65040
ALuPin wrote: > In QuartusII they can be included in the MegaWizard- > PlugInManager. > But how do I involve these .hex files when simulating in Modelsim? > Do they have to be compiled additionally to the > design VHDL files or do they have to be linked to in the testbench? > When trying to simulate after compiling the VHDL modules I get > an error message "Fatal error ... altera_mf.vhd ... not found". Consider using the standard vhdl templates to infer block rom or ram to eliminate the MegaWizard simulation hassles. -- Mike TreselerArticle: 65041
The 22V10 originated at AMD (I was there!), but later became the "standard" for high-end PALs. You can find it with anybody who (still) makes PALs. Try Lattice, TI, NSC... There are bipolar and CMOS versions, sharing the same functionality and pin-out, but obviously not the programming. The 22V10 dates back to the early 'eighties. That's 20 years ago. At my analogy of 15 human years per 1 programmable logic year, these 22V10s are 300-year-old "senior citizens". Using them for a new design would be silly (inhumane?). One cheap CPLD runs circles around several 22V10s, and CoolRunner CPLDs consume almost no power... Peter Alfke ======================== hamilton wrote: > > I have found a tube of these AMD parts from on old project. > > AMD no longer manufactures these parts. Does anyone know who > picked up these parts from AMD ? > > I am also looking for a simple programmer for these parts. > > I have found $500+ programmers out on the net, but I would like > to keep it cheap. > > Thanks for any info. > > hamiltonArticle: 65042
See page 54, second paragraph in XAPP462: Using Digital Clock Managers (DCMs) in Spartan-3 FPGAs. http://www.xilinx.com/bvdocs/appnotes/xapp462.pdf -------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/II/IIE FPGAs http://www.xilinx.com/spartan3 --------------------------------- Spartan-3: Make it Your ASIC "Peter Alfke" <peter@xilinx.com> wrote in message news:400C191A.6C001E1D@xilinx.com... > Just to confirm it officially: > In frequency synthesis mode, M/D is done as a combined mathematical > operation. Therefore it is irrelevant that the multiplication by itself > might exceed the max frequency. I remember publishing this in several > places, but cannot find it right now. It is one of the major nice > features of the DCM. > > Peter Alfke, Xilinx Applications > ================ > Antti Lukats wrote: > > > > " > > RTFM, RTFM, RTFM > > there is somewhere a notice in datasheets that the DCM can be used > > in such situation where the virtual CLK is way beyound operating > > frequency, the DCM will still work. > > > > So you should be safe, using the DCM with those parameters as given. > > > >Article: 65043
Nick Suttora wrote:
>>Consider siming your source level before gate level.
>>That's about ten times faster.
>>
>> -- Mike Treseler
>
>
> I am using a core in the part which was delivered as a gate level
> netlist so I have no choice.
The choice is a tradeoff of the cost of getting the source
code vs the cost of testing the core netlist as is.
-- Mike Treseler
Article: 65044Thanks for responding. What I mean is that I have 9 designs, each desined for a different chip, but each chip must interact with the others. Therefore, to simulate this environment I need to run an implementation and simulation for each chip and have the outputs of the chips interacting with one another. Since XILINX's Project Manager only loads one chip's design at a time, I would need to have many instances of it running at once and to have them interact with one another. It is a real time system so the response time, and communication between chips are crucial. I really appreciate Mike Treseler's suggestion to represent each chip as an HDL module and then simulate the design. My main concern with this though is whether I could get a target FPGA with enough space for the nine designs. Also, I noted that Brandon King has a system with similar complexity as mine. I don't have my board built as yet and was wondering if there is any place I can ask to build a board for me with 9 Virtex FPGAs. Thanks so much for the responses. Bob Perlman <bobsrefusebin@hotmail.com> wrote in message news:<c51k00lpi09inh4kb69ogettgmgrc4dpkn@4ax.com>... > On 16 Jan 2004 08:39:37 -0800, pbrowne0@excite.com (Patrick Browne) > wrote: > > > I noticed that XILINX will not run in multiple instances. > > What does this mean? > > Bob Perlman > Cambrian Design WorksArticle: 65045
Hi, I am looking for a distributor of the altera ep1k10 fpga series. I need to order a small number (1-5) of these devices together with configuration proms, oscillators etc. Is there any distributor in Europe (Germany?), who offers this? If you could answer the same question also for Xilinx fpga's as well as for A/D converters like adc0831 or adc08060, you would help me very much. Thanks PatrickArticle: 65046
Patrick Birger wrote: > Hi, > I am looking for a distributor of the altera ep1k10 fpga series. I > need to order a small number (1-5) of these devices together with > configuration proms, oscillators etc. Is there any distributor in > Europe (Germany?), who offers this? > > If you could answer the same question also for Xilinx fpga's as well > as for A/D converters like adc0831 or adc08060, you would help me very > much. have a look at http://www.ebv.com for the Altera parts. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 65047
On 19 Jan 2004 10:55:15 -0800, pbrowne0@excite.com (Patrick Browne) wrote: >Thanks for responding. What I mean is that I have 9 designs, each >desined for a different chip, but each chip must interact with the >others. Therefore, to simulate this environment I need to run an >implementation and simulation for each chip and have the outputs of >the chips interacting with one another. Since XILINX's Project Manager >only loads one chip's design at a time, I would need to have many >instances of it running at once and to have them interact with one >another. It is a real time system so the response time, and >communication between chips are crucial. Do you want to: 1) simulate the FPGAs on a computer 2) emulate the desired functions in actual hardware 3) both? For (1), you can use virtually any HDL simulator. As Mike suggested, you have a (top-level) module for each FPGA, and another top-level module that ties them all together. For (2), you build a board with multiple FPGAs, or buy a board; the Dini Group makes stuff like this. I'm not sure what any of this has to do with Xilinx Project Manager. Bob Perlman Cambrian Design WorksArticle: 65048
> Has anybody tried Chipscope Pro with a MicroBlaze based system? > > I am using JTAG-Uart for debugging purposes and now I want to use > ChipScope Pro at the same time, but when I try to implement it > generates an error with BSCAN. > >I know that JTAG-Uart uses a BSCAN and ChipScope also needs another >one. If I take out the JTAG-Uart from the design it works. There is single BSCAN per FPGA, that BSCAN instance has two "user" instructions. If either JTAG UART or ChipScope uses both user instructions then it most likely is nogo with JTAG Uart and ChipScope at the same time, if both use only one user instruction then it could at least theoretically be possible. But I think it is not possible at this time. Ok, I can confirm at current time it is not possible: if you look at opb_jtag_uart RTL sources you see that even it is using only one user instruction from the 2 available ones it uses the BSCAN instance in a way that it can not be shared with Chipscope, and second - even it would worked, I think XMD and ChipScope can not share the JTAG interface so it wouldnt work anyway antti xilinx.openchip.orgArticle: 65049
I have to make a change to a XC4005pc84-5 part but I don't have the tools that support XC4000 parts. I've gone all the way back to Alliance Series 1.5i and XC4000E's are supported but not XC4000's. I believe I need an old set of M1 tools but I don't know where to find them. Does anyone know where I can get an old set of Xilinx tools that can supports XC4000 parts (not XC4000E parts). Thanks for any info. Ted
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