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Peter Alfke <peter@xilinx.com> wrote in message news:<401011AA.9D090355@xilinx.com>... > Strong words, Rudi ! > But unless you can substantiate your claims, we will ignore them as your > kind of BS. Which part in my post was unclear ??? Let me break it down for you: Paul Leventis wrote: > But this is why FPGA companies have timing modeling and characterization > groups, and part of why FPGAs are slowly taking over the world (or so I hope > :-) -- imagine having to worry about all this stuff when doing your ASIC? Only seldome have I been able to repeat a synthesis run with FPGAs and get exactly the same results every time (if I don't make changes). Running FPGA synthesis is like throwing the dies in Las Vegas. Funny enough, I can run Synopsys Design Compiler 100 times in a raw and always get the same result. Besides what is he trying to say ? ASIC vendors don't do timing models and don't do characterization ? Hmm, anybody from TSMC, or UMC, or any other ASIC vendor who would like to comment ? FPGA guys always look at a FPGA and tell everybody how cheap they are. They never include the cost for a PROM, and if they do they always use the cheapest ROM, and then tell you how you can easily change the configuration. However they never tell you in advance that the ISP ROM cost just as much as a (small) FPGA. Hmm, that deception in my eyes. > I am an engineer, and I do not make marketing claims, and neither do I > publish 80% nonsense and 15% lies. I didn't anywhere in my post refer to you or mantion your name. I was replying to the writings of Paul Leventis. It is not my intent to search the archives and evaluate what you have written or not, and judge you. I know you and Paul, and many other from both companies provide excellent tech support. So why, oh why, do some guys throw in the occasional marketing crap ??? > For some reason the world is rapidly converting to FPGA. Last year there > were less than 1500 new ASIC designs and probably 100 000 new designs > using FPGAs. Many of us in this ng are aware of the ASIC advantages, but > they come with a hefty price tag, long manufacturing time, risk and > inflexibility. That's why most of us prefer FPGAs. It is also reflected > in the name of this ng. Last couple of years where plagued by bad economy. We saw very few ASIC designs. A large factor why FPGA sales have been growing is because they are getting big and fast enough to be used in ASIC modeling and prototyping. I can't envision a $1000 US FPGA going in to many designs. That are very special situations - not the norm. In my opinion, FPGA are not taking market share away from ASICS. Thats where Structured ASICS and Gate Arrays come in. The reason IMHO, is that, FPGAS are getting big and fast and open up new areas and possibilities that where before impossible to achieve. > So, Rudi, if you want to post here, say something meaningful,and do not > just blurt out unsubstantiated insults. Hurts your reputation more than mine... > > Peter Alfke, Well, I hope this was meaningfully and substantial. And don't worry, marketing crap will not hurt my reputation, but yours ... you are telling lies not me ... rudi ======================================================== ASICS.ws ::: Solutions for your ASIC/FPGA needs ::: ..............::: FPGAs * Full Custom ICs * IP Cores ::: FREE IP Cores -> http://www.asics.ws/ <- FREE EDA ToolsArticle: 65326
Hi, I am interested in the timing model of the MultiTrack interconnects on Stratix. The timing models for most resources (LEs, M4ks, IOs, etc) are described in detail in the Stratix handbook, but, curiously, while the symbols are defined for the MultiTracks (R4, R8, R24, C4, C8, C16) in the latest handbook (pg 4-25), the actual timing numbers are never given. Does anyone have this information? I am digging into a DSP circuit using Chip Editor and am very curious what the tPD's are for the various MultiTracks used in the critical path (I know the overall tPD from the timing analysis report). -- PeteArticle: 65327
>So does this mean from now on if I reply to a query for >a proto/starter board, you will start beating me :) Your posting didn't contribute much to the group. Most of us had already seen your previous announcement/ad. It would have been much more interesting if you had included a list of the boards that you think of as compention and a quick summary of which board is good for what/why. Price? I/O gear? ... You can also use email if you don't have anything to contribute here. Don't get me wrong. I like announcements. It's just that I want engineering info rather than marketing blabber. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 65328
Dear FPGA developers, I'm a CS student who's currently trying to get into Evolvable Hardware. Unfortunately I don't have much background in hardware design, but maybe you can still point me in the right direction. So far I was able to set up a FreeBSD server and do a memory map of the vintage Xilinx XC6200 mounted on a VCC Hotworks PCI board and write the resulting bitstream to a file. Is there a tool for Windows which would decode the XC6200 bitstream into a CAL file, thus allowing me to import the configuration to a design tool? All the Xilinx tools I tried expect the board to be mounted either on the local machine or on a remote Windows system. I found quite some stuff about Virtex readback, .bit files, bitgen and so on, but I'm unsure to what extend that work- flow can be adopted to the vintage XC6200/Hotworks... Best regards, TobyArticle: 65329
Try floorplanning. If you floorplan an FPGA, you get repeatable results.
Rudolf Usselmann wrote:
> Only seldome have I been able to repeat a synthesis run with
> FPGAs and get exactly the same results every time (if I don't
> make changes). Running FPGA synthesis is like throwing the dies
> in Las Vegas. Funny enough, I can run Synopsys Design Compiler
> 100 times in a raw and always get the same result.
>
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 65330Is the Virtex II flip-flop primitive FDDRRSE limited in that its output can only connect to an I/O or obuf type primitve? The naming convention would imply that it can be used for internal connections to another CLB, but that doesn't appear to be the case.Article: 65331
Hi Rudolf, Let's examine my conclusion again: > > But this is why FPGA companies have timing modeling and characterization > > groups, and part of why FPGAs are slowly taking over the world (or so I hope > > :-) -- imagine having to worry about all this stuff when doing your ASIC? The last bit was a somewhat vague dig at ASICs -- to some degree, I'm smokin' a bit of the FPGA marketing dope. But I still believe there is truth to this statement. I am not claiming that ASICs lack timing models, nor that there aren't tools to analyse the myriad of phenomena that one must worry about when eeking the most performance out of them. I do suppose a user has the choice of sticking with a conservative view of timing, leaving some performance on the table for guard-band (while still exceeding the performance of an FPGA), and making their life easier in this department. However, I think you would be hard-pressed to argue that it is as easy or easier to design to an ASIC as it is to design to an FPGA... > Only seldome have I been able to repeat a synthesis run with > FPGAs and get exactly the same results every time (if I don't > make changes). Running FPGA synthesis is like throwing the dies > in Las Vegas. Funny enough, I can run Synopsys Design Compiler > 100 times in a raw and always get the same result. I'm not sure how synthesis repeatibility is related to my discussion of timing-related phenomena. Regardless, you should get the same answer out of our CAD tools every time you run them with the same input on the same machine. If you don't, this is a bug and should be reported to Altera -- I know Vaughn's team just loves hunting down non-determinism issues. Sucks to be the engineer who draws the short-straw on those bugs... > Besides what is he trying to say ? ASIC vendors don't do > timing models and don't do characterization ? Hmm, anybody > from TSMC, or UMC, or any other ASIC vendor who would like > to comment ? He was not trying to say that. Altera and other FPGA vendors would be screwed if that were the case. Who do you think we're relying on the for the underlying models we use for telling you your timing? > FPGA guys always look at a FPGA and tell everybody how > cheap they are. They never include the cost for a PROM, > and if they do they always use the cheapest ROM, and then > tell you how you can easily change the configuration. > However they never tell you in advance that the ISP ROM > cost just as much as a (small) FPGA. Hmm, that deception > in my eyes. In the design of Cyclone (our low-cost family), we kept in mind overall system cost, including the required PROM. This is why we added the active-serial programming mode, a matching family of low-cost serial programming devices, and the bitstream compression feature. If you look at our web page on our active serial devices (http://www.altera.com/products/devices/serialcfg/features/scg-adv_features. html) you will see a marketing chart, complete with vague x-axis, examining total cost of device + programming solution. A thorough treatise of the subject it is not, but we're not trying to deceive anyone. > > I am an engineer, and I do not make marketing claims, and neither do I > > publish 80% nonsense and 15% lies. > > I didn't anywhere in my post refer to you or mantion your name. Ah, come now -- Peter's had a few posts with less than 100% truth at times too ;-) My original posting contained 1425 characters, of which 114 were detected to the marketing crap in the last paragraph. So while not quite 80% non-sense and 15% lies, that's about 8% questionable/non-technical content, more than I typically strive for. > So why, oh why, do some guys throw in the occasional marketing > crap ??? It's hard to resist. This is a public forum, and as much as we'd like to be providing 100% engineering data at all times, we also must try to sell our products. I never post anything I believe is misleading, but I have (and will continue to) actively direct people to our products and marketing collateral whenever I feel it is relevant. > Last couple of years where plagued by bad economy. We saw > very few ASIC designs. A large factor why FPGA sales have > been growing is because they are getting big and fast enough > to be used in ASIC modeling and prototyping. I can't envision > a $1000 US FPGA going in to many designs. That are very > special situations - not the norm. In my opinion, FPGA are not > taking market share away from ASICS. Thats where Structured > ASICS and Gate Arrays come in. Trust me, $1000 US FPGAs go into many designs. And we love it. The truth is that as we push into smaller and smaller process technologies, the investment in NRE costs such as masks, as well as development tools and the engineering effort required to bring a chip out are increasing rapidly. There are fewer and fewer sockets that have large enough revenues to generate a high enough ROI on a (pure-play) ASIC development. Now, comparing FPGAs at 90 nm against ASICs at 90 nm is not fair, since you can get similar performance and cost at older technology nodes, but the trend is still there. Let's look at that $1000 FPGA again. Let's say it costs you $6 M to design, test, and manufacture your first ASIC and $0 per unit thereafter, while the FPGA costs $1M to develop & test, and $1000 per unit. You'd need to have guarenteed volumes of more than 5000 units before this effort pays itself off, and that's excluding the opportunity cost of tying up those resources for the time it takes to develop the product. Including a desired ROI, it's probably 10x higher. As the dev costs get higher, and FPGAs grow in density but remain at the same price, the break-even point pushes further and further out. Examples of boxes with $1000 FPGAs in them: Think any big box that costs ~$100K -- routers, storage servers, telecom boxes, etc. There are companies that have products that they are happy to sell 100 of each year. In these markets, FPGAs are a perfect fit. I agree that structured ASICs will also work to take market share from ASICs, as they provide an intermediate solution in the cost-per-unit & fixed cost space. That's why we have our HardCopy product line. This allows our customers to go to production with an FPGA, with the insurance that they can move to a structured ASIC in the future. Plus converting over is easy -- all the hard IP blocks are identical (PLLs, RAMs, etc.) reducing the chances of problems in conversion. It's a hard-to-copy business strategy, and we hope it will continue to a be a very succesful one. And with the availability of low-cost, high-performance FPGAs such as Cyclone, markets with volumes of 100,000+ units are now opening up to us. Will we truely take a lot of market share from ASICs here? I dunno -- we'll know the answer in five years after we've seen another full ASIC up-and-down cyclone. Regards, Paul Leventis Altera Corp.Article: 65332
This appears to be the latest thinking, from NASA. Flash seems like it would be fairly susceptible to radiation. Does anyone know if any other inter-planetary craft have utilized this technology? BobArticle: 65333
regarding LVDS_25_DT, John wrote:
> Does anyone know of any issues with using this
> input termination mode?
I recently bought a Avnet V2Pro eval board to try out
the new _DT terminators; unfortunately, as recently as
last month, they were still shipping boards with 2VP7-ES
parts, which do not support the _DT terminators or the
new DCI update modes.
If you're going to test or prototype soon, make sure
you have a part listed as supporting _DT termination in
Answer Record 17244.
The _DT terminators should address the LVDS_25_DCI
static power dissipation, DC offset, and DCI modulation
problems; however, the published differential input
buffer parasitics in the datasheet and IBIS models are
identical for both the V2Pro and the V2, so be careful
if driving the inputs from a fast LVDS/ECL device.
I'd provide some Answer Record #'s, but the Xilinx Answer
Record search function seems to be broken tonight- here's
what I recall from the last time I looked:
- the _DT terminators do not require a VRP/VRN reference
resistor pair. This suggests that they have a fixed
value, rather than being controlled by the DCI logic,
so they should be immune from any remaining DCI
modulation problems in the V2Pro
- RSDS and LVDS primitives can not co-exist in the same bank
- be careful of VCCO levels- as noted by Symon, although
the LVDS Rx's are powered by VCCAUX, the documentation
states that the banks with the _DT terminators also need
to have VCCO at 2.5V
- LVDS drivers MUST be in a 2.5V bank on the V2Pro (unlike V2)
- V2Pro DCMs do NOT support external 2X clock feedback.
This omission may affect your 800 Mbps application.
- Verify the _DT IBIS models with some simple test cases
before trusting them and your IBIS simulator.
I've had plenty of problems with differential ECL/LVDS
IBIS models and simulators in the past, and I'm not certain
IBIS 2.x can properly model differential terminators and
differential package parasitics.
Brian
Article: 65334
Jan Panteltje <pNaonStpealmtje@yahoo.com> wrote in message news:<1074893678.673451@news-01.evisp.enertel.nl>...
> On a sunny day (Thu, 22 Jan 2004 10:56:52 -0800) it happened Austin Lesea
> <austin@xilinx.com> wrote in <bup6dl$8dl2@cliff.xsj.xilinx.com>:
> >
> >Hope those folks figure it out, as it is a tradegy for everyone to lose
> >the ability to gain knowledge of our solar system.
> It is obvious whodidit:
> http://www.home.zonnet.nl/panteltje/mars/easthills-bunny.jpg
Thats an interesting graphic to coool out the topic
Ram
Article: 65335
you can add X"00000001" to the result.. or if you include the right file....
'use ieee.std_logic_signed.all' (I think) then the conversion from 1 to
X"00000001" is done automatically.
but you might want to try
library ieee;
use ieee.std_logic_signed.all;
...
if (...) then
if (nano_bit /= X"FFFFFFFF") then -- I think you can use (others =>
'1') instead of X"FFFFFFFF" here
nano_bit <= nano_bit + 1;
else
nano_bit <= 0;
end if;
end if;
Simulators will tend to barf as an overflow will occur when the counter
reaches max and increments so good practice is to limit the range of a
counter. This also makes the counter have a readable limit.
Simon
"Trent R." <rnenna@gmx.de> wrote in message
news:buu99a$acv$1@ngspool-d02.news.aol.com...
> Hello,
>
> I started now with VHDL....so maybe it´s a stupid Question....
> but is there an easy way to increment a bitvector?
> For example something like this:
>
> SIGNAL nano_bin : std_ulogic_vector(31 downto 0);
> IF....THEN
> nano_bin <= nano_bin +1 ;
> END IF;
>
> THX Trent
>
Article: 65336Hi, group: I am using a DCM to convert 40MHz to 36Mhz...now I need 12/4/1MHz clocks also... May I simply cascade a three DCMs to 36MHz (CLKDV_DIVIDE = 3/12/36) or three DCMs using Multiply/Division (violates CLKOUT_FREQ_FX_LF_Min)? Will two DCMs cascaded together work well? In one simulation I found the second DCM complained the previous stage's skew is greater than 1ns... How may I do with my situation? Thanks for your advice. KelvinArticle: 65337
"Kelvin @ SG" <kelvin8157@hotmail.com> wrote in message news:buvks6$13g$1@mawar.singnet.com.sg... > Hi, group: > > I am using a DCM to convert 40MHz to 36Mhz...now I need 12/4/1MHz clocks > also... > May I simply cascade a three DCMs to 36MHz (CLKDV_DIVIDE = 3/12/36) or three > DCMs using Multiply/Division (violates CLKOUT_FREQ_FX_LF_Min)? > > Will two DCMs cascaded together work well? In one simulation I found the > second DCM > complained the previous stage's skew is greater than 1ns... > > How may I do with my situation? > > Thanks for your advice. > Kelvin > > > The biggest problem may be a violation of the DCM's input jitter spec. A given DCM's output jitter is due to its intrinsic jitter and its input jitter. I believe that you can safely cascade two, but not three DCM's -- even if the input jitter to the first DCM is zero. You'll have to check the data sheet and also consider your clock source jitter. If the jitter applied to a DCM input is too high then it will not lock. BobArticle: 65338
Hi, there: I am performing partial reconfiguration tutorial. How do I fix this error in the final assembly stage? Thanks for your advice. Kelvin Starting Guide File Processing. Loading device database for application Par from file "../../pims/iq_gen/iq_gen.ncd". "sig_gen" is an NCD, version 2.38, device xc2v250, package fg256, speed -4 The STEPPING level for this design is 1. FATAL_ERROR:Guide:basgitaskphyspr.c:255:1.28.20.2:137 - Guide encountered a Logic0 or Logic1 signal GLOBAL_LOGIC1_32 that does not have a driver or load within the module boundary. This problem may be caused by having a constant driving the input from outside the module boundary or because a driver or load comp did not meet the par-guiding criteria. The design will not be completely placed and routed by Par-Guide Process will terminate. To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.com. If you need further assistance, please open a Webcase by clicking on the "WebCase" link at http://support.xilinx.comArticle: 65339
I am quite new to FPGAs and I would like to play with Altera EPK10TC100-3. My main computer is an Alpha CPU Linux machine. I learnt how to transfer compiled RBF files to the chip. What I would like to know is how one goes about to write, for instance, a Verilog compiler for a specific chip. I have experience with microprocessors only, and it is quote stratightforward to write assemblers as processor makers release the specification of the machine code. I am interested in what each bit represents in the Raw Binary Format, so that I can play with the device at the lowest level, making the wiring myself first and possibly use this know-how to write some compiler later. Is there such low-level specification available for FPGAs? Thanks GasparArticle: 65340
Kelvin @ SG <kelvin8157@hotmail.com> wrote in message news:buvks6$13g$1@mawar.singnet.com.sg... > Hi, group: > I am using a DCM to convert 40MHz to 36Mhz...now I need 12/4/1MHz clocks > also... > May I simply cascade a three DCMs to 36MHz (CLKDV_DIVIDE = 3/12/36) or three > DCMs using Multiply/Division (violates CLKOUT_FREQ_FX_LF_Min)? > Will two DCMs cascaded together work well? In one simulation I found the > second DCM > complained the previous stage's skew is greater than 1ns... > How may I do with my situation? > Thanks for your advice. > Kelvin Kelvin, You could run all the 36/12/4/1 MHz stuff off the 36 MHz clock and create clock enables for the 12/4/1 MHz logic. This would remove any potential problems transferring data between these different clock domains. Hope this helps, Nial Stewart ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design Cyclone based 'Easy PCI' proto board www.nialstewartdevelopments.co.ukArticle: 65341
> I am interested in what each bit represents in the Raw Binary Format, > so that I can play with the device at the lowest level, making the > wiring myself first and possibly use this know-how to write some > compiler later. > > Is there such low-level specification available for FPGAs? The companies won't publish a lot of information on the bitstream data format. A lot of universities request that for their research in the past. What they got is the XC62000 series from Xilinx which was quickly discontinued. What you can get for Xilinx is the jbits package. That's an API that will not tell you what the individual bits mean, but it allows you to manipulate the bitstream in a meaningful way. You can for example set the content of LUT x and connect it ot LUT y. Altera has a university program that allows you to manipulate the data structures of their backend tools. So you still need the full set of Altera tools running, but you can experiment with your own algorithms. Kolja SulimmaArticle: 65342
"Patrick Klacka" <pklacka@trexenterprises.com> writes: Build with FFs? What's the depth X width? Homann -- Magnus Homann, M.Sc. CS & E d0asta@dtek.chalmers.seArticle: 65345
On 19 Jan 2004 10:55:15 -0800, pbrowne0@excite.com (Patrick Browne) wrote: >Thanks for responding. What I mean is that I have 9 designs, each >desined for a different chip, but each chip must interact with the >others. So a board with 9 FPGAs, each with a different design. The chips communicate with each other. >Therefore, to simulate this environment I need to run an >implementation and simulation for each chip and have the outputs of >the chips interacting with one another. No you don't need to run implementation to run simulation. You can (and should) run a pre place and route simulation. These also simulate faster than the post P&R simulations, but they do not contain timing information. This is also sometimes called unit-delay or functional simulation. If you have been a good boy and done fully synchronous design, these simulations can be sufficient for robust design, and the timing simulation (must be post P&R) is not needed. If you create a test bench for each design, you can test each design in isolation. In a multi chip design like yours, this may not be the best plan, as the interactions may be hard to describe in a test bench. >Since XILINX's Project Manager only loads one chip's design at a time, >I would need to have many instances of it running at once and to have >them interact with one another. No you don't. The Xilinx project manager is just a shell that runs separate programs. The simulation program (which I am guessing is Modelsim) can be run outside the Xilinx project manager. In fact you can probably find out how the project manager starts up modelsim, then just do it for your self. This will be somewhat less circuitous and will use less memory on your PC, as there is no actual need for the Xilinx project manager to be running when you are running your simulation. So this is how you run one designs simulation. You can run a multichip simulation the same way, and you only need one instance of the simulator running. Here's how: Let's say your 9 designs are named PB1 through PB9. Each has a top level, and the I/O of the top level is the pins that will be on the FPGA. Each of your designs probably has a different I/O list. You now create a system simulation test bench that is hierarchically one level higher than your 9 designs. In fact it represents your board. In this file you instantiate one of each of your designs PB1 .. PB9, and you connect between their I/O just as you expect your board to be wired. And I/O that are left over (i.e. not going between the FPGAs) are your system level in's and out's. Your test bench must drive these inputs with appropriate test signals and the outputs are probably what you care about. As you can see, there is no need to be running the Xilinx project manager, nor is there a need to push the 9 designs through P&R to do this. This is all unit-delay, pre P&R simulation. >It is a real time system so the response time, and >communication between chips are crucial. > >I really appreciate Mike Treseler's suggestion to represent each chip >as an HDL module and then simulate the design. My main concern with >this though is whether I could get a target FPGA with enough space for >the nine designs. I hope you now understand that there is no need for such a huge FPGA, since you do not have to get all into 1 FPGA to do this simulation. >Also, I noted that Brandon King has a system with >similar complexity as mine. I don't have my board built as yet and was >wondering if there is any place I can ask to build a board for me with >9 Virtex FPGAs. There are many companies that will build boards, but this is not going to be cheap. You may want to look at products from the Dini group that specifically makes such boards: http://www.dinigroup.com/ Or another company to look at is Aptix. Either way, sit down before you ask the price. Even though the prices will seem high, they will be cheaper than trying to do it your self. Philip Freidin FliptronicsArticle: 65346
Patrick Klacka wrote:
> Thank you everyone for your suggestions thus far. It's clear that more
> details are needed in order to better explore this problem. Please see
> http://www.trexenterprises.com/~pklacka/fifo.html for implementations in C
> code.
>
> It seems that all the solutions favor one change to a particular value, but
> do not consider the case of the changed value being changed. For example,
> the value of 5 is changed to 6. Now a 5 is retrieved from the fifo. We know
> through the Blake's CAM implementation and Jim's SyncRAM implementation that
> the value of 5 will be transformed to a 6. Now the 6 is changed to a 7. When
> we retrieve a 6 from the fifo, we get a 7 as intented. But should a 5 come
> off the fifo, we still get a 6, unless some sort of recursion is used. The
> recursion is what I am attempting to avoid. If all the 5's in the fifo could
> be changed to 6's before the 6's get changed to 7's, then I have a working
> solution.
We need some more info on peak/average Read and Change stream rates,
and likely 'change depth'.
You can either change on read, and iterate until the change stack
stops changes, which will be HW frugal, but will have a finite settling
time. ( similar to a linked-list in SW )
Or, you can change all in-situ, but that is also likely to have a
finite settling time, as the delta-list will have to arrive
sequentially, but maybe at a much lower average rate.
This will read faster, but consume much more HW.
So it's like any parallel/serial trade off: HW vs bandwidth.
If the change-list stream rate is slow, you could do a combination of
table correct {fast, but one-deep), and interleaved scan change,
(slower, but will recurse).
Thus the FIFO becomes a bit like video memory, where one task
scans/changes and the other reads.
It would need "pause" ability, for when/if too many changes arrive
for the change paths to settle.
-jg
Article: 65347Yeah, yours is the better approach...However I am converting an ASIC design into FPGA... there are a few megabytes of source codes...sigh...that is the problem... "Nial Stewart" <nial@nialstewartdevelopments.co.uk> wrote in message news:4013975e$0$214$fa0fcedb@lovejoy.zen.co.uk... > Kelvin @ SG <kelvin8157@hotmail.com> wrote in message > news:buvks6$13g$1@mawar.singnet.com.sg... > > Hi, group: > > I am using a DCM to convert 40MHz to 36Mhz...now I need 12/4/1MHz clocks > > also... > > May I simply cascade a three DCMs to 36MHz (CLKDV_DIVIDE = 3/12/36) or > three > > DCMs using Multiply/Division (violates CLKOUT_FREQ_FX_LF_Min)? > > Will two DCMs cascaded together work well? In one simulation I found the > > second DCM > > complained the previous stage's skew is greater than 1ns... > > How may I do with my situation? > > Thanks for your advice. > > Kelvin > > Kelvin, > > You could run all the 36/12/4/1 MHz stuff off the 36 MHz clock > and create clock enables for the 12/4/1 MHz logic. This would > remove any potential problems transferring data between these > different clock domains. > > Hope this helps, > > Nial Stewart > > ------------------------------------------------ > Nial Stewart Developments Ltd > FPGA and High Speed Digital Design > Cyclone based 'Easy PCI' proto board > www.nialstewartdevelopments.co.uk > >Article: 65348
Hi, just to simplify the previous reccomandations, I suggest you instantiate the primitive IOBUF at the xilinx pins. Tullio On Tue, 20 Jan 2004, Tobias Möglich wrote: > Hello > > An application question. > I want to design a Tristate buffer for a data bus. dinb is the input > data port of a BlockRAM > dataDSP is the bus of a DSP controller. > Isn't it possible to create the tristate buffer in the way I quoted at > the bottom of this article ??? > It doesn't work. > What's wrong ?? > > WRITING to BlockRAM > ----------------------------- > > ... > if (cs = '0') then > dinb <= data_DSP; > else > dinb <= (others=>'Z'); > > > Thanks for any help. > > Tobias Möglich > > -- Tullio Grassi ====================================== Univ. of Maryland-Dept. of Physics | College Park, MD 20742 - US | Tel +1 301 405 5970 | Fax +1 301 699 9195 | ======================================Article: 65349
Hello everybody!
I have a problem with placing my tbuf-elements.
Modules using bus operations are coupled to top-level switching them
to a bidirectional bus. See, like this:
---<snip!>
entity my_struct is port (
...
BD : inout std_logic_vector(15 downto 0);
...);
end my_struct;
architecture Behavioral of my_struct is
...
signal de, di : std_logic_vector(15 downto 0);
...
begin
...
my_external_connector : process (de, BD, ext_read)
begin
if (ext_read = '1') then
BD <= de;
de <= "ZZZ...Z";
else
BD <= "ZZZ...Z";
de <= BD;
end if;
end process;
...
mod_databus_write_sync : SYNC_2xFF port map (
I => de,
O => di);
...
my_module : SOME_MODULE port map (
DIN => di,
DOUT => internal_output,
CS => ...,
...);
my_toplevel_bus_read_process: process (internal_output,
read_condition)
begin
if (read_condition = '1') then
de <= internal_output;
else
de <= "ZZZ...Z";
end if;
end process;
end Behavioral;
---<snap!>
Additional Note:
****************
There are about 3 upto 5 internal modules which make use of this
structure.
So we get a maximum of 5x16 = 80 tristate buffer lines, probably some
more.
****************
Synthezising, Translation and Mapping is always fine, but since the
implementation process comes to PAR, the placer stops after a couple
of warnings and at least one error like this:
---<snip!>
... WARNING! Unable to place TBUF of module <#1>!
...
... WARNING! Unable to place TBUF of module <#n>!
...
... ERROR! Placing was not complete!
...
---<snap!>
I have read on XILINX support pages, that this problem can be worked
around by using AREA_GROUP constraints. If I have understood this in
the right way, the constraints will show the placer how I would like
to layout the tristate buffers. But all I can choose in ISE for
SPARTANII are Row and Column-statements, for which I have no idea how
to use them in a proper way.
I am using XILINX Webpack ISE 6.1 with a SPARTANII (-5) architecture.
Help or at least some hints would be very appreciated!
Bye,
Thomas.
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