Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
praveenkn123@yahoo.com (prav) writes: > Are there any other alternatives to replace a opto isolator so that i > can work at higher frequency. IsoLoop has isolators that run up to 35 Mbps. http://www.nve.com/products/isolators/isproducts.phpArticle: 66201
"rickman" <spamgoeshere4@yahoo.com> escribió en el mensaje news:402D5004.7E73D943@yahoo.com... > "Amontec Team, Laurent Gauch" wrote: > > For the JTAG interface, just add an Multi-ICE 20-pin header. Most > > designers have Wiggler-like Dongle. Or if you need a better flash > > programming baudrate or debugging baudrate, use the Chameleon POD with > > raven_all_speeds configuration. > > (note: Chameleon POD can operates as Raven, Wiggler, > > Xilinx_parallel_cable, Altera_ByteBlaster, Lattice_ispDownload, > > Atmel_AVR_stkxxx, configutation! ALL config for FREE, ALL in ONE Dongle) > > Or you could just add the Xilinx coolrunner part that they are using on > the Chameleon pod and connect directly to the PC! Actually, we are doing something much better, but it will only see the light once we have the necessary ROI to fund its production ;^) Regards.Article: 66202
"rickman" <spamgoeshere4@yahoo.com> escribió en el mensaje news:402D53AD.C0D80CBB@yahoo.com... > > Many of the newer ARMs are available in Industrial temps (OKI only comes > in Industrial) and some work with a 32 kHz xtal (the OKI does not). Main problem is, as always, availability. There are some newer parts that have more features than the one we are using at a similar price, but, believe me, we laid out all the information we had on the table before we picked up the processor. > > Yes, we considered and are considering other devices as well, like OKI > > chips (they support external SDRAM, though these are difficult to > > source in industrial temp) and the LPC22XXs. > > Unfortunately the LPC22xx are not out yet. Only the versions with no > external bus are available. The LCP21XX are supposedly to be available, but they are very difficult to source. Waiting for the LPC22XX was simply out of the question. Also, these devices are too new to put them out directly into production without knowing the exact erratas. These chips look good, though, so surely we will be evaluating them to use them in our solutions. > Wow! That is a lot more than other devices can do, but I guess if it is > not an issue with your application it does not matter. The OKI part > runs at 60 MHz with less than 60 mA @ 2.5v. Of course the FPGA current > will depend on the app inside, but we are designing with <70 mA @ 5v > target in mind. Our sleep current is around 5 mA which is almost all > from the FPGA. Many of our customers run from batteries and the current > is a *major* concern. Thanks, that is a good figure to know about. > > Have you measured their standby current (before configuration) and > > static consumption (after configuration and halted clocks)? That would > > be nice figures to compare. > > I have not measured it, but the numbers that Altera has given me are 100 > mA startup surge and 5/10 mA static current (commercial/industrial > temps). Well, so I guess in this case the datasheet reflects reality (not always the case, with any vendor indeed). Regards. -- PabloBleyerKocik / "Personally I don`t understand the motivation pbleyer / to build robots in human form since humans are @embedded.cl / so available and inexpensive." -- Lou BoydArticle: 66203
[Sorry to repost, but it seems my news server screwed up again] "Garrett Mace" <g.ryan@macetech.com> wrote in message news:<874Xb.9864$_66.2611@twister.rdc-kc.rr.com>... > I think the FPGA does separate it from most of the pack, though it is still > not alone. The size is quite attractive, making it lean towards a powerful > minaturized mobile application. However, the FPGA is not incredibly > power-efficient; some applications might require all the flip-flops, but a > low-power CoolRunner variation might be something to consider. They are > quite inexpensive and can fit a surprising amount of logic, I have a > four-axis (8 coil) bipolar microstepping translator and driver project that > so far fits into 128. The processor itself would probably be able to handle > many of the tasks you would use all the flip-flops for, anyway. The CPLD > also won't need to be reloaded every power cycle. Yes, we considered a CPLD versus the FPGA. For some applications the CPLD fits fine, but it leaves a lot of applications out. For example, we have had applications where we need a *lot* of UARTs, you can only fit one or two UARTs in most reasonably priced CPLDs. There is also a benefit/cost relationship. Indeed, the Coolrunner XC2C128 costs only ~US$4 less than the Spartan XC2S100E, and the latter has far more resources. The FPGA itself is not as power-hungry as one might think. > I think you what need to do is identify your competitors. In this case, I > think your main competitor is the Pocket PC series of devices, which get up > to a full day's worth of battery life, have an integrated LCD controller and > LCD, standard interfaces to memory and expansion cards, and with a 200MHz > processor and 64 megabytes of RAM can be had for less than $200. It is really not a PocketPC. You cannot put a PocketPC in an industrial environment! The idea of the board is to use it for deeply embedded devices, although of course you can plug an LCD and other consumer-electronics stuff to it. We are targeting the sub-US$100 market of 8 and 16 bit module boards. The idea for the battery operation is that you use the low power modes of the processor to reach weeks of battery life. > Your device > needs to make up its shortcomings in the display, memory, and standard > interface department, by pushing the programmable device aspect and large > number of high-speed user I/O. Yes, we will make modules and FPGA cores available for this. We know that the 1MB RAM limit could scare many people out there, but for the applications we have in mind there is no need for more (really -- eCos is so configurable that it only takes the memory resources it actually needs). The CF module, for example, will add enough memory for data logging applications, that is a typical scenario where you need lots of memory (eg 512MB). > Price the device in a range where customers > won't choose instead to build their own CompactFlash interface card with a > CPLD, and end up with a more powerful system for less money. If you target > this to engineers in a production environment, you could possibly get away > with a price near $400-$500, if you have a lot of options and good support > (you've also got to compete against the popular PC104 systems, and low-power > options probably won't be a selling point). If you target to hobbyists, I > think a $175 to $250 range would be realistic though they will always buy > something cheaper if they can. Basically find a cheap ARM board and a cheap > FPGA board, and add the prices together. In fact, we are targeting hobbyist and other OEMs. We are trying to sell the core board and modules for less than US$100, and the kit in no more than US$200. Thanks again for your comments, they are very valuable. Regards.Article: 66204
[Sorry to repost. Seems my news server screwed up.] Hello Lewin. Thanks for replying. larwe@larwe.com (Lewin A.R.W. Edwards) wrote in message news:<608b6569.0402130650.717890c2@posting.google.com>... > Hi Pablo, > > Interesting product. Some comments: > > > We would like to introduce this first as a basic kit with all the necessary > > tools to get one started (core module, adapter board with serial > > transceivers, wiggler-like JTAG programmers, software). The board itself is > > a wonderful combo-kit for learning about embedded systems with the ARM > > IMHO, this board is a bit complicated for introductory embedded > learning purposes. And I expect it will be a bit too expensive. You'll > be competing with sub-$200 boards from Atmel and sub-$100 ARM boards > based on other ARMs. Maybe it's better marketed as a poor-man's-ASIC > :) Yep, that's a nice comparison. ;^) However, we are trying to sell the core module and other modules for less than US$100 (single quantities), and the kit for something between US$150 and US$200. The idea of the core+module is to make modules as cheap as possible (eg 2 layer PCBs instead of the 6 layer PCB the core has). This will allow people to build their own custom boards cheaply too. > > > - How much will you be willing to pay for a kit like this. How much for core > > boards in quantities? > > I would personally pay up to about $300 for the board and > documentation. I wouldn't pay extra for a parallel port wiggler, etc. > because I already have these tools. For "production", I would only be > willing to pay around half that price for a board including FPGA. I > would suggest preloading Angel or (better) RedBoot in ROM, not > including JTAG tools with the appliance, and letting people use it the > good old way with a serial cable. Wow, that's a lot more than the price we thought we could sell the boards. We are pushing our costs as low as we can. We don't have all the cost figures yet (since this will be a first full fledged production we cannot benefit from scale economies yet), but the idea is to make the price low cost. If we have success we expect prices to improve. > > > - Do you think the FPGA configuration (ie, FPGA present on the board) will > > be useful for you? Would you choose this board over other similar products > > because of its FPGA functionality? > > The FPGA isn't directly useful to me - because I don't have enough > time to use it effectively (one-man team...) But it could become > useful if I could download canned applications from you - LCD > controller being the application of primary interest! Yes, that is the whole idea of it (like you said, a poor-man's ASIC. ;^) In the future we will provide FPGA cores, auto-configurable modules and configuration tools. For now the kit will be available, and most of the software (including HDL code) will be open source. > > > - Concerning the kit, do you think a base board with integrated programmers, > > serial transceivers and prototyping area would be more useful to you than an > > adapter board and separated programmers? > > Lose the prototyping area. Bring the signals to headers. I'm not > hacking stuff onto an eval board. Thanks, that is worthful. We were into the discussion of how valuable was the prototyping area for some people. Thanks again for your comments and suggestions! Regards.Article: 66205
We have a need to create hundreds of non proprietary digital test structures, each which would fit a pre-determined pinouts for a pre-determined block size & a pre-determined block shape (e.g., rectilinear). Can you provide a pointer to a good random logic verilog gate netlist generator? I'd expect to feed it technology & macro LEF; the input & output pins; and either a gate count, or a block area (most likely a gate count). After running this random-logic verilog-gate generator, we would then place & route the results. The easy part is the place & route. The hard part is to come up with hundreds of non-proprietary sets of random (well mixed) gates to fill the blocks up with. Any pointers would be appreciated. SimonArticle: 66206
> In fact, we are targeting hobbyist and other OEMs. We are trying to > sell the core board and modules for less than US$100, and the kit in > no more than US$200. > > Thanks again for your comments, they are very valuable. > > Regards. Nice looking board! How can you make a 6 layer board stuffed with memory, arm7 processor and a spartan II and sell for under $100??? I could see if you are making several hundred to thousands.... Which board house made the board? Digikey must be really juicing me on pricing... RickArticle: 66207
I wonder if even "serious" frequency counters, with single-shot time resolutions in the 10ps range, could profit from FPGA implementations. What if one were to simply distribute the incoming edge to thousands of flops over routes with various delays, then derive the incoming time from the resulting thermometer-encoded bit vector? The routing delays aren't known to such high precision, of course, but one could characterize the whole circuit once it's placed and routed: slew an input test signal over some range like 0--5 ns (created perhaps with an external phase microstepper chip), and watch when the bits flip. A random collection of 5000 routes would probably cover the clock interval with pretty good resolution. Could do this self-calibration every so often to control temperature variations. Or ovenize the FPGA. Cheers, Peter MontaArticle: 66208
There's a fairly nice arbitrary frequency sine and cosine generator core available from Xilinx that has a whole host of options. We're playing with it on a current project. It even has a multiplex mode where you can reuse the LUTs for up to 16 different signals. YMMV -Marty "Ian Poole" <ian.poole@doulos.delete-this-bit.com> wrote in message news:c0fmn5$ap8$1$8300dec7@news.demon.co.uk... > There is a synthesisable sine wave generator on our website here : > http://www.doulos.com/knowhow/vhdl_models/sine_wave_generator/ > > It includes a perl script to generate a sine wave lookup table of arbitrary > dimensions/precision. The code will probably want modifying slightly so it > uses LUT based ROM or BRAMs. If I have time, I might add an FPGA optimisd > version... > > HTH > > IanArticle: 66209
Hello Rick. "Rick" <rick@skyko.com> escribió en el mensaje news:CphXb.9460$5W3.4461@nwrddc02.gnilink.net... > > > In fact, we are targeting hobbyist and other OEMs. We are trying to > > sell the core board and modules for less than US$100, and the kit in > > no more than US$200. > > > > Thanks again for your comments, they are very valuable. > > > > Regards. > > Nice looking board! How can you make a 6 layer board stuffed with memory, arm7 > processor and a spartan II and sell for under $100??? I could see if you are > making several hundred to thousands.... No, we are not (yet -- but fingers are crossed. ;^) Our post was trying to analyze the demand for the product. We don't have final cost figures, but, yes, we think will be able to sell the core in single quantities around that amount. > Which board house made the board? Protos were manufactured by E-teknet (http://www.e-teknet.com/). I strongly recommend them. > Digikey must be really juicing me on > pricing... Digikey has improved its pricing a lot, but on some parts they are still pricey (specially AT91 mcus in this case). You can buy packs from, eg, Avnet (60 units) at the same price Digikey offers them at 1000 units. Regards.Article: 66210
"Invisible One" <Invisible_1@sympatico.ca> wrote in message news:hfuUb.8985$bp1.563899@news20.bellglobal.com... > I am doing my thesis in artificial intelligence, and wish to create a "proof > of concept". It has been a long time since I have been working with FPGAs > directly and wish to know the following: > > 1 - What software and hardware tools are available that operate well under > Windows (compilation, etc...)? Atmel and Xilinx have packages that are free and at cost for developing VHDL and other languages on their FPGA's. I use the Xilinx software for development in Windows XP and 2000. > 2 - Has anyone had any experience with programming AI's on FPGAa? Are there > tools available for FPGA development? I have seen Neural net applications and chaos generators developed on FPGA's for AI applications. Do a search on Google for papers that describe the NN and chaos applications. They also have VHDL source code available. > 3 - Are there any programmable logic devices out there that have a ADC built > in? Never seen a built-in ADC inside an FPGA but interacting is easy, especially for serial ADC's. I have connected 8 12-bit serial ADC's at one time. VHDL coding is easiest for serial ADC's. > 4 - Are there any "tricks" that I would be able to use in order to generate > uniform, gaussian or Cauchy noise with a minimal of external hardware? Yeah, the chaos application mentioned above uses "tricks" to geenrate the chaos "noise". Also, using spread-spectrum codes using a VHDL based LFSR can generate a noise when low-pass filtered on an output pin. > > Thank you in advance, I have posed many questions for a single posting! > > John. > >Article: 66211
Hi all, I'm looking for the PREP (Programmable Electronic Performance Cooperative) benchmark. Unfortunately, the site www.prep.org seems to be closed down... Does anyone know where to find the code (or e-mail me) ? Thanks in advance, -- Davide. anguita AT dibe.unige.itArticle: 66212
"Ray Andraka" wrote: > Obviously, the price point for FPGAs is not so far off the mark since people do use them. Ray, I think Steve is screaming at the delta between low and high quantity pricing, not necessarily at any specific price. In other words, if the high volume guys paid 50% less than low volume buyers he might not object. He is seeing a 400% differential and that bothers him. The rationalization might be that there are no real differences in the cost of manufacture for the chips that the small guy is buying (vs. the large buyer). Or the production of tools, documentation, etc. And, armed with that, I think he's saying that he can't see what in the process of getting chips to a small operator can justify a factor of 4x or more. I can't say that I am in complete disagreement with the idea of questioning pricing practices. However, I have yet to decide not to do a product based on the price of small quantities of FPGA's. Today, thanks to FPGA's, we can design systems that were impossible to realize not too long ago. On a price-per-FF basis you can't beat them. And, to repeat what I said in an earlier post, communication with the chip manufacturer is very important. They are sensitive to your needs and I've found Xilinx (through Austin and others) to be genuinely interested in helping the little guys. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 66213
Jim Granville <no.spam@designtools.co.nz> writes: > Marius Vollmer wrote: > >> Could you explain what "10 digits/second" means? I have no idea... >> Thanks! > > It's a figure of merit for reciprocal counters, [...] Thanks a lot! -- GPG: D5D4E405 - 2F9B BCCC 8527 692A 04E3 331E FAF8 226A D5D4 E405Article: 66214
Use the WIRE primitive and use a[1] as the name of the input to te WIRE
primitive, and b[0] as the name of the ouput of the WIRE primitive. You can
insert the WIRE primitive from the Symbol Enter box.
|\
a[1] | \ b[0]
-------------| /----------------
|/
Where the buf type symbol is the WIRE primitive.
Alternatively if you are using Blocks instead of symbols you an use Conduits
and set the properties of the mappers correctly. This information is
available in the online help for Quartus.
- Subroto Datta
Altera Corp.
"chi" <chi_huageng@yahoo.com> wrote in message
news:232ce803.0402131341.2dc8763a@posting
.google.com...
> Hi all,
>
> For example, I want to connect a[1] to b[0], where both a and b are
> buses in the current file of block editor. How to do that? Can you
> show documents on how to use block editor?
>
> I've been using VHDL for years, graphical design entry of QuartusII
> looks wired to me. I'm trying to get familar with it.
>
> Thanks a lot.
>
> Chi
Article: 66216"prav" <praveenkn123@yahoo.com> wrote in message news:863df22b.0402122322.77eac1ee@posting.google.com... > Hi Vladislav, > > As u told that optoisolator dosen't support high clock frequency . > Are there any other alternatives to replace a opto isolator so that i > can work at higher frequency. www.analog.com optical isolation for data rates 100M antti www.openchip.orgArticle: 66217
I had planned to generate an ADC clock from a DCM block in my VirtexII. I'm told the jitter on the DCM output clock is likely to degrade the ADC performance. The ADC clock is 56 MHz. The source clock will be 8MHz so I need 7x in the DCM. Is the jitter really a major problem at 56MHz? Thanks, ClarkArticle: 66218
>Is the jitter really a major problem at 56MHz? That depends upon YOUR application. Get out an old envelope and do some rough calculations. What's the fastest rise time of a signal you will be looking at? As an estimate, use the highest frequency sine wave at max amplitude. How many pico-seconds does your clock need to be off in order to make a 1 LSB change in the reading? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 66219
Last time I checked, the jitter when using the CLKFX output was surprisingly large. I needed to multiply by 4X so I cascaded two DCMs together, using the CLK2X outputs, which had much less jitter. I don't know if CLKFX jitter has been improved since I last checked. -Kevin "Clark Pope" <cepope@mindspring.com> wrote in message news:FksXb.5284$hm4.3214@newsread3.news.atl.earthlink.net... > I had planned to generate an ADC clock from a DCM block in my VirtexII. I'm > told the jitter on the DCM output clock is likely to degrade the ADC > performance. The ADC clock is 56 MHz. The source clock will be 8MHz so I > need 7x in the DCM. > > Is the jitter really a major problem at 56MHz? > > Thanks, > Clark > >Article: 66220
Depends on the application, but off-hand, the answer is most likely it will
result in an unacceptably high noise floor at 56 MHz assuming your bandwidth
requirements are such that a 56 MHz sampling clock is needed.
Clark Pope wrote:
> I had planned to generate an ADC clock from a DCM block in my VirtexII. I'm
> told the jitter on the DCM output clock is likely to degrade the ADC
> performance. The ADC clock is 56 MHz. The source clock will be 8MHz so I
> need 7x in the DCM.
>
> Is the jitter really a major problem at 56MHz?
>
> Thanks,
> Clark
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 66221May be that article somehow explains discussed odd situation concerning Spartan-3 availability. http://www.digitimes.com/NewsShow/Article2.asp?datePublish=2004/02/13&pages=A1&seq=1Article: 66222
"Thomas Womack" <twomack@chiark.greenend.org.uk> wrote in message news:qGi*MtWcq@news.chiark.greenend.org.uk... > Is http://www.parallax.com/detail.asp?product_id=60002 a sensible > thing to buy as an introduction to working with FPGAs? If not, can > you recommend anything else at the same kind of price with no-charge > development tools? > > The parallax board seems to be reasonably priced, has a Stratix core > so you get the DSP components and the large memories, lots of header > pins to connect to externals (DRAM is presumably impractical on a > breadboard, for signal-integrity reasons and the difficulty of putting > 184-pin sockets on a breadboard if nothing else, but I can't see why > SRAM and an ADC or DAC wouldn't work). > > Is it at all conceivable to get VGA out of something like that, or > would the signals degrade hopelessly on their way from the headers > to the 15-pin plug for the monitor? > > Tom www.digilentinc.com something like D2E + DIO1 boards The board has vga out.Haven't tried vga on mine yet. https://digilent.us/Sales/Product.cfm?Prod=D2E-DIO1 Or whatever their newest equivalent is. D2SB + DIO5 https://digilent.us/Sales/Product.cfm?Prod=D2FT-DIO5 OR if a smaller fpga is fine https://digilent.us/Sales/Product.cfm?Prod=PEGASUS Looks like they are finally getting the boards out they've been talking about for a while. Pity they went for 6 pin for the jtag.If it had been 20 pin, could have made it a debugger(for micros) as well. Or the other one is http://www.burched.com.au/ http://www.burched.biz/b5xsvp.html Wonder when his Altera board is going to be out ? AlexArticle: 66223
Sounds like you already selected the layer count. I'd recommend the following two books if you haven't already looked at them. They are both right on the money. 1. High-Speed Digital Design: A Handbook of Black Magic by Howard Johnson (Title is a misnomer, it is not black magic, and it is not presented as black magic.) 2. High-Speed Digital System Design: A Handbook of Interconnect Theory and Design Practices by Stephen H. Hall (Author), Garrett W. Hall (Author), James A. McCall Reducing layers often results in voids on the plane layers which leads to impedance mismatches and cross talk. Using ADCs, as well as digital ICs that have VCCOs different than internal VCCs can lead to less than ideal use of plane islands. Add to this some application notes put out by vendors that give bad advice (when compared to the tried, true, and tested advice given in the above two books), and you can run into trouble. I.e., you should always follow application notes regarding layout recommendations. Some are on the money, others mis-apply rules of thumb. Also watch for board designers that use via anti-pads that are so large on the plane layers that they result in copper voids (see above). Finally, if you can, get a digital scope with a FET probe and use very low impedance grounds for the probes for lab validation of your simulations and calculations (final sanity check). "Kenneth Land" <kland1@neuralog1.com1> wrote in message news:<102q798km86rn0d@news.supernews.com>... > Hi William, > > Our fastest signals on the board will probably be the 32 bit SDRAM at > 100-120 MHz. Our ADC's are operating at 6 MSPS (10 bit samples). USB 2.0 is > operating at 30 MHz. Nios will match SDRAM. > > I need to look at the signals on an analog scope, but the logic analyzer is > showing very low jitter operation and the clocks (both input and PLL > generated output) look very clean and stable on my digital scope. The > boards are operating at 110 MHz for as many days as I care to let them, so > I'm fairly confident. > > If you stay tuned, I'm sure I'll have a fun emissions testing story in a > month or two. NTI was great help with our first board 3 years ago. I'm > sure they'll be a big help again. We've shipped the products to 40+ > countries since then with the biggest problem being that we once had to fax > the emissions report to a diligent customs official. > > Believe you me, my intimate intimate life-force-draining familiarity with > production realities and EMC/Safety regulations is why I'm drooling over > this new board. Lower parts count and layer count is key. Anyone who > understands joint probability can see why. > > Ken > > > > > "William Wallace" <msm30@yahoo.com> wrote in message > news:7e4865b7.0402130820.482bb3a6@posting.google.com... > > "Kenneth Land" <kland1@neuralog1.com1> wrote in message > news:<102ok9hpug47378@news.supernews.com>... > > > Hi Greg, > > > > > > I was thinking more in terms of SI rather than routing difficulty. > > > > > > In that case let me share how we handled that on only two signal layers. > (We > > > did to a split PWR plane, BTW) > > > > > > It was a challenge with all the pins and signals and we wound up using a > > > routing service. The company does nothing but apply a full up SPECTRA > > > auto-routing system as a service to others. They were so knowledgeable > and > > > helpful and the whole transaction was done by email and phone over a few > > > days. The price was incredible and now we'll save much more than their > fee > > > every batch of boards due to the fewer number of layers. > > > > > > Did you make it past emissions testing? At what rate do your signals > > change? How is signal integrety? Getting a few boards to work in the > > lab is not as tough as getting a design to work in production in > > different envirinments while meeting goverment regulations.Article: 66224
On 13 Feb 2004 19:19:07 -0800, pablobleyer@hotmail.com (Pablo Bleyer Kocik) wrote: >[Sorry to repost. Seems my news server screwed up.] > >Hello Lewin. Thanks for replying. > >larwe@larwe.com (Lewin A.R.W. Edwards) wrote in message news:<608b6569.0402130650.717890c2@posting.google.com>... >> Hi Pablo, >> >> Interesting product. Some comments: >> >> Lose the prototyping area. Bring the signals to headers. I'm not >> hacking stuff onto an eval board. > > Thanks, that is worthful. We were into the discussion of how valuable >was the prototyping area for some people. Another vote for headers. If one of them bears some relationship to a SODIMM socket, you could conceivably support SDRAM through a controller in the FPGA, for those who need it. Just a thought. - Brian
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z