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Hi, there: I need a bus-macro for spartan-2...It seems the Spartan-2 layout is so much different from Virtex-2, I am sure the corresponding bus macros is also different from Virtex-based. May I know how to obtain one? Best Regards, KelvinArticle: 66276
On Mon, 16 Feb 2004 16:22:27 -0000, "Jonathan Bromley" <jonathan.bromley@doulos.com> wrote: >"Bob Perlman" <bobsrefusebin@hotmail.com> wrote in message >news:csp13016toguahpob0fnon53r1jjms0qm1@4ax.com... > >> On Mon, 16 Feb 2004 10:16:17 -0000, "Jonathan Bromley" >> <jonathan.bromley@doulos.com> wrote: >> >hi PLD gurus - especially those with grey hair :-) > >> If for some reason Philip Freidin doesn't see your post, send him an >> e-mail. He was the father of the 29PL141. > >OK, I give in. Is there some kind of ex-AMD conspiracy >going on here? I already know that Peter Alfke was with >AMD for a while; Bob, unless I'm much mistaken, I attended >your presentation on proposals for the 29050 CPU at an AMD >FAE meeting; now you tell me about Philip Freidin... Will >all those who are *not* AMD alumni please stand up? :-) I believe it was Jerry Sanders who said in the early 70's that in the future, everyone would work at AMD for 15 minutes. It took me 6-1/2 years, but I finally fulfilled the 15-minute work requirement. By the way, there's an excellent AMD alumni Web site here: http://www.flamesite.org/ Bob Perlman Cambrian Design WorksArticle: 66277
Some references... Scott Keagy, Integrating Voice and data Networks, Cisco Press, 2000 ANSII / EIA/TIA-464-B-1996, Requirements for Private Branch Exchange (PBX) Switching Equipment. AT&T PUB 43801, Digital Channel Bank Requirements and Objectives, 1982 R2 Signalling, in case you're interested: ITU Q.400, Specifications of Signaling System R2: Definitions and Functions of Signals - Forward Line Signaling Equipment, 1993 ITU Q.421, Specifications of Signaling System R2 Line Signaling, Digital Version - Digital Line Signaling Code, 1993 ITU Q.422, Specifications of Signaling System R2 Line Signaling, Digital Version - Clauses for Exchange Line Signaling Equipment, 1993 ITU Q.440, Specifications of Signaling System R2 Inter-register Signaling - General, 1993 ITU Q.441, Specifications of Signaling System R2 Inter-register Signaling - Signaling Code, 1993Article: 66278
Hint: IOB's are not created by themselves. "Tobias Möglich" <Tobias.Moeglich@gmx.net> wrote in message news:4030F01F.92CDA398@gmx.net... > Hello > > I use Xilinx ISE 6.1 for synthesis. > I discovered in the floorplanner that there are used very much IOB's. > Even more than used IO pads. > Why that ?? Is it for the reason of timing constraints (for example > delays)?? > As far as I know, I haven't made any timing constraint in my design. > Is it possible not to use so many IOB's. > How can I tell ISE to do so ? > > > Greatings Tobi. >Article: 66279
Hi there, Anyone having weird memory access and alignment issues with hardware generated using EDK6.2 even automatically generated without revup? Cheers, Jon. Mike Wellington wrote: | All I know is that Xilinx customer support told me that EDK 3.2 and | EDK 6.1 are incompatible with each other. Oh this I know. Everything should in theory work but right now I am having to run my own Linux port with cacheing disabled under 6.1 and am tracing some weird alignment issues or somesuch other problem with certain accesses through the memory controller to SDRAM. I will get it this week I hope. Spent most of last week manually tracing the Linux startup process, validating every TLB entry by hand[0] and patching instructions with hexedit/gdb since hardware breakpoints still do not seem to be working correctly through xmd in that you cannot con after stopping properly. Sometimes I have seen potential cacheline corruption but I am not sure where the problem is yet and whether it is hardware flakiness or software not doing something it should be doing. However I have now created a consistent crash scenario where a particular structure used by the glibc rtld is being courrupted on the way up and am hopeful that I can this week track down exactly what causes it to get fscked. Jon. [0] So I now understand the ppc405 TLB handling code far more than I did even a week ago. I love doing this kind of thing sometimes.Article: 66280
I'd redesign it for a split but better yet get a bigger part (if possible) even if it means porting it to a different vendor. Cutting up a design into multiple pieces, even with tools that promise to do it, is dicey. You have timing issues, added real-estate as well as potential problems with scaling (if applicable). In addition, the design becomes bounded and dependent on the partition.Article: 66281
> An RTX2000 clone core is available from us in VHDL for FPGAs. A > C compiler is also available. The CPU runs at 20 MIPs in a > Xilinx Spartan. This is twice as fast as the original Harris > (Intersil) part, with an interrupt latency of 200ns before > starting useful work. I just read the online RTX2010 manual. Does the RTX2000 also have the multiply-and-accumulate logic? Do people buy these chips nowadays for DSP?Article: 66282
tushit wrote:
> I have a design which does not fit on my Altera Stratix device.
You may have some unused resources
like block ram and multiplier/dsp blocks
that could be used for logic.
Consider trying other synthesizers.
-- Mike Treseler
Article: 66283Hi, I am trying to configure 8 Virtex 2 Pros (V2P7) (with the same bitstream) on a single board. I will use the the Master Serial programming mode. Are there known issues which i need to worry about ? Any documentation available ? Prior Experience ? Thanks in advance, AdarshArticle: 66284
I suggest you read the data sheet. The DCM "manages" an incoming clock, so obviously there is a need for an input clock. And if you think that 84 divided by 1.5 is 66, then you also should also consult your calculator. Apparently it is way too easy to ask questions in this newsgroup... :-( Peter Alfke QiDaNei wrote: > > Hi, > I am confused at how to set DCM generic parameters on Xilinx FPGA, I > know the input clock is 84MHz, and I see my colleague set > > CLKDV_DIVIDE = 1.5 > CLKIN_PERIOD = 10 > > then it seems he can get 66MHz from output pin CLKDV. > > I am confused: Does 84MHz have any use here? It seems the actual > input clock frequency does not matter here, the output frequency is > totally depending on how you set these parameters. > > Then my question is what's the frequency of clk0? 84MHz or 100MHz? > > Thanks.Article: 66285
Don't treat the 7400 series as gospel. Those TTL-MSI circuits were defined with two constraints: 1. make them universal, so that only a limiyted number of different circuits needs to be built, 2. and fit them in a 16-pin apckage, without giving up the ability to expand. That was the rationale behind all those circuits (I know, I was there at the creation). Using the same constraints when implementing such functions in an FPGA does not make any sense at all. Peter Alfke -------------------------------- Hal Murray wrote: > > > I am using webpack 4.1 and trying to create a 74ls193. I first basically > >built it from scratch using the logic diagram from the TTL datasheet but it > >would not work correctly in a circuit. > > > Anyone have a solution or idea of how I could design a ls193 with either > >descrete logic (like I tried) or using the library counters? > > The party line is don't-do-that, Do something else, for example use > a different part. > > The basic rule is that you have to meet both setup and > hold times on all flip-flops in your design. That gets tricky > if you have a complicated clock distribution system. > > Xilinx FPGAs have a very low skew clock distribution system. They > promise that the hold time will be 0. (or really that the min prop > time will be enough to cover the hold time) That means you only > have to worry about the setup time. Their software is smart enough > to figure that out and tell you the max speed your design will > run at. > > Where are your up/down pulses coming from? If they come out of > a state machine (flip-flop), then you want to use the same clock > that drives that state machine to drive a counter, and use the > up/down signals to decide if your counter goes up, down, hold... > > It will all make sense after you get used to it. It's much > cleaner/simpler for high speed designs. > > -- > The suespammers.org mail server is located in California. So are all my > other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited > commercial e-mail to my suespammers.org address or any of my other addresses. > These are my opinions, not necessarily my employer's. I hate spam.Article: 66286
PREP was a naive attempt at standardized benchmarks for FPGAs and CPLDs. It became totally poisoned by super-aggressive marketing methods by some of the competing manufacturers, turning it into a sad joke. I consider my active participation (as one of the founders of the group) the most disappointing experience of my long carreer. Peter Alfke ============ Davide Anguita wrote: > > Hi all, > I'm looking for the PREP (Programmable Electronic Performance Cooperative) > benchmark. > Unfortunately, the site www.prep.org seems to be closed down... > > Does anyone know where to find the code (or e-mail me) ? > > Thanks in advance, > > -- Davide. > > anguita AT dibe.unige.itArticle: 66287
Peter,
I see your point exactly, but for the sake of testing I want to make
sure a suitable ls193 replacement works. I am only making one ttl chip at a
time and placing it in a working circuit comprised of many ttl chips. I have
done this with a ls670 I built in xilinx and a ls191. Which have both worked
fine in circuit.
I plan to slowly implement all the other ttl components until its all on
a single cpld.
An argument for placing everything on the cpdl at once is probably
justified, but I am a newbee and would like to take it in steps to make sure
that the individual parts work correctly before trying to debug something
very large. I feel that when all the parts work then I can adjust the whole
design to better fit or work in a cpld.
Again I am new to this (cpld) so I may have an old style rational.
Thanks,
Fred
"Peter Alfke" <peter@xilinx.com> wrote in message
news:40312592.890CC95A@xilinx.com...
> Don't treat the 7400 series as gospel.
> Those TTL-MSI circuits were defined with two constraints:
> 1.
> make them universal, so that only a limiyted number of different
> circuits needs to be built,
> 2.
> and fit them in a 16-pin apckage, without giving up the ability to expand.
>
> That was the rationale behind all those circuits (I know, I was there at
> the creation).
> Using the same constraints when implementing such functions in an FPGA
> does not make any sense at all.
> Peter Alfke
> --------------------------------
> Hal Murray wrote:
> >
> > > I am using webpack 4.1 and trying to create a 74ls193. I first
basically
> > >built it from scratch using the logic diagram from the TTL datasheet
but it
> > >would not work correctly in a circuit.
> >
> > > Anyone have a solution or idea of how I could design a ls193 with
either
> > >descrete logic (like I tried) or using the library counters?
> >
> > The party line is don't-do-that, Do something else, for example use
> > a different part.
> >
> > The basic rule is that you have to meet both setup and
> > hold times on all flip-flops in your design. That gets tricky
> > if you have a complicated clock distribution system.
> >
> > Xilinx FPGAs have a very low skew clock distribution system. They
> > promise that the hold time will be 0. (or really that the min prop
> > time will be enough to cover the hold time) That means you only
> > have to worry about the setup time. Their software is smart enough
> > to figure that out and tell you the max speed your design will
> > run at.
> >
> > Where are your up/down pulses coming from? If they come out of
> > a state machine (flip-flop), then you want to use the same clock
> > that drives that state machine to drive a counter, and use the
> > up/down signals to decide if your counter goes up, down, hold...
> >
> > It will all make sense after you get used to it. It's much
> > cleaner/simpler for high speed designs.
> >
> > --
> > The suespammers.org mail server is located in California. So are all my
> > other mailboxes. Please do not send unsolicited bulk e-mail or
unsolicited
> > commercial e-mail to my suespammers.org address or any of my other
addresses.
> > These are my opinions, not necessarily my employer's. I hate spam.
Article: 66288Jonathan, don't get too impatient too fast. Today is a holiday in this part of the world, where we celebrate the birthday of that great leader who liberated us from the Brits. So most of us are out carousing. :-) I have the 29PL141 Handbook in my hot little hand ( hundreds of pages, including assembler and app notes). I could easily fax you the 6-page data sheet, it you send me your fax#. Cheers Peter Alfke ========================== Jonathan Bromley wrote: > > "Bob Perlman" <bobsrefusebin@hotmail.com> wrote in message > news:csp13016toguahpob0fnon53r1jjms0qm1@4ax.com... > > > On Mon, 16 Feb 2004 10:16:17 -0000, "Jonathan Bromley" > > <jonathan.bromley@doulos.com> wrote: > > >hi PLD gurus - especially those with grey hair :-) > > > If for some reason Philip Freidin doesn't see your post, send him an > > e-mail. He was the father of the 29PL141. > > OK, I give in. Is there some kind of ex-AMD conspiracy > going on here? I already know that Peter Alfke was with > AMD for a while; Bob, unless I'm much mistaken, I attended > your presentation on proposals for the 29050 CPU at an AMD > FAE meeting; now you tell me about Philip Freidin... Will > all those who are *not* AMD alumni please stand up? :-) > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services > > Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK > Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com > Fax: +44 (0)1425 471573 Web: http://www.doulos.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated.Article: 66289
Fredk wrote: > Peter, > > I see your point exactly, but for the sake of testing I want to make > sure a suitable ls193 replacement works. I am only making one ttl chip at a > time and placing it in a working circuit comprised of many ttl chips. I have > done this with a ls670 I built in xilinx and a ls191. Which have both worked > fine in circuit. > > I plan to slowly implement all the other ttl components until its all on > a single cpld. That's impressive patience, but it is a proven-safe pathway. > > An argument for placing everything on the cpdl at once is probably > justified, but I am a newbee and would like to take it in steps to make sure > that the individual parts work correctly before trying to debug something > very large. I feel that when all the parts work then I can adjust the whole > design to better fit or work in a cpld. Understood. > > Again I am new to this (cpld) so I may have an old style rational. Taking a close look at the '193, it CAN be implemented in a CPLD, but not in a natural/efficent way. I see two choices : a) Keep with your method, but when you strike a device like a '193, try and change it to TWO TTL devices, a GATE and a Sync counter '161 series You can verify the new combination, and also easily replace it with a CPLD. b) If you _must_ duplicate the '193, you will need to create what they do, to merge clocks. ( peek at the Fairchild 74F193 data ) This needs a cross-coupled latch, to set DIRECTION on the Falling Edge, and an AND gate to merge the two clocks. Note the '193 requires that the inactive clock is HIGH, and has min pulse widths on dirn change that are > same direction. -jgArticle: 66290
Jonathan Bromley wrote: > Key suggestion: DON'T supply one FPGA's clock from an output > on the other FPGA. Instead, be sure to supply BOTH FPGA's > clocks from the same source. The worst-case skew between the > two FPGA's clock buffer delays should be very much smaller > than propagation delays of each FPGA's output pads; > if this is true, you will have no problems with hold time. I wonder about this because I'm looking into moving data across device boundaries for a project. The approach I am favoring at the moment is to have a source-synchronous bus + control + clock leave device A and enter device B. The output clock would be generated via DDR method within the IOB. It would seem to me that --assuming careful PCB layout-- this method might be preferable to having an external clock generator feed devices A and B. Am I missing something? I can see that with proper DCM configuration it truly doesn't matter which way you go (or it shouldn't)? -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 66291
The sample rate depends on the speed grade of the part, especially the block RAM timing, and how full the part already is without ChipScope. Fairly full designs cause larger routing delays. You'll have to build your design with ChipScope to see if it meets your timing specs.Article: 66292
IOB's are created by inputs and outputs of the top level module in ISE. Normally you can account for all of the IOB's from the inputs and outputs of the design. The only other possibility is that you have turned on "Use Bonded I/Os" in the place and route options (not default) which allows use of unassigned pads for route through. If you're seeing IOB's used in the floorplanner, you may have some LOC constraints assigning internal logic incorrectly into IOB's.Article: 66293
One of the V2P7 chips is the master and drives CCLK to the SPROM and to the other V2P7s, the other seven V2P7s must be in slave serial mode and receive CCLK. Al Din pins are tied together and thus receive the same bitstream from the SPROM.. Peter Alfke Adarsh Kumar Jain wrote: > > Hi, > I am trying to configure 8 Virtex 2 Pros (V2P7) (with the same bitstream) on > a single board. > I will use the the Master Serial programming mode. > Are there known issues which i need to worry about ? > Any documentation available ? Prior Experience ? > Thanks in advance, > AdarshArticle: 66294
In most FPGA designs I've done there's been an external reset input which has been used as the power on reset mechanism. I'm now doing a design for a Spartan-3 with no external reset, and I've some signals I need pre-set so I need to use the internal asynch reset mechanism. I've read here in the past of the problems of using the GSR, but in this design there are synchronous enables which control the data flow. The functionality of these means there shouldn't be any timing problems out of reset. I was under the impression that if you had a top level signal which was used in the usual VHDL asynchronous reset template manner, the synthesis tools would pick it out and connect it to the GSR net. I'm using XST and getting .. "Signal <rst> is used but never assigned. Tied to value 0." So what do I need to do to get 'rst' connected to the GSR net? I've spent a fair bit of time searching the Xilinx site/docs and googling this group with no results. It seems to be one of those things that I should probably know, but just can't find anywhere. Thanks for any pointers, Nial.Article: 66295
"Davka" <mygarbagepail@hotmail.com> wrote in message news:<T%XXb.70$pM3.121810@news.uswest.net>... > I want to bring my knowledge about Forth processors up to date, so I'm > posting some questions. > > Who is currently selling Forth processors? Dr. Ting has a few thousand MuP21 and MuP21h VLSI chips that date back to 94 and 95. He was always charging about what they cost him to make but you might be able to get a deal on them now that they are getting rather old. He also still has some stock on RTX parts and kits. His latest projects include P8,P16,P24,P32,and P64. He has a nice development board with a P32 that uses about 75% of the FPGA on the board so there is room for adding custom instructions or custom I/O hardware to the design. The board also has RAM and FLASH, a color LCD interface and LCD and software for a PC for development. I believe that board is about $300 and has a 400Mhz part. Patriot has various models of their chip ranging from 100 to 350Mhz or so. There is a family of tiny 4Mhz 4-bit bus 16-bit Forth chips manufactured in Europe. These and other Forth chips are listed on my Forth chips page referenced in another post. > What happened to forthchip.com? > > Is there a community that is actively involved in discussing and/or > developing FPGA-based Forth chips, or more generally, stack > machines? There are mailing lists but the hardware list has been silent for a long time. There are discussions sometimes in #forth or #FIGUK chat rooms, even in c.l.f from time to time, but mostly people talk about Forth software not hardware. > Has anyone done any substantial DSP work in Forth? Are there libraries > of code available? > How about hardware Forth implementations that include dedicated DSP > hardware? You might also consider that there are Forth systems that run on DSP hardware. These are not Forth chips per se but might meet your needs. The Harris RTX 2001 had the one cycle multiply-accumulator, many FPGA can support the inclusion of single cycle multiply-accumulate circuites. Some can hold quite a lot of them as you probably know. P32 does 32x32->64 and 64/32 but with multiply and divide steps. But with larger FPGA specialized DSP circuits or coprocessors can be added without too much trouble. I can't say too much at this time about our current work in custom VLSI Forth processors and they are not available for public sale anyway. Best WishesArticle: 66296
Hi Ian, Ian wrote: > I have a simple partial reconfig design. Under ISE6 SP2 it is only > routable using fpga editor, command line PAR fails with the message > 'abnormal program termination'. Not a big problem as fpga editor does > the job! > > But after installing SP3, command line PAR and fpga editor fail > reporting the design is unroutable. The problem is confirmed as being > SP3 as I have now uninstalled it and the design routes OK. > > If anyone is having similar problems routing a design you may want to > do the same. I don't know if you saw the thread about this a few days ago, I had some similar inexplicable problems with the tools producing invalid NCDs, that would crash the FPGAeditor and bitgen tools. The bottom line seems to be that there are still a lot of issues to be worked out! I'm sorry I don't have any concrete suggestions for your problem, but it does make me wonder... Would there be interest in a partial reconfiguration research mailing list? Or, is there already such a thing? Our department has a list-server configured and ready for use (I currently run the microblaze uclinux list on it). I'd be happy to setup and maintain such a list, if there was interest. Regards, JohnArticle: 66297
Jim Granville wrote: <snip> > b) If you _must_ duplicate the '193, you will need to create what they > do, to merge clocks. ( peek at the Fairchild 74F193 data ) > This needs a cross-coupled latch, to set DIRECTION on the Falling Edge, > and an AND gate to merge the two clocks. > Note the '193 requires that the inactive clock is HIGH, and has min > pulse widths on dirn change that are > same direction. To show your request was not unreasonable, I should have added that I actually did this in a 22V10 a while ago, for an 'electronic thumbwheel', where you have UP and DOWN buttons above and below a 7 segment display. -jgArticle: 66298
> Is there a community that is actively involved in discussing and/or > developing FPGA-based Forth chips, or more generally, stack > machines? > Tha Java Virtual Machine is stack based. There are some projects to build a 'real' Java machine. You can find more information about a solution in an FPGA (with VHDL source) at: http://www.jopdesign.com/ It is sucessfully implemented in Altera ACEX 1K50, Cyclone (EP1C6) and Xilinx Spartan2. MartinArticle: 66299
Jim,
Thanks for the input on this... I have started to make a JK flip flop
with set and clear to see if I can make it work ;)
Fred
"Jim Granville" <no.spam@designtools.co.nz> wrote in message
news:5qbYb.24594$ws.3031929@news02.tsnz.net...
> Jim Granville wrote:
> <snip>
> > b) If you _must_ duplicate the '193, you will need to create what they
> > do, to merge clocks. ( peek at the Fairchild 74F193 data )
> > This needs a cross-coupled latch, to set DIRECTION on the Falling Edge,
> > and an AND gate to merge the two clocks.
> > Note the '193 requires that the inactive clock is HIGH, and has min
> > pulse widths on dirn change that are > same direction.
>
> To show your request was not unreasonable, I should have added that
> I actually did this in a 22V10 a while ago, for
> an 'electronic thumbwheel', where you have UP and DOWN buttons above
> and below a 7 segment display.
> -jg
>
>
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