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Nial Stewart <nial@nialstewartdevelopments.co.uk> wrote: : > Any logic signal can drive the .GSR input of the STARTUP_SPARTANX. You can : > generate it internally or connect to an external pin. Where's the problem? : I don't want to have to drive it. GSR is driven as part of the : power up process and I want this to drive my reset net. : Previously using Leonardo I've been able to have a reset : net declared as a signal with some directives to tell : Leonardo to connect this net to the GSR. : I was hoping that XST would do the same thing, but it doesn't : seem to. As I said elsewhere in the thread Simplify has a : directive "xc_isgsr" which looks like it's doing this, but : there's no equivalent XST dierective listed. You can access glbl.GSR in you testbench... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 66376
"Ray Andraka" <ray@andraka.com> wrote in message news:40336236.A85B6B7F@andraka.com... > ROC is a place holder and simulation primitive. It should appear in > your edif netlist, then the xilinx mapper removes it and connects the > net to GSR. It is doing what you want. You can check the xilinx > results in FPGA editor to convince yourself. Thanks Ray, this was the confirmation I was looking for. Previously I think the reset net had to reset _all_ flip flops in the design for the synthesis tools to pick it up and connect it to GSR. Do you know if these conditions still apply if using ROC? I had looked in FPGA editor, but am not _that_ familiar with it and wasn't sure what it was telling me. Time to read the tutorial. Thanks again, Nial.Article: 66377
I was wondering as to are there any good resources online /and or some tools to learn about formal design verification of large complex designs like for instance a processor. Also a good paper reading list in the same field would be great as there are a tons of papers in this field on the ACM portal and I have no clue where to start from. Thanks --------------------------------- Kartik Krishnan kkrishnan[at]wisc.edu www.cae.wisc.edu/~kartik ---------------------------------Article: 66378
> You can access glbl.GSR in you testbench... But what about in real life, which is what I'm worried about. The STARTUP_SPARTAN3 only has an input port, this is used to drive GSR. I need something to drive my reset net, ie GSR -> rst. Nial.Article: 66379
"John Plows" <s22838 at rmc dot ca> wrote in message news:403378f2@news.kos.net... > Hello > > A collegue and I are trying to implement a 256 point FFT on a Virtex-II. > The problem we are having is finding a way to transfer the calculated FFT > data off the FPGA so we can display it (preferably in Matlab). > > If anyone knows of a tool for uploading/downloading to/from the block > RAM on the Virtex-II, please let us know. > If anyone has any information on how to interface to the 16Mb flash > memory card on our board, it would be greatly apreciated. > Finally, any tip on how to implement this project would be helpful. We > are at our wits end trying to figure out a way of displaying our FFT > function and testing its accuracy. John, What sort of bandwidth requirements do you have? What physical interface do you have with the FPGA? I built a USB interface for my own debug use, this connects to a header and can be used to access internal registers/ ram or whatever you want. A couple of times this has been invaluable. Have a look at the downloads page of my web site for more details. Nial. ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design www.nialstewartdevelopments.co.ukArticle: 66380
"Nicky" <Miaz371240@austromail.at> wrote in message news:c7068a2e.0402180404.71afeaa@posting.google.com... > Hello, > > I have to design a universal PCI card according to PCI spec 2.2 with > 33Mhz and 32 pins. However for several reasons I have to use a FPGA > that is not 5V but only 3.3V tolerant. Since nearly all motherboards > just offer 5V slots I have to make this card somehow 5V compliant. I > thought of using a quickswith from IDT. Is this a good idea? What are > the things I have to take care of when using this method? Are there > any other ways to make my card 5V compliant? > > thanks+regards, > Nicky Nicky, do a google groups search on this newsgroup for some discussions on this. My Cyclone PCI board (details on web site) uses Quickswitches and appears to work flawlessly. This approach isn't actually compliant with the PCI spec which stipulates 1 load per net, but I met the capacitance limits and inspection shows clean transitions on the bus. Hope this helps, Nial ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design www.nialstewartdevelopments.co.ukArticle: 66381
"John Plows" <s22838 at rmc dot ca> wrote in message
news:403378f2@news.kos.net...
> Hello
>
> A collegue and I are trying to implement a 256 point FFT on a Virtex-II.
> The problem we are having is finding a way to transfer the calculated FFT
> data off the FPGA so we can display it (preferably in Matlab).
>
> If anyone knows of a tool for uploading/downloading to/from the block
> RAM on the Virtex-II, please let us know.
Does the Xilinx jtag debugger allow it?
> If anyone has any information on how to interface to the 16Mb flash
> memory card on our board, it would be greatly apreciated.
----------
Without any information on what your board is and what it has on it, you're
not going to get a lot of useful help.
If I assume you have a standalone board with no standard interface (since if
it has PCI, a serial port, or USB why would you be asking) the best I advice
I can give is to look at the parallel printer port on your PC. This used to
be an easy way to get data to/from a custom board. It has at least 8 "data"
bits as well as some signalling bits, is bi-directional (well, most are) and
I seem to recall it uses standard logic levels. So it may be a matter of
jury rigging a cable from your PC's printer port to your board, implementing
a simple interface in the FPGA, and writing some PC code to read data from
the printer port.
> Finally, any tip on how to implement this project would be helpful.
We
> are at our wits end trying to figure out a way of displaying our FFT
> function and testing its accuracy.
>
> Anythign anyone can tell us is apreciated! Thanks!
>
> John Plows & Andrew Dalrymple
> Royal Military College of Canada
How's Kingston these days?
------
Ron Huizen
BittWare
Article: 66382
"Florian-Wolfgang Stock" <f.stock@tu-bs.de> wrote in message
news:40334504$0$17577$9b4e6d93@newsread4.arcor-online.net...
> int m,u,e=0;float l,_,I;main(){for(;1840-e;putchar((++e>907&&942>e?61-m:u)
> ["\t#*fg-pa.vwCh`lwp-e+#h`lwP##mbjqloE"]^3))for(u=_=l=0;79-(m=e%80)&&
> I*l+_*_<6&&26-++u;_=2*l*_+e/80*.09-1,l=I)I=l*l-_*_-2+m/27.;}
Nice piece of code and it even compiles and works :) I am not sure I fully
understand the output though.. :)
/Mikhail
--
To reply directly:
matusov at square peg ca
(join the domain name in one word and add a dot before "ca")
Article: 66383Nial Stewart <nial@nialstewartdevelopments.co.uk> wrote: : > You can access glbl.GSR in you testbench... : But what about in real life, which is what I'm : worried about. : The STARTUP_SPARTAN3 only has an input port, : this is used to drive GSR. Inn real life, GSR is driven when the FPGA boots. For simulation you drive or force it. Wher's the problem? Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 66384
Problem is that no matter how you re-sample it, you are sending multiple data bits (the counter output word) across clock domains, and you have the potential of getting incorrect data. I faced a similar problem, and I chose to convert the counter output to grey code, sample it in the new clock domain, and then convert back to binary. With grey encoding, only one bit changes at a time as you count up or down, so you cannot get incorrect data, even when there is a race condition when you re-sample. Barry Brown "prav" <praveenkn123@yahoo.com> wrote in message news:863df22b.0402172352.5886ed1c@posting.google.com... > hi all, > > I have a counter running at 50 Mhz . Now i have to sample that counter > at 77 Mhz. > > My question is can i sample the counter running at 50 mhz directly > with 77 mhz clock or should i synchronize the 50 mhz counter to 77 mhz > clock domain and then only sample it. > > what are the effects if i don't the sample the 50 Mhz counter and i > directly sample with 77 Mhz. > > rgds, > pravArticle: 66385
"Nial Stewart" <nial@nialstewartdevelopments.co.uk> wrote in message news:40337c46$0$8980$fa0fcedb@lovejoy.zen.co.uk... > > > ROC is a place holder and simulation primitive. It should appear in > > your edif netlist, then the xilinx mapper removes it and connects the > > net to GSR. It is doing what you want. You can check the xilinx > > results in FPGA editor to convince yourself. > I had looked in FPGA editor, but am not _that_ familiar with > it and wasn't sure what it was telling me. > > Time to read the tutorial. I've built the design with the ROC module driving rst. In the floorplanner if I do a search for Net rst, highlight it then look for all logic loading that net I get 491 flip flops. There are 1372 slice flip-flops in the design, and many that aren't loading rst are asynchronously reset in the code. You can easily find flip flos in the floor plan that aren't selected. I'm not happy this is doing what I want it to. When I use the counter reset mechanism as discussed elsewhere in the thread and do a search for rst I get 15 nets. Selecting these and doing a search for then selecting logic loading these nets gives 1558 symbols, and I can't see a flip_flop on the floorplan that's not selected. I'll stick with this method unless I can work out why the GSR implementation isn't working. Did Ray actually give advice that was wrong? >:-0 Nial.Article: 66386
I have added preserve_signal attributes to some signals in the VHDL source codes, and got the following warning messages in Leornado : WARNING: The value of an attribute is being overwritten: WARNING: On object named: clk WARNING: Attribute name: preserve_signal WARNING: Old Value: true WARNING: New Value: <NOT SET> These warnings do not apply to all preserve_signal attribute signals. Do you know what may have caused these warnings to appear ? Thanks. KennethArticle: 66387
"Uwe Bonnes" <bon@elektron.ikp.physik.tu-darmstadt.de> wrote in message news:c104o6$j54$1@news.tu-darmstadt.de... > Nial Stewart <nial@nialstewartdevelopments.co.uk> wrote: > : > You can access glbl.GSR in you testbench... > > : But what about in real life, which is what I'm > : worried about. > > : The STARTUP_SPARTAN3 only has an input port, > : this is used to drive GSR. > > Inn real life, GSR is driven when the FPGA boots. For simulation you drive > or force it. Wher's the problem? GSR isn't connected to the reset that I've used throughout my code to asynchronously reset flip flops on power up. (At least I can find nothing in the tools to say it's been connected, and as I said there's no XST directive to indicate which net should be connected to GSR). Nial.Article: 66388
Hi there, Added configuration options to Linux config.in to control (actual names are slightly different for internal naming convention): CACHE_MODE - Toggle these CACHE_REAL - Real mode cacheing enabled CACHE_KERNEL - Kernel pages cacheing enabled CACHE_USER - User pages cacheing enabled The system now boots if I disable all cacheing and it seems to be ok. However this only partially helps me and I still welcome input. Anyone know of any particular reason why this Memec Insight board would dislike cacheing being enabled especially with EDK6.1 hardware? I would love to hand validate the cache contents and this kind of thing but the Xilinx documentation is not good. The Xilinx XMD FAQ says that icachestartadr is a command when in fact it is a parameter to ppcconnect and then fails to provide an actual example of its use. *Sigh*. Cheers, Jon.Article: 66389
"MM" <mbmsv@yahoo.com> writes:
> "Florian-Wolfgang Stock" <f.stock@tu-bs.de> wrote in message
> news:40334504$0$17577$9b4e6d93@newsread4.arcor-online.net...
>
>> int m,u,e=0;float l,_,I;main(){for(;1840-e;putchar((++e>907&&942>e?61-m:u)
>> ["\t#*fg-pa.vwCh`lwp-e+#h`lwP##mbjqloE"]^3))for(u=_=l=0;79-(m=e%80)&&
>> I*l+_*_<6&&26-++u;_=2*l*_+e/80*.09-1,l=I)I=l*l-_*_-2+m/27.;}
>
> Nice piece of code and it even compiles and works :) I am not sure I fully
> understand the output though.. :)
the part with the email address is obvious, the thing around is called
mandelbrot-set (in german also called "Apfelmaennchen") - And no, I
havnt implemented it yet on a fpga (but its just some complex
calculation, so it should not be difficult :)
Florian
--
int m,u,e=0;float l,_,I;main(){for(;1840-e;putchar((++e>907&&942>e?61-m:u)
["\t#*fg-pa.vwCh`lwp-e+#h`lwP##mbjqloE"]^3))for(u=_=l=0;79-(m=e%80)&&
I*l+_*_<6&&26-++u;_=2*l*_+e/80*.09-1,l=I)I=l*l-_*_-2+m/27.;}
Article: 66390Nial Stewart wrote: > > I've built the design with the ROC module driving rst. > > In the floorplanner if I do a search for Net rst, highlight it then > look for all logic loading that net I get 491 flip flops. > There are 1372 slice flip-flops in the design, and many that > aren't loading rst are asynchronously reset in the code. > You can easily find flip flos in the floor plan that aren't > selected. > > I'm not happy this is doing what I want it to. > > When I use the counter reset mechanism as discussed > elsewhere in the thread and do a search for rst I > get 15 nets. Selecting these and doing a search for > then selecting logic loading these nets gives 1558 symbols, > and I can't see a flip_flop on the floorplan that's > not selected. > > I'll stick with this method unless I can work out why > the GSR implementation isn't working. > > Did Ray actually give advice that was wrong? I may be mistaken, but I thought that *all* FFs were *always* driven by the global reset signal. By specifying in your code the async reset, you can make the simulation match the chip and you can control whether the FF is set vs. reset. Am I mistaken about this? Can the chip remove the GSR from FFs? Maybe I am confusing the GSR which can be controlled by the user with a power on reset... -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 66391
"Sander Vesik" <sander@haldjas.folklore.ee> schrieb im Newsbeitrag
news:1077074083.882919@haldjas.folklore.ee...
> In comp.arch Martin Schoeberl <martin.schoeberl@chello.at> wrote:
> > > Is there a community that is actively involved in discussing
and/or
> > > developing FPGA-based Forth chips, or more generally, stack
> > > machines?
> > >
> >
> > Tha Java Virtual Machine is stack based. There are some projects
to
> > build a 'real' Java machine. You can find more information about a
> > solution in an FPGA (with VHDL source) at:
http://www.jopdesign.com/
> >
> > It is sucessfully implemented in Altera ACEX 1K50, Cyclone (EP1C6)
and
> > Xilinx Spartan2.
>
> It would be intresting to see results for a version that cached the
> top of the stackand used a more realistic memory interface
>
Hallo Sander,
In this design the stack is cached in a multi level hirarchy:
TOS and TOS-1 are implemented as register A and B. The next level of
the stack is local memory that is connected as follows: data in is
connected to A and B, the output of the memory to the input of
register B.
Every arithmetic/logical operation is performed with A and B as source
and A as destination. All load operations (local variables, internal
register, external memory and periphery) result in the value loaded in
A. Therefore no write back pipeline stage is necessary. A is also the
source for store operations. Register B is never accessed directly. It
is read as implicit operand or for stack spill on push instructions
and written during stack spill and fill.
This configuration allows following operation in a single pipeline
stage:
ALU operation
write back result
fill from or spill to the stack memory
The dataflow for a ALU operation is:
A op B => A
stack[sp] => B
sp-1 => sp
for a 'load' operation:
data => A
A => B
B => stack[sp+1]
sp+1 => sp
An instruction (except nop type) needs either read or write access to
the stack ram. Access to local variables, also residing in the stack,
need simultaneous read and write access. As an example, ld0 loads the
memory word pointed by vp on TOS:
stack[vp+0] => A
A => B,
B => stack[sp+1]
sp+1 => sp
This configuration fits perfect to the block rams with one read and
one write port, that are common in FPGAs. A standard RISC CPU needs
three data ports (two read and one write) to implement the register
file in a ram. And usually one more pipeline stage for the ALU result
to avoid adding the memory access time to the ALU delay time. And for
single cycle execution you need a lot of muxes for data forwarding.
As summary: In my opinion a stack architecture is a perfect choice for
the limited hardware resources in an FPGA.
About the 'more realistic memory interface':
I don't see the problem. The main memory interface is a separate block
and currently there are three different implementations for different
boards: a low cost version with slow 8 bit ram, a 32 bit interface for
fast async. ram and Ed Anuff added a 16 bit interface for the Xilinx
version on a BurchED board. Feel free to implement your interface of
choice (SDRAM,...).
Sorry for the long mail, but I could not resist to 'defend' my design
;-)
Martin
Article: 66392fox@ultratechnology.com (Jeff Fox) wrote in message news:<4fbeeb5a.0402161414.66daa9d7@posting.google.com>... > "Davka" <mygarbagepail@hotmail.com> wrote in message news:<T%XXb.70$pM3.121810@news.uswest.net>... > > I want to bring my knowledge about Forth processors up to date, so I'm > > posting some questions. > > > > Who is currently selling Forth processors? > > Dr. Ting has a few thousand MuP21 and MuP21h VLSI chips that date > back to 94 and 95. He was always charging about what they cost him to > make but you might be able to get a deal on them now that they are > getting rather old. He also still has some stock on RTX parts and > kits. > > His latest projects include P8,P16,P24,P32,and P64. He has a > nice development board with a P32 that uses about 75% of the FPGA > on the board so there is room for adding custom instructions or > custom I/O hardware to the design. The board also has RAM and > FLASH, a color LCD interface and LCD and software for a PC for > development. I believe that board is about $300 and has a 400Mhz > part. > > Patriot has various models of their chip ranging from 100 to 350Mhz > or so. There is a family of tiny 4Mhz 4-bit bus 16-bit Forth chips > manufactured in Europe. These and other Forth chips are listed on > my Forth chips page referenced in another post. > > > What happened to forthchip.com? > > > > Is there a community that is actively involved in discussing and/or > > developing FPGA-based Forth chips, or more generally, stack > > machines? > > There are mailing lists but the hardware list has been silent for > a long time. There are discussions sometimes in #forth or #FIGUK > chat rooms, even in c.l.f from time to time, but mostly people > talk about Forth software not hardware. > > > Has anyone done any substantial DSP work in Forth? Are there libraries > > of code available? > > How about hardware Forth implementations that include dedicated DSP > > hardware? > > You might also consider that there are Forth systems that run on > DSP hardware. These are not Forth chips per se but might meet your > needs. > > The Harris RTX 2001 had the one cycle multiply-accumulator, many > FPGA can support the inclusion of single cycle multiply-accumulate > circuites. Some can hold quite a lot of them as you probably know. > P32 does 32x32->64 and 64/32 but with multiply and divide steps. > But with larger FPGA specialized DSP circuits or coprocessors can > be added without too much trouble. > > I can't say too much at this time about our current work in custom > VLSI Forth processors and they are not available for public sale > anyway. > > Best Wishes Corrections: The RTX 2000 had two 16-bit 256 element deep stacks (Return & Data), a 2-4 cycle interrupt response time, and a bit-mutiply instruction which could perform a complete general purpose multiply in 16-cycles. It was rated a 8 MHz (but they could easily run at 10 MHz [which meant it took a 20 MHz clock] at least at room temperatures). The RTX 2010 had all of the above, plus a one-cycle hardware 16-bit multiply, a one-cycle 16-bit multiply/accumulate, and a one-cycle 32-bit barrel shift. This was the version that Harris/Intersil based the radhard version upon, which NASA and APL (Applied Physics Lab in Columbia, MD) used for its space missions. They both still have a stash left, the last that I heard. The RTX 2001 was a watered down version which was basically the 2000, but with only 64 element deep stacks. It was intended (according to Harris) to be a cheaper/faster alternative to the 2000, but like the Celeron vs the Pentium, if you can get the real thing at basically the same price, why use the neutered version? Plus, the reduction of stacks from 256 elements to 64 element greatly reduced the ability to do multi-tasking and stack switching. I used the RTX 2000/2010 extensively when I worked at NASA GSFC Goddard Space Flight Center in Greenbelt, MD) from 1979-1994. I hope this helps set the history straight with regards to the differences between the RTX versions. Too bad Harris didn't know how to market them. Jabari ZakiyaArticle: 66394
Antti Lukats wrote: > Marius Vollmer <mvo@zagadka.de> wrote in message news:<87ad3hp6w2.fsf@zagadka.ping.de>... > >>Imagine you want to have an FPGA board that has a USB port and no >>other connection (i.e., no other way to upload a bitstream). Can that >>FPGA bootstrap itself over the USB port? >> >>There would be a 'boot' bitstream in some flash on the board and the >>FPGA would be configured initially with that bitstream. The function >>of that bitstream would be to make the FPGA listen on the USB port for >>another bitstream that is then used to configure the FPGA for its real >>function. >> >>Can this be done? Without external memory (other than the boot >>flash)? > > > YES. but it is a little bit dangerous as the FPGA would rewrite the main > primary config and if the process is not succesful the system will be > totally dead. > > Altera Cyclone: doable with no tricks. > Atmel FPSLIC: use I2C port to repropgram the config memory appnote exists. > Xilinx: connect config memory JTAG to FPGA > > antti > www.openchip.org you could use one of the usb-serial/usb-parallel chips from ftdichip.com they have a bigbang mode that when connected to the config pins on the fpga could configure it, you won't even need a prom then. I haven't figured out if theres a smart way use all of the interface pins on the FTDI and at the same time be able to reconfigure. Guess you could have some logic in the fpga to pull its own "program" pin with a command send over usb? it shouldn't care if the rest of the config pins a toggling after configuration? -LasseArticle: 66395
Hi,
I recommend you take a look at Xilinx application note 646
(http://direct.xilinx.com/bvdocs/appnotes/xapp646.pdf).
Simon
Nicky wrote:
>Hello,
>
>I have to design a universal PCI card according to PCI spec 2.2 with
>33Mhz and 32 pins. However for several reasons I have to use a FPGA
>that is not 5V but only 3.3V tolerant. Since nearly all motherboards
>just offer 5V slots I have to make this card somehow 5V compliant. I
>thought of using a quickswith from IDT. Is this a good idea? What are
>the things I have to take care of when using this method? Are there
>any other ways to make my card 5V compliant?
>
>thanks+regards,
>Nicky
>
>
Article: 66396If you do not want to convert to Gray code, you can also sample it continuously and always compare the new sampled value with the previous one. If they are identical, they are both good, if not, just continue until you get a valid pair. This method may have a problem when your (continuous?) count rate and sample rate are so close together. There are several ways to solve your problem, but you must realize that this is a complex issue, not to be ignored. Peter Alfke =========================== > Problem is that no matter how you re-sample it, you are sending multiple > data bits (the counter output word) across clock domains, and you have the > potential of getting incorrect data. I faced a similar problem, and I chose > to convert the counter output to grey code, sample it in the new clock > domain, and then convert back to binary. With grey encoding, only one bit > changes at a time as you count up or down, so you cannot get incorrect data, > even when there is a race condition when you re-sample. > > Barry Brown > > "prav" <praveenkn123@yahoo.com> wrote in message > news:863df22b.0402172352.5886ed1c@posting.google.com... >> hi all, >> >> I have a counter running at 50 Mhz . Now i have to sample that counter >> at 77 Mhz. >> >> My question is can i sample the counter running at 50 mhz directly >> with 77 mhz clock or should i synchronize the 50 mhz counter to 77 mhz >> clock domain and then only sample it. >> >> what are the effects if i don't the sample the 50 Mhz counter and i >> directly sample with 77 Mhz. >> >> rgds, >> prav > >Article: 66397
>I have a counter running at 50 Mhz . Now i have to sample that counter >at 77 Mhz. > >My question is can i sample the counter running at 50 mhz directly >with 77 mhz clock or should i synchronize the 50 mhz counter to 77 mhz >clock domain and then only sample it. > >what are the effects if i don't the sample the 50 Mhz counter and i >directly sample with 77 Mhz. What do you expect to happen? Are you meeting setup and hold times? If not, you might get any sort of answer, including metastability. I don't know of any easy way to do what I think you want to do. I would probably make a duplicate counter running off the 77 MHz clock and only enable it at 50 MHz. That is, send the LSB of the 50 MHz counter through the classic double FF synchronizer and then use any change in that signal as an enable pulse for the 77 MHz counter. That will give you several cycles of delay. You can reduce that some with a bit of work. Or figure out how much delay there is and correct in software. Or ... -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 66398
Thank you for your answer. In the meanwhile I already read all the threads I could find in this newsgroup concerning this topic. Your PCI-card is a universal card as well. In a 5V PCI slot the Quickswithes transfer 5V to 3.3V in one direction and the other way round in the other direction but what does the Quickswith do in a 3.3V slot? And I have another question. Somewhere in a newsgroup message I read that for universal PCI cards it is necessary to store 2 different bitfiles in an EEPROM and configure the PCI-FPGA depending on the voltage. That is to say 3.3V needs another configuration than 5V. Is this true? If yes, why? Anyway I can't do that since I use a Lattice FPGA which provides an internal EEPROM and my board is not going to have an external one additionally. I planed to use the PCI clock and put it into a PLL in the PCI-Core Lattice and consequently distribute the PLL-generated clock to other devices on my PCI card. I read that on your board the PCI-Clk is also routed to a PLL and is available for user logic. However, I read that this is maybe not a good idea since according to the PCI-spec it is possible that the PCI-clk is 0-33 MHz. On the other hand with an external oscillator there are much more problems with synchonisation. How did you tread this problems? Does the Altera Cyclone provide intern FIFOs with 2 different clocks? I hope you can help me again + best regards > > Nicky, do a google groups search on this newsgroup for some > discussions on this. > > My Cyclone PCI board (details on web site) uses Quickswitches > and appears to work flawlessly. > > This approach isn't actually compliant with the PCI spec which > stipulates 1 load per net, but I met the capacitance limits > and inspection shows clean transitions on the bus. > > Hope this helps, > > Nial > > ------------------------------------------------ > Nial Stewart Developments Ltd > FPGA and High Speed Digital Design > www.nialstewartdevelopments.co.ukArticle: 66399
Does anyone know where I can download the source to the NIOS GNU toolchain? Altera's web site gives some instructions: http://www.altera.com/support/kdb/rd11272000_7307.html But when logging in to the FTP site, I can only see empty directories. Any suggestions? Cheers, JonB
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