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Bassman59a@yahoo.com (Andy Peters) writes:
> "Subroto Datta" <sdatta@altera.com> wrote in message news:<JYaAb.3672$2C5.2593@newssvr33.news.prodigy.com>...
>
> >
> > A VHDL Test Bench File is the same as a standard VHDL test bench file, saved
> > with a .vht extension.
> >
>
> Why do vendors insist on using non-standard extensions for VHDL (and
> Verilog) source files? (Altera's not the only one.)
>
> Emacs, for example, knows that a .vhd file is VHDL and a .v file is
> Verilog. It doesn't know about a .vht file, unless I go and tell it.
> ModelSim recognizes .vhd and .v files but doesn't know from .vht
> files.
>
> The solution, of course, is to rename the files created by the tools.
>
For emacs , the solution is to stick this sort of thing in your .emacs
file:
(setq auto-mode-alist (append '(("\\.vht?$" . vhdl-mode)) auto-mode-alist))
Tweak the "vht" to suit...
Cheers,
Martin
--
martin.j.thompson@trw.com
TRW Conekt, Solihull, UK
http://www.trw.com/conekt
Article: 64101
Hi,
I want to make a block-based design using megafunctions and other
primitives of QuartusII 3.0. The design is to dived a bits stream to
even bits stream and odd bits stream.
/ d0,d2,d4,...
d0,d1,d2,d3,d4,d5... /
\
\ d1,d3,d5,...
Please give me some hints.
Thanks
Article: 64102
zhao wrote:
> I want to make a block-based design using megafunctions and other
> primitives of QuartusII 3.0. The design is to dived a bits stream to
> even bits stream and odd bits stream.
> / d0,d2,d4,...
> d0,d1,d2,d3,d4,d5... /
> \
> \ d1,d3,d5,...
How about a counter on rx_clk running 0,1,0,1,0,1,...
with its Q going to shiftA enable
and not Q going to the shiftB enable.
Both shifters also on rx_clk.
Note that you don't need to
bother with megafunctions
for shifters and counters.
-- Mike Treseler
Article: 64103
ranbow wrote:
> I use foundation2.1i to do simulation.
Using modelsim?
> My design has passed functional simulation.
Post the code.
> how to synchronize the reset pulse in the testbench?
You could deassert reset on the falling edge of the clock.
-- Mike Treseler
Article: 64104John Williams wrote: > Hi Pierre, > > > So, what I was hoping to get is either suggestions about how I might > > measure these delays, or, if someone has already measured/received > > this information, the actual min:typ:max board delays between memory > > and FPGA. > > I can't answer your question directly, but can offer a set of numbers > (parameters and constraints etc) for the EDK-provided DDR controller > that work on the v2mb1000 board... perhaps you can extract what you > need from these? > > Regards, > > John > (sound of hand slapping forehead) Thanks for the idea, I should have thought of that myself... I already have the EDK and all associated pcores, so I'll see what I can get from that (unless you have stuff that isn't in the vhdl files?). Of course, I always prefer to know as much as I can about the tools I use, so if anyone has the information, I'd still be interested in getting it. Thanks again, -- Pierre-Olivier -- to email me directly, remove all _N0SP4M_ from my address --Article: 64105
ALuPin wrote:
> Hi Mike,
>
> ok let's consider vcom and vsim from the command line ...
> what does I learn from it? :o)
Well, let's try it and see:
61 steptoe Mon Dec 15 /usr0/tres/marge/fpga/fr/vhdl > vcom
Model Technology ModelSim SE vcom 5.7c Compiler 2003.03 Mar 13 2003
Usage: vcom [options] files
Options:
-help Print this message
-version Print the version of the compiler
-work <path> Specify library WORK
-87 Disable support for 1076-1993
-93 Enable support for 1076-1993
-check_synthesis Check for compliance to some synthesis rules
-debugVA Print VITAL cell optimization information
-defercheck Defer all compile-time range checking on constant index and
slice expressions until run time
-explicit Resolve resolution conflicts in favor of explicit functions
+acc[=<spec>][+<entity>[(<architecture>)]]
Enable access to objects indicated by <spec> when
optimizing with -O4 or -O5, for processes merged
under certain conditions, where <spec> is the
character:
v (variables, constants, and aliases).
Optionally, enable access only for specific entities
and their associated architectures.
-f <path> Specify file containing more command line arguments
-gen_xml <entity> <output>
Output (into a file) the interface definition of the
specified entity in XML format.
-force_refresh Force Refresh library image from .dat file(s) even if
there are errors
-ignoredefaultbinding
Do not generate a default binding during compilation
-ignorevitalerrors Ignore VITAL compliance errors
-just eapbc Compile only selected design unit kinds
(e=entity, a=arch, p=package, b=body, c=config)
-line <lineNum> Specify starting line number
-lint Perform lint-style checks
-no1164 Disable optimization for the std_logic_1164 package
-noaccel <pname> Disable optimization for the specified package
-nocasestaticerror Suppress case static warnings
-nocheck Disable run-time range and index checks
-nodebug Do not put symbolic debugging information into library
-noindexcheck Disable run-time index checks
-nologo Disable startup banner
-norangecheck Disable run-time range checks
-novital Disable all VITAL optimizations
-novitalcheck Disable VITAL Level 1 compliance checking and optimizations
-nowarn <number> Do not flag warnings for the warning number specified
-O0 Disable optimizations
-O1 Enable some optimizations
-O4 Enable most optimizations (default)
-O5 Enable additional compiler optimizations
-pedanticerrors Enforce strict static checks
-performdefaultbinding
Enable default binding when it has been disabled with the
RequireConfigForAllDefaultBinding modelsim.ini variable
-quiet Disable 'Loading' messages
-refresh Refresh library image from .dat file(s)
-s Do not load package standard
-skip eapbc Compile all but selected design unit kinds
(e=entity, a=arch, p=package, b=body, c=config)
-source Print the source line with error messages
62 steptoe Tue Dec 16 /usr0/tres/marge/fpga/fr/vhdl >
Article: 64106
Hi,
I'm looking for a PCI board with multiple high-capacity FPGAs
(preferably Virtex2/Virtex Pro) and expansion connectors for
user-designed daughterboards.
The FPGAs should be completely contained on the PCI card - no interface
cards to an external whiz-bang box.
I'm already aware of boards from the DINI group which are pretty close
to meeting my needs. Any other ideas.
Paul
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Article: 64107You can remove the cost variable from the equation. Check www.opencores.org. They offer open source code for numerous cores, including a MAC PHY with associated test bench, and documentation. According to the "Status Log" for this core, it has been already tested in HW, and has been used in several commercial implementations. The reasons for implementing functions in FPGA vs discrete IC implementation, are all very generic : [1] Probable reduction in IC count, probable associated cost reduction, and probable increase in reliability. [2] Eliminate future redesigns of PWB when an external part experiences end-of-life. [3] Ability to "contain" majority of digital logic within single device simplifies clock domain management for synchronous design - ie. moves from a PWB/chip-to-chip problem to a single chip problem .. where it is much easier to manage. -- Regards, John Retta Owner and Designer Retta Technical Consulting Inc. email : jretta@rtc-inc.com web : www.rtc-inc.com "Martin" <ma_d@freenet.de> wrote in message news:8c88ba05.0312121258.7e68dc7c@posting.google.com... > Hi all! > > Can someone tell me the advantages and disadvantages of an ethernet > MAC core implemented in a FPGA for a System On Chip? > > Why to buy a lincese for several thousand dollar for an ethernet MAC > core and there is also an external PHY chip on the board? > There are also external chips which combine the MAC and the PHY layer. > > Thanks > > MartinArticle: 64108
Eric Crabill <eric.crabill@xilinx.com> wrote in message news:<3FDE4A33.B951D2B8@xilinx.com>... > Hi, > I can't tell you how many times I stabbed my fingertips with > the DIP device pins while putting this together. Here's hoping > your XC2000's are PLCC or SOJ!!! > > Eric Hi, Yeah, for me that's the biggest advantage of surface mount parts, I haven't had a 0.1" spaced row of puncture wounds for over 10 years!! cheers, Syms.Article: 64109
John Retta wrote: > You can remove the cost variable from the equation. > Check www.opencores.org. They offer open source code > for numerous cores, including a MAC PHY I found the MAC, but the only PHY listed is for USB. -- Mike TreselerArticle: 64110
On 16 Dec 2003 18:11:50 GMT, Paul Urbanus <urbpublic@hotmail.com> wrote: >Hi, > >I'm looking for a PCI board with multiple high-capacity FPGAs >(preferably Virtex2/Virtex Pro) and expansion connectors for >user-designed daughterboards. > >The FPGAs should be completely contained on the PCI card - no interface >cards to an external whiz-bang box. > >I'm already aware of boards from the DINI group which are pretty close >to meeting my needs. Any other ideas. > >Paul Try here for a little list: http://www.fpga-faq.com/FPGA_Boards.shtmlArticle: 64111
Googling web & usenet didn't provide answer or pointers - so here it goes: We have a fully tested design on fat Xilinx FPGA. Must go to ASIC, 0.18 or better. Relatively simple design, 3 clock domains, 300K gates. The only interface is USB, so very low pin count. If the foundry doesn't have USB phy in standard lib, we'll interface external phy. The question is - how long does it take - how many months ? We will farm that out, but I need some realistic idea about time between giving cash and working FPGA code to this outsourcing entity until we get first chips in sample quantities. I fully understand that each project is different, but feel uncomfortable with sales' quotes - I'd like to hear real experiences. And, BTW, are fabs busy these days or are they in mood for deals ?Article: 64112
That is correct. No Phy. My mistake in original email. -- Regards, John Retta email : jretta@rtc-inc.com web : www.rtc-inc.com "Mike Treseler" <mike.treseler@flukenetworks.com> wrote in message news:3FDF7EEB.7060509@flukenetworks.com... > John Retta wrote: > > You can remove the cost variable from the equation. > > Check www.opencores.org. They offer open source code > > for numerous cores, including a MAC PHY > > I found the MAC, but the only PHY listed is for USB. > > > -- Mike Treseler >Article: 64113
Xilinx seems to have launched a new architecture - ASMBL. There is no information except a news article. Can we have more info??? Is anyone from Xilinx Listening????Article: 64114
On Thu, 11 Dec 2003 23:38:51 +0000, Gus Baldauf wrote: > Hi, > > does anyone know if the Xilinx 6 tools work on Red Hat Enterprise or Fedora? > > I see this note on the Xilinx web site: > > RedHat 7.3 and 8.0 are supported for the 6.1i Release. > > RedHat 9.0 supports the Linux environment variable "LD_ASSUME_KERNEL=2.4.1" > which allows version 9.0 to run applications that are compatible with previous > versions of RedHat. This environment variable will allow ISE 6.1i to run, but > it is not supported or tested by Xilinx. > > Thanks, Gus Should work fine, I'm using Mandrake 9.2.Article: 64115
I deasserted reset on the falling edge of the clock and the problem
"insufficient RECOVERY time after async CLEAR,missing time 1.6ns" has
been solved.Thank you.
but another error message still appeared.The tool i use isn't
modelsim.
The following is the source code of the multiplier:
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity m13x10v is
port (
ai: in STD_LOGIC_VECTOR (12 downto 0);
bi: in STD_LOGIC_VECTOR (9 downto 0);
clk:in std_logic;
product: out STD_LOGIC_VECTOR (22 downto 0);
done: out STD_LOGIC
);
end m13x10v;
architecture m13x10v_arch of m13x10v is
begin
process(clk,ai,bi)
variable a,b,m:std_logic_vector(12 downto 0);
variable count:integer;
begin
if clk'event and clk='1' then
a:=ai;
b:="000"&bi;
m:="0000000000000";
done<='0';
for I in 0 to 12 loop
if a(0)='1' then
m:=m+bi;
end if;
a:=m(0)& a(12 downto 1);
m:='0'& m(12 downto 1);
end loop;
product<=m(9 downto 0)&a;
done<='1';
end if;
end process;
end m13x10v_arch;
You can check it and do simulation.
Article: 64116I don't think there will be any more public domain data for a while. Parts are similarly unlikely be around for a few months. If you have a serious design interest then the best approach will be to approach your FAE who may able to arrange early access via a NDA. We are still coming terms with the new family ourselves. But the main details that have been released indicate that their is a modular fabric. With this fabric Xilinx can produce multiple variants of a given die size allowing them target particular market sector needs. John Adair Enterpoint Ltd. Xilinx Xperts Partners This message is the personal opinion of the sender and not that necessarily that of Enterpoint Ltd.. Readers should make their own evaluation of the facts. No responsibility for error or inaccuracy is accepted. "Rahul Khanna" <rahulkh888@yahoo.com> wrote in message news:7897cd1e.0312161940.17e89bcb@posting.google.com... > Xilinx seems to have launched a new architecture - ASMBL. There is no > information except a news article. Can we have more info??? Is anyone > from Xilinx Listening????Article: 64117
> The question is - how long does it take - how many months ? We will > farm that out, but I need some realistic idea about time between > giving cash and working FPGA code to this outsourcing entity until we > get first chips in sample quantities. Give your design house a month, and the fab 6-8 weeks. Cheers, JonArticle: 64118
Paul Urbanus <urbpublic@hotmail.com> wrote in message news:3fdf4ae6$2_4@news.uncensored-news.com... > Hi, > > I'm looking for a PCI board with multiple high-capacity FPGAs > (preferably Virtex2/Virtex Pro) and expansion connectors for > user-designed daughterboards. > > The FPGAs should be completely contained on the PCI card - no interface > cards to an external whiz-bang box. > > I'm already aware of boards from the DINI group which are pretty close > to meeting my needs. Any other ideas. It sounds like one of Nallatech's boards is exactly what you're looking for. www.nallatech.com Nial. ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design www.nialstewartdevelopments.co.ukArticle: 64119
Hi all, Is that possible to invert a signal in the Xilinx .ucf file (thinking an input or output signal on a PAD)? if yes, which syntax? Thanks in advance, Laurent Gauch www.amontec.com ------------ And now a word from our sponsor --------------------- For a secure high performance FTP using SSL/TLS encryption upgrade to SurgeFTP ---- See http://netwinsite.com/sponsor/sponsor_surgeftp.htm ----Article: 64120
Hello, Running the module generator gives you two .vhd files. One is the generic component declaration for the P&R tool. One file has the name xxxxx_sim.vhd! You need to import this file from the ispLEVER project navigator for the functional simulation! At least make sure that the file name of the init file matches the GENERIC declaration in the component declaration and in the instantiation! Than it should work. Best Regards Joerg SiemersArticle: 64121
Just changing the Subject: to what is should have been ... > Googling web & usenet didn't provide answer or pointers - so here it > goes: > > We have a fully tested design on fat Xilinx FPGA. Must go to ASIC, > 0.18 or better. Relatively simple design, 3 clock domains, 300K gates. > The only interface is USB, so very low pin count. If the foundry > doesn't have USB phy in standard lib, we'll interface external phy. > > The question is - how long does it take - how many months ? We will > farm that out, but I need some realistic idea about time between > giving cash and working FPGA code to this outsourcing entity until we > get first chips in sample quantities. > > I fully understand that each project is different, but feel > uncomfortable with sales' quotes - I'd like to hear real experiences. > > And, BTW, are fabs busy these days or are they in mood for deals ?Article: 64123
B. Joshua Rosen wrote: > Should work fine, I'm using Mandrake 9.2. I get the following error when I run the GUI setup. [root@quark cdrom]# ./setup Wind/U Error (294): Unable to install Wind/U ini file (/mnt/cdrom/data/WindU). See the Wind/U manual for more details on the ".WindU" file and the "WINDU" environment variable. Wind/U X-toolkit Error: wuDisplay: Can't open display ************ setup done! *************** -GusArticle: 64124
ranbow wrote: > I deasserted reset on the falling edge of the clock and the problem > "insufficient RECOVERY time after async CLEAR,missing time 1.6ns" has > been solved.Thank you. > > but another error message still appeared.The tool i use isn't > modelsim. > . . .code deleted > > You can check it and do simulation. Post your vhdl testbench, and I would be happy to do that. The problem I see right away is that your variables b and count are never used, and there are no comments describing how you expect these shifts and adds to work. If this is an industrial application, consider using an fpga with a built-in multiplier. -- Mike Treseler
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