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"SneakerNet" <nospam@nospam.org> wrote in message news:<Qf%ib.178724$JA5.4476502@news.xtra.co.nz>... > Hi All > > Has anyone got this going fully (using the VB code from the site)? I'm still > stuck *wawawa* > Pls reply to this post.. how far did you get? is the USB device enumerated? I only did verify that the synthesis is ok 'out of box' so I assume the the VB project should also be OK, but I had no reasons to check the project in more detail. anttiArticle: 61926
Peter Alfke wrote: > John, the last time Xilinx printed a data book covering all our > programmable devices was in the year 2000. Thanks for the run. It's fun to look at the old data books from time to time. All the way back to the one with 'counter examples' ;-) An increase in clock speeds can be detected.Article: 61927
thanks for your advice, we will try this out. greetings dennis Sandeep Kulkarni schrieb: > Hello, > One of the possibility could be due to interference on the JTAG port you can > try the following to see if it resolves the problem: > 1. Provide a pull up on the JTAG pins > 2. Use the security bit, by which the contents cannot be read or changed, > the device can only be erased. > > Regards > Sandeep > "Dennis Binder" <dennis.binder@ipm.fhg.de> wrote in message > news:bmgeum$bvb$1@news.BelWue.DE... > >>Hello, >> >>we encounter problems with a XC18v01. >>In which way is it possible, that the prom loses >>information ? >>Most time everything works fine. But after delivering >>the mashine to the customer, the content of the XC18v01 has changed. >>We have no idea how this can happen. >>All the JTAG-Signals of the prom are left open and we supply the >>whole electronic with two seperated external power-supplies (3.3V 5V). >>3.3V for FPGA and Prom. >>5V for the digital electronic which interfaces to the FPGA. >> >>I would be glad if anybody can help ! >> >>Dennis >> > > >Article: 61928
Uwe Bonnes wrote: > > rickman <spamgoeshere4@yahoo.com> wrote: > : Peter, thanks, but we have had this conversation several times. None of > : the Virtex or Spartan II devices can be used in this socket because of > : the high start up currents. > > For Spartan II the specifications for the startup current for recent silicon > has been revised some days ago. Do they still not meet your requirements. No, the requirement only dropped from 2.0 Amps to 1.5 Amps at the industrial temp range. This would require the power converter to be larger than the chip! This section of the board is our "low power" section and the power converter will supply a *total* of 250 mA at 2.5 volts. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 61929
An LFSR output is only "random" for a single bit out per clock. The
remaining bits are delayed copies of the first bit. In order to use an
LFSR and really have a random stream of 3 bit numbers you'd need to clock
it 3x per die. If you go further to reject 'illegal' combinations, then
you are skewing the probabilities of the legal combinations so that they
are no longer uniform.
jetmarc wrote:
> > I'm trying to make an electronic dice (3 die). Basically the dice has
> > 3 seven-segment displays and the 3 dice values will run randomly so
> > that we would always get different values combinations. However I
> > tried and was unable to write the program in VHDL .
>
> Use an LFSR type pseudo random number generator (PRNG). [you will find
> a lot of documentation and VHDL example code in the crypto community,
> just google for the two acronyms].
>
> Clock it at an arbitrarty rate. Write VHDL code to convert the
> output of the PRNG into dice values. Probably the easiest is to take
> 3 bits of output to form 1 dice value (0-5 => 1-6) and flag the other
> states as illegal. Clocking the PRNG should not stop until all 3 dice
> are legal. That solves the bias-by-mapping problem without adding
> lots of complexity to the logic.
>
> Write code to output the dice value on the 7-seg LCD.
>
> Write code to stop the PRNG on user request (respecting the legal
> state thing mentioned above).
>
> Quite easy once you know how to do the "random" portion of it.
>
> Marc
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 61930"Symon" <symon_brewer@hotmail.com> wrote in message news:a28bc07f.0310141330.6158537d@posting.google.com... > Jonathan, > Please pay attention to the OPs spec. He/she said 'randomly'. This > implies the measurement of some random process, I suggest radioactive > decay measurement is the preferred solution. My humblest apologies to all, and the OP in particular. You are of course quite correct. Unfortunately, this makes the problem even harder. As I'm sure you're aware, standard methods for detecting the randomness of radioactive decay mandate the use of a cat, a sealed box and a vial of some toxic substance. Since the cat has a 0.5 probability of survival in each measurement to determine one bit, and a 6-position die requires an average of approximately 2.5849625007211561814537389439478 bits of data, it's clear that this mechanism will entail a mean loss of 1.2924812503605780907268694719739 cats per displayed value, or nearly 4 cats per 3-dice roll. In order to achieve this with a 20% margin of spare bandwidth, it's clearly necessary to use CAT-5 cable for all the interfaces. > This is why Xilinx offer radiation hardened devices > specifically so people can make reliable unbiased dice. > (It's no coincidence the chips are also called 'dice'.) > Note these parts are not usually offered in BGA packages, > but in leaded ones. The lead protects against radiation. Superb. ROFL. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 61931
Jim Granville wrote: > > rickman wrote: > > > > "José F. da Rocha" wrote: > > > > > > Hello. > > > > > > I’m new at the FPGA/CPLDs world and I’m currently subscribed to > > > receive Xilinx email communications. > > > > > > I would like to know if is there some FPGA/CPLD incorporating some few > > > analog functions or analog blocks like instrumentation amplifiers, > > > OPerational AMPlifiers/(analog amplification), ADCs > > > (Analog-to-Digital-Converter) and DACs? > > > > > > Thank you very much if you are kindly enough to answer. > > > (jose_rocha@yahoo.com) > > > > There are two devices you might be interested in. One is an MCU with > > programmable digital and analog blocks made by Cypress Semi. This is > > not really an FPGA since they don't make it easy for you to design your > > own digital functions. They used to, but they seem to have gone to a > > canned module approach where you have lots of standard functions to > > choose from. > > Did you see info that documented this ? - all I ever saw was 'marketing > arm waving' > and I was looking for better detail, on just what was SFR based, and > what was programmable logic in the true sense. I don't understand. What are you looking for documentation on; the chips being ready or being programmable? Originally, when they first came out, you could program the digital and analog blocks yourself. But I think the rules were very complex and people objected to the limited amount of logic and capability for a single block. So they went to a marketing approach where they predesign function blocks and you pick the ones you need. BTW, I don't know what SFR means. > > But I think the digital blocks are easier to work with > > than the analog blocks, so you might be able to do what you need. > > > > The other chip is an FPAA (field programmable analog array). This is an > > analog analog (pun intended) to digital FPGAs. I don't know a lot about > > them, but a google search should tell you the maker(s) and you can read > > up. > > > > AFAIK, there are no chips that combine programmable digital and analog > > functions on one chip. > > Well, none that do it with any performance.... > > The FPAAs I've seen have very poor analog numbers, and high prices. > > Lattice have a power-sequencer device, that has a SPLD, and voltage > comparator / timers - but costs a lot more than a 16V8 and LM339's > > STm have devices with uC + ADC / PWM and 16-32 Macrocell CPLDs Perhaps I did not understand what is being sought. None of these has "programmable" analog. I was not aware of the STm parts. But then I find their web site nearly impossible to use. > > The processing technologies are different enough > > that this would be a poor tradeoff and would be neither a good digital > > or a good analog chip. Eventually when FPGAs have gotten dense enough > > that they are mostly overkill for many apps, they will sacrifice digital > > speed and density for the added features of built in analog functions. > > But don't hold your breath. And don't expect the analog functions to be > > programmable, at least not at first. > > There are devices that combine uC+FLASH+PGA+24 bit ADCs/ 16 Bit DACS, > that are impressive indications of what IS possible, but they > come from very experienced ANALOG companies. Yes, but these chips are not using cutting edge digital. An 8051 is not a chalenge in any sense. The FPGA vendors currently have no interest in chips that are not 90 nm, fast as hell, etc... But as the market matures, this can change. We may see the FPGA vendors start to develop chips that have more than just programmable logic (or built in CPUs). -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 61932
Hi , Following web page has a complete explanation on Linker scripts. Hope you find this useful. http://www.delorie.com/gnu/docs/binutils/ld_6.html bye RAM Tom Tassignon <t_t_1232000@yahoo.com> wrote in message news:<2tonovsmpm3lnktq61r49g7d832t8euhea@4ax.com>... > Hi, > I am new to linker scripts. Can someone explain me program headers > (phdrs) ? > > Thanks, > > TomArticle: 61933
Hi, We have found the problem and this might interest somebody here so I explain the reasons of the voltage falling : It was simply because we put too many bypassing capacitors around the FPGA ! The virtex II datasheet is asking for many capacitors to have good linearity in the fpga voltages, but our power supply was not enough strong to support the current when we power on the board. Etrac. etraq@yahoo.fr (etrac) wrote in message news:<c99b95c7.0309150215.32a211e8@posting.google.com>... > At poweron I think the FPGA is not programmed ! It is in boundary scan > mode (pins M0-M1-M2), but I can't access to it with JTAG because the > voltage isn't sufficient. So I'm sure the FPGA is free ! > > There are some other components on the board, such as DSPs, they have > independant power supplys, but they are connected on some FPGA IOs. Do > you think they can disturb the FPGA at poweron ? My meaning was that > the FPGA IOs were tristated at poweron, nevertheless could they be > active when core or IO voltage are not yet stabilized ? > > etrac > > Austin Lesea <Austin.Lesea@xilinx.com> wrote in message news:<3F5F3C37.9758AF5F@xilinx.com>... > > etrac, > > > > Sounds broken. > > > > Virtex II and II Pro have no power on current surges whatsoever. > > > > Are you sure that you are not programming it to do something? Like all > > IOs are DCI HSTL input terminations (~54 mW each IO, 17 mA)? One hundred > > of these IOs programmed this way makes ~ 1.7 amperes, and 5.4 watts. > > > > The delay one one second is billions of times faster than the logic works, > > so it is unlikely it is the part doing something, it is more likely > > programming has just completed..... > > > > Open a hotline case. > > > > Austin > > > > etrac wrote: > > > > > We want to power on a Virtex II xc2v3000 FPGA (Xilinx). The core power > > > seems to work correctly (VccInt = 1.5V ; I<100mA), but VccAux and VccO > > > are asking too much current (> 1.5A) for a long time. This occurs > > > approximatively 1 second after the power is on. > > > We have a current limitation power supply, so the VccAux/VccO voltage > > > fall at nearly 1.5V, that is to say that the FPGA needs very much than > > > 1.5A .. > > > > > > Does anybody ever had this kind of issue ? Or do you know a possible > > > cause of this event ?Article: 61934
Hi, Im looking for a regulator for the 1.5 and 1.2 Volt. I have a insight board as reference which has 2 times a 1.5 amps regulators for the 1.5 V. I would like to have one regulator on my own design. I'm going to use the following components: xc2v1000 and xc3s400 later. Yours Bram -- ================================================== Bram van de Kerkhof OCE-Technologies BV Building 3N38 St. Urbanusweg 43, Venlo, The Netherlands P.O. Box 101, 5900 MA Venlo ================================================== Direct dial : +31-77-359 2148 Fax : +31-77-359 5473 ================================================== e-mail : mailto:bvdk@oce.nl ================================================== www : http://www.oce.nl/ ==================================================Article: 61935
I am designing a mainboard which contains a Xilinx FPGA, and contains connectors for hot-swap daughter card plug-in modules. The mainboard Xilinx (Spartan IIe) has direct I/O connections (LVPECL, LVTTL) to these daughter card connectors. Hot swap design guidelines seem to apply to Power/GND pins, and power ramp up on hot-swap modules. Are there any issues with Xilinx I/O tied directly to a connector with a hot-swap module? Plug-in modules do not contain any programmable devices. Regards John R.Article: 61936
You may also want to use the DDR output flops in the IOB to
output the clock rather than running them straight through
a simple output buffer. This keeps the clocks on dedicated
clock lines and eliminates a bunch of skew. There are several
app-notes that show this, look at some of the DDR memory ones
for examples.
Here's code a used to drive a clock out to some synchronous SRAM.
Note by swapping the D0 and D1 values you can invert the clock.
// infer a DDR type I/O cell for low clock skew
FDDRRSE uddr_clk(
.Q (sram_clk),
.C0 (g_sr_clk),
.C1 (~g_sr_clk),
.CE (1'b1),
.D0 (1'b1),
.D1 (1'b0),
.R (1'b0),
.S (1'b0)
);
John Providenza
Austin Lesea <Austin.Lesea@xilinx.com> wrote in message news:<3F8C4846.62042276@xilinx.com>...
> Markus,
>
> Keep the OBUFs to the right or left sides, and near the center of the parts
> (least H Clock Tree skew from IOB to IOB <<50 ps).
>
> Worst is to have them in the center of the top or bottom, and go to the
> extreme right or left corners (~500 to 600 ps in 2VP100 skew).
>
> You can infer the skew on the hclck tree by examining delays in FPGA editor.
>
> Austin
>
> Markus Meng wrote:
>
> > Hi all,
> >
> > a simple question:
> >
> > We intend to use a DCM in a Virtex-II Pro to drive multiple OBUF's but
> > only ne feedback signal - of course. What is the best way to minimize the
> > delay difference between the OBUF's?
> >
> > Any help would be appreciated.
> >
> > Markus
Article: 61937Jim, Various changes went into the new mask for the 300mm fab, so we were able to reduce (by design) the start up peak by more than 60%. This also allows for relaxing the dV/dt. SInce we figured out what causes this in Virtex II, we have had no POS (power on surge) issues in subsequent families. Unfortunately it required a complete redesign which is not possible for the older parts. Austin Jim Granville wrote: > Uwe Bonnes wrote: > > > > rickman <spamgoeshere4@yahoo.com> wrote: > > : Peter, thanks, but we have had this conversation several times. None of > > : the Virtex or Spartan II devices can be used in this socket because of > > : the high start up currents. > > > > For Spartan II the specifications for the startup current for recent silicon > > has been revised some days ago. Do they still not meet your requirements. > > Interesting. I see the Spartan IIE also had a tweak downwards, > and gained on dV/dT caveats. > MAX static currents are still not nice. > > -jgArticle: 61938
rickman wrote: > No, the requirement only dropped from 2.0 Amps to 1.5 Amps at the > industrial temp range. This would require the power converter to be > larger than the chip! This section of the board is our "low power" > section and the power converter will supply a *total* of 250 mA at 2.5 > volts. Did you see Austin Lesea's cunning trick of cycling the chip until it warms up and starts on lower power?Article: 61939
Rick, I understand. Industrial temp minimum current to power on cleanly is the toughest part of the specification, even with the mask changes that were made to improve things. The app note on the "kick start" circuit is the only other alternative we can offer. Storing up the charge required to supply the 1.5A does however require a fairly large capacitor, and it gets even larger and tougher at -40C where almost all caps are -30% to -80% less C (as the electrolyte freezes). AustinArticle: 61940
Bram, TI has a webpage pdf on how to power all Xilinx FPGAs. It lists linear regulators, switching regulators, and modules from 200 mA to 12 amperes (and greater). Micrel, Linear Tech, Power One, Summit Labs, Vishay, Analog Devices and many other have powering solutions for FPGAs, as well. These are the few who have come to San Jose in the last year to visit us, and go thru their line cards with us, provide us samples to test, etc. Contact your favorite from the list above, and they will be happy to provide you with a tested and working solution. Austin Bram van de Kerkhof wrote: > Hi, > > Im looking for a regulator for the 1.5 and 1.2 Volt. > > I have a insight board as reference which has 2 times a 1.5 amps regulators > for the 1.5 V. > > I would like to have one regulator on my own design. > > I'm going to use the following components: xc2v1000 and xc3s400 later. > > Yours Bram > > -- > ================================================== > Bram van de Kerkhof > > OCE-Technologies BV > Building 3N38 > > St. Urbanusweg 43, > Venlo, The Netherlands > P.O. Box 101, 5900 MA Venlo > ================================================== > Direct dial : +31-77-359 2148 > Fax : +31-77-359 5473 > ================================================== > e-mail : mailto:bvdk@oce.nl > ================================================== > www : http://www.oce.nl/ > ==================================================Article: 61941
A customer wants to input 10 bit data into a Xilinx Virtex-II at 800MHz. I've looked at XAPP265 which suggests that this should be possible, albeit with some effort. This seems to REAL close to the limit that the Xilinx parts could handle. Looking at the Altera "true-LVDS" pads, it seems like they may have a cleaner / more robust solution for this. Has anyone actually had experience doing this with a Xilinx Virtex-II or an Altera part? Any horror stories or other tips? Clearly, all the usual (unusual??) care with board layout, pin assignment, etc. is needed. Thanks! John ProvidenzaArticle: 61942
John, Youa re absolutely right! I failed to mention that you should always use the DDR FF for clock forwarding, as it has the best timing performance. Good catch. Austin John Providenza wrote: > You may also want to use the DDR output flops in the IOB to > output the clock rather than running them straight through > a simple output buffer. This keeps the clocks on dedicated > clock lines and eliminates a bunch of skew. There are several > app-notes that show this, look at some of the DDR memory ones > for examples. > > Here's code a used to drive a clock out to some synchronous SRAM. > Note by swapping the D0 and D1 values you can invert the clock. > > // infer a DDR type I/O cell for low clock skew > FDDRRSE uddr_clk( > .Q (sram_clk), > .C0 (g_sr_clk), > .C1 (~g_sr_clk), > .CE (1'b1), > .D0 (1'b1), > .D1 (1'b0), > .R (1'b0), > .S (1'b0) > ); > > John Providenza > > Austin Lesea <Austin.Lesea@xilinx.com> wrote in message news:<3F8C4846.62042276@xilinx.com>... > > Markus, > > > > Keep the OBUFs to the right or left sides, and near the center of the parts > > (least H Clock Tree skew from IOB to IOB <<50 ps). > > > > Worst is to have them in the center of the top or bottom, and go to the > > extreme right or left corners (~500 to 600 ps in 2VP100 skew). > > > > You can infer the skew on the hclck tree by examining delays in FPGA editor. > > > > Austin > > > > Markus Meng wrote: > > > > > Hi all, > > > > > > a simple question: > > > > > > We intend to use a DCM in a Virtex-II Pro to drive multiple OBUF's but > > > only ne feedback signal - of course. What is the best way to minimize the > > > delay difference between the OBUF's? > > > > > > Any help would be appreciated. > > > > > > MarkusArticle: 61943
John, It is definitely a challenge. Here are a few pointers (and yes we have done it, and tested it, but I can not speak for customers): 1) use IOBs that are best for clock skew to minimize that issue. These are left and right sides, adjacent, working out from the center. Using this topology, the hclk skew can be kept to less than ~ 50 ps. 2) get the flight time maps for the package you wish to use, so that pcb trace skew, package skew, can all be kept to less than 5 or 10 ps. There is a per bit deskew core that we offer, and this may also be a chosie you should consider, as it makes the layout, etc a lot easier. 3) use dynamic alignment (either our IP cores, or your own design) which will automatically find and keep the data in the center of the eye 4) be extremely careful with single ended IO switching (causes ground bounce which will cause jitter) be sure that all single ended IOs are keep away from the LVDS pairs 5) have to probably use faster speed grade than -4. I know of many designs using ~ 700 Mbs with -5 speed grade parts. You may want to consider V2P for this instead, (faster). 6) keep the design synchronous (ie one clock is used for all timing, or all clocks are related (ie x2, /2, /3, etc). 7) use the fixed phase shift to shift offending single ended IO switching away from the sample point of the LVDS eye, also good for large amounts of switching CLBs, too. This places the clock edge for logic and single ended IOs where the ground bounce will not interfere with the LVDS. Typical phase whift is ~270 degrees to ~300 degrees (or -60 to -90 degrees). 8) use two BUFG trees: one for clk0, and one for clk180 to minimize duty cycle distortion (also directly takes away from the timing budget) 9) all IO is done with DDR FF in the IOB Also check out the SPI POS 4 cores, and similar high speed cores in our IP lounge. 800 Mbs is no easy task, regardless of the chip. This is also known as "microwave" in some communities, and the signal integrity, pcb layout, and all the rest is as much or more of a challenge than the FPGA part of it. This is precisely why the MGTs (high speed gigabit serializer-deserializers) are becoming so popular. Austin John Providenza wrote: > A customer wants to input 10 bit data into a Xilinx Virtex-II at 800MHz. > I've looked at XAPP265 which suggests that this should be possible, > albeit with some effort. This seems to REAL close to the limit > that the Xilinx parts could handle. > > Looking at the Altera "true-LVDS" pads, it seems like they may have > a cleaner / more robust solution for this. > > Has anyone actually had experience doing this with a Xilinx Virtex-II > or an Altera part? Any horror stories or other tips? > > Clearly, all the usual (unusual??) care with board layout, pin > assignment, etc. is needed. > > Thanks! > > John ProvidenzaArticle: 61944
How about using one LFSR per die pip? Using the SRL16s in Xilinx chips (don't know A, sorry), that would mean somewhere around 9 slices (for 3x6 pips), plus overhead, decoding logic, etc..., if I'm not mistaken? Incidentally, would using different polynomials effectively (as far as the human is concerned) decorrelate the LFSRs? Or would varying lengths (16, 32, etc...) do the trick? Or even, would different seeds be enough? I've never gotten around to studying the math, and never been great with statistics anyway... Pierre-Olivier -- to contact me directly, remove the obvious from my email --Article: 61945
"Vinh Pham" <a@a.a> wrote in message news:ft4jb.12621$ZH4.10910@twister.socal.rr.com... > > It's a seven segment display, so it might be up to 1d16 > > ... > > > between 1d2 and 1d16. Bonus points for only allowing configurations > > where an actual polygon would make a legal die (all sides the same > > area). > > Whew. I was freaking out for a moment there. I thought there was a gap in > my gaming lore, that I had somehow gone through life ignorant of the > 16-sided die :_) Just because 16 sided dice aren't used doesn't mean they can't be done. I could supply three different types of 16 sided polyhedra, all with equal faces. I was, after all, responsible for getting the 30 sided die on the market (back in the summer of '82). Now it's FPGA design for me. - John_HArticle: 61946
> An LFSR output is only "random" for a single bit out per clock. The > remaining bits are delayed copies of the first bit. In order to use an There are two forms of an LFSR. One where the bits are just delayed versions and you have a huge adder that feeds the chain (good ol' Google says this is called the Fibonacci form). And there's another one where there are adders inbetween the registers so that the bits are not delayed versions of each other (called the Galois form). Even in the case of the Fibonacci form, I have a feeling that grabbing a few adjacent bits will still produce a "random" number. Of course it depends on what you consider random, and I don't know much about the measurements they use for that. > it 3x per die. If you go further to reject 'illegal' combinations, then > you are skewing the probabilities of the legal combinations so that they > are no longer uniform. Rejecting illegal combinations should be okay. The legal combinations will remain uniform. Unfortunately I don't know a good way to explain this. But you can take a six sided dice, reject values of 5 and 6, and have it act like a uniform four sided dice. The only problem with the rejection method is you're not guaranteed a valid value every clock cycle, which is no big deal in this human operated push button application, but for some deterministic applications, you can't afford to wait for a "reroll" of the number. --VinhArticle: 61947
"SneakerNet" <nospam@nospam.org> wrote in message news:<r%Fib.177618$JA5.4453818@news.xtra.co.nz>... > Hi John > I now remember that Altera provided a mp3 project with their Nios > Development Kit (APEX Edition). I wonder where I can find the source code > for that. > > Thanks ;o) > > Hi Sneaker, Send me an email to my business address: jkempa -at- altera -dot- com and I'll get the mp3 ref design for you via email. One of my colleagues has probably ported it to a more recent version of Nios to work on the newer Nios dev. boards. Jesse Kempa Altera Corp.Article: 61948
Hi, Are you looking for completed projects (i.e. bitstreams) just to test out a board for functionality, or are you looking for lab assignments for use with the XLA5? I have some lab assignments. Go check my website at http://www.engr.sjsu.edu/crabill and look at the lab assignments. These are for 4.2i, XST Verilog, with the D2E board, but if you contact me privately I can send you the same assignments for 2.1i, Aldec Schematics, with the XLA5 board. I used those last year... EricArticle: 61949
ram wrote: >Hi all, > I am interested in doing partial reconfiguration using Xilinx Virtex >2 pro, i am having a HW AFX xilinx prototype baord. >I tried the small bit manipulation method defined in Xilinx >application note >xapp290, with the simple example , Example 1 simple system desing from >xilinx EDK examples web page. >Ok , my desing is this, > I am using PPC405, and uartlite and gpio with uart continiously >writing some data in Hyper terminal and gpio is connected to four leds >and writing '1' to it >I tried to change the routing for the LEDs , I do have to mention >here, my board has 8 user LEDS, i changed the routing from upper half >to lower half and generated the partial bit stream. > The configuration frames are columns, so if the routing you are changing is in the same column as the PPC, UART, or any of their routing, they will probably stop. Steve >Everything goes well so far, but when i download this partial >bitstream into FPGA, my uart stops putting out data, but LEDS gets >rerouted and now the lower half LEDs o/p '1'. >I would like to know wether what i am trying to do was right, also if >anybody worked on small bit manipulations, I would appreciate their >comments and advice. >Thank you for the posting me a reply. >bye >Ram > >
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